™fiXtress Chip�Interconnection�Verificationfor�Chip�Vendors�&�Board�Level�Designers

Auto-Spotterfor�Electronic�Design�Errors

Designers'�Challenges Benefits

Solution

Digital� ICs�are�becoming� increasingly�complex,�with�up�to�thousands� of� pins,� making� manual� interconnection�verification�extremely�difficult� for�OEM�designers.� To� ease�the� task,� chip� vendors� provide� Reference� Designs�specifying� a� chip's� interconnection� to� its� peripheral�components.� However,� verification� of� the� reference�design's� compliance� with� the� chip� manufacturer's�reference� design� is� also� extremely� difficult,� due� to� the�complexity� and� lack� of� automated� tools� in� the� CAD/EDA�environment.

f iXtress �ASR� (Automatic � Schematic � Review) �Chip�Interconnection�Verification�module�performs� effective�auto-verif ication�of� a�particular� implementation's�compliance�with� the�Reference�Design� and�Chip� vendor�recommendations.�

fiXtress�ASR�uses� the�design�BOM�and�Netlist� as� input.� It�also�uploads�Part�Library�Models� in�order� to�obtain�useful�information�about�the�design�(See�Fig.�1).

The�module� checks� the� interconnection�of� two�or�more�complex� ICs� according� to� a� sequence�of� rules.� The�connection� is�performed�between�groups�of�pins,� such�as�the� interconnection� scheme�between� an�ASIC� and� a�memory� chip�DDR� (See� Fig.� 4),� or� the� interconnection�scheme�between�SoC,�CPU,� FPGA�and� surrounding�peripheral�chips.An� error� report� lists� the� schematic� errors� detected� in� the�interconnection�design,�classified�by�severity�levels.

Dramatically�shortens�verification�process�from�weeks�to�minutes

Performs�Automatic�instead�of�Manual�verification

Performs�more�effective,�accurate�and�reliable�verification�

Shortens�time�to�manufacturing�following�shorter�test�cycles

Increases�chip�reliability�by�eliminating�hidden�errors

Avoids�hazards�which�could�result�in�high�costs�and�loss�of�reputation

Saves�vendor's�time,�expenditures�and�effort�spent�on�checking�designs

�Fig.�1

5�Mazal�Eliezer�St.�Rishon-lezion�75101,�Israel +972-3-962-5911��� www.bqr.cominfo@bqr.com

BQR�Company

BQR� is� a� world� leader� in� reliability� analysis� and�maintenance� optimization� solutions� for� the� EDA�market.�BQR�software�tools�help�engineers�create�more� robust� and� reliable� products,� as� well� as�improving�the�design�process.

Throughout� its� 25� years� of� experience,� the�company�serves� leading�companies� in� Israel�and�worldwide,�including�Elbit,�IAI,�DSO,�Israel�Electric�Corporation,� Cisco,� Baker-Hughes,� IBM,� Philips,�Bombardier,� Schiphol� Airport,� Mobileye� and�others.�

Mobileye�Use�Case�

fiXtress�Chip�Interconnection�Verification�‒�How�it�Works

Mobileye,� a� leading� vendor� of� Vehicle� ADAS� (Automated�Driving� Assistance� System),� uses� fiXtress� Automatic�Schematic� Review� for� ADAS� systems� verification,� testing�the�electronic�chip�deployed�in�the�vehicle.��The�ADAS�test�performed�by� fiXtress� is� a� Common�Rule� Verification� Test�that�checks�the�inter�-connection�of�two�ICs,�according�to�a�sequence�of�rules.�Using�fiXtress�ASR,�Mobileye�verification�process�was�effectively�reduced�to�moments.

“With� fiXtress� ASR,� we� went� from� entire� days� of� manual�checks� to� an� effective� automated� process� lasting� just�several�moments.�Best�of�all,�now�we�can�be�sure�that�the�chip�is�used�correctly�by�every�single�car�manufacturer”.Israel�Bar,�Hardware�Design�Engineer,�Mobileye

fiXtress�Chip� Interconnection�Verification�module� is�based�on�a�logical� binary� tree� connectivity� check,� according� to� a� user�defined� sequence� (see� Figure� 2).� The� connectivity� check� is�performed� between� sets� of� functional� pins� (Groups).� The�software�performs�a�check,�and�uses�its�results�to�either�continue�with�additional�checks�or�exit,�signaling�an�error�or�success.The� test� sequence� configuration� is� performed� using� Group�definition�and�Sequence�definition�tables.

The�verification�results�are�displayed�on�the�screen�and�in�a�Log�file�(see�Fig.�3).

Chip�Interconnection�Verification�Results

�Fig.�2

�Fig.�4

�Fig.�3