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George Mason University
Data Flow Modeling ofCombinational Logic
ECE 545
Lecture 5
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Required reading
P. Chu, RTL Hardware Design using VHDL
Chapter 4 , Conc urrent S ignal As s ign m ent
Statem ents of VHDL
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3ECE 448 FPGA and ASIC Design with VHDL
Dataflow VHDL Design Style
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4
VHDL Design Styles
Components andinterconnects
structural
VHDL DesignStyles
dataflow
Concurrentstatements
behavioral(sequential)
Registers
State machines Instruction decoders
Sequential statements
Subset most suitable for synthesis
Testbenches
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Synthesizable VHDL
Dataflow VHDLDesign Style
VHDL codesynthesizable
VHDL codesynthesizable
Dataflow VHDLDesign Style
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Register Transfer Level (RTL) Design Description
CombinationalLogic CombinationalLogic
Registers
Todays Topic
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Data-flow VHDL
concurrent signal assignment ( )
conditional concurrent signal assignment(when-else)
selected concurrent signal assignment(with-select-when)
generate scheme for equations(for-generate)
M ajor instructions
Concurrent statements
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Data-flow VHDL: Example
xy
cins
cout
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Data-flow VHDL: Example (1)
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY fulladd ISPORT ( x : IN STD_LOGIC ;
y : IN STD_LOGIC ;cin : IN STD_LOGIC ;s : OUT STD_LOGIC ;
cout : OUT STD_LOGIC ) ;END fulladd ;
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Data-flow VHDL: Example (2)
ARCHITECTURE dataflow OF fulladd IS
BEGIN s
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Logic Operators
Logic operators
Logic operators precedence
and or nand nor xor not xnor
not
and or nand nor xor xnor
Highest
Lowest
only in VHDL-93or later
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Wanted: y = ab + cdIncorrecty
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RTL Hardware Design Chapter 4 14
E.g.,
status
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RTL Hardware Design Chapter 4 15
Signal assignment statement with aclosed feedback loop
a signal appears in both sides of aconcurrent assignment statement
E.g.,q
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Data-flow VHDL
concurrent signal assignment ( )
conditional concurrent signal assignment(when-else) selected concurrent signal assignment
(with-select-when)
generate scheme for equations(for-generate)
M ajor instructions
Concurrent statements
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Conditional concurrent signal assignment
target_signal
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Most often implied structure
target_signal
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RTL Hardware Design Chapter 4 19
2-to- 1 abstract mux
sel has a data type of boolean If sel is true, the input from T port is connected
to output.
If sel is false, the input from F port is connectedto output.
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RTL Hardware Design Chapter 4 20
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RTL Hardware Design Chapter 4 21
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RTL Hardware Design Chapter 4 22
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RTL Hardware Design Chapter 4 23
E.g.,
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RTL Hardware Design Chapter 4 24
E.g .,
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RTL Hardware Design Chapter 4 26
E.g .,
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Signed and Unsigned Types
Behave exactly likeSTD_LOGIC_VECTOR
plus, they determine whether a given vectorshould be treated as a signed or unsigned number.Require
USE ieee.numeric_std.all;
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compare a = bc Incorrect
when a = b and c else
equivalent to when (a = b) and c else
Correct when a = (b and c) else
Priority of logic and relational operators
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VHDL operators
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Data-flow VHDL
concurrent signal assignment ( )
conditional concurrent signal assignment(when-else) selected concurrent signal assignment
(with-select-when)
generate scheme for equations(for-generate)
M ajor instructions
Concurrent statements
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Selected concurrent signal assignment
with choice_expression select
target_signal
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Most Often Implied Structure
with choice_expression select
target_signal
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Allowed formats of choices_k
WHEN value
WHEN value_1 | value_2 | .... | value N
WHEN OTHERS
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Allowed formats of choice_k - example
WITH sel SELECTy
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RTL Hardware Design Chapter 4 36
Syntax
Simplified syntax:with select_expression select
signal_name
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RTL Hardware Design Chapter 4 37
select_expression Discrete type or 1-D array With finite possible values
choice_i A value of the data type
Choices must be mutually exclusive all inclusive others can be used as last choice_i
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RTL Hardware Design Chapter 4 38
E.g., 4-to-1 mux
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RTL Hardware Design Chapter 4 39
Can 11 be used to replace others ?
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RTL Hardware Design Chapter 4 40
E.g., 2-to-2 2 binary decoder
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RTL Hardware Design Chapter 4 41
E.g., 4-to-2 priority encoder
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RTL Hardware Design Chapter 4 42
Can we use -?
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RTL Hardware Design Chapter 4 43
E.g., simple ALU
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RTL Hardware Design Chapter 4 44
E.g., Truth table
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RTL Hardware Design Chapter 4 45
Conceptual implementation
Achieved by amultiplexing circuit
Abstract (k+1)-to-1
multiplexer sel is with a data type
of (k+1) values:c0, c1, c2, . . . , ck
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RTL Hardware Design Chapter 4 46
select_expression is with a data type of 5values: c0, c1, c2, c3, c4
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RTL Hardware Design Chapter 4 47
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RTL Hardware Design Chapter 4 48
E.g.,
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RTL Hardware Design Chapter 4 49
3. Conditional vs. selected signalassignment
Conversion between conditional vs.selected signal assignment
Comparison
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RTL Hardware Design Chapter 4 50
From selected assignment toconditional assignment
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RTL Hardware Design Chapter 4 51
From conditional assignment toselected assignment
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RTL Hardware Design Chapter 4 52
Comparison
Selected signal assignment: good match for a circuit described by a
functional table
E.g., binary decoder, multiplexer Less effective when an input pattern is given
a preferential treatment
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May over specify for a functional table
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RTL Hardware Design Chapter 4 54
May over -specify for a functional tablebased circuit.
E.g., mux
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MLU Example
l k
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MLU Block Diagram
B
A
NEG_A
NEG_B
IN0
IN1
IN2
IN3
OUTPUT
SEL1 SEL0
MUX_4_1
L0 L1
NEG_Y
Y
Y1
A1
B1
MUX_0
MUX_1 MUX_2
MUX_3
0
1
0
1
0
1
l
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MLU: Entity Declaration
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY mlu ISPORT(
NEG_A : IN STD_LOGIC;NEG_B : IN STD_LOGIC;NEG_Y : IN STD_LOGIC;
A : IN STD_LOGIC;B : IN STD_LOGIC;
L1 : IN STD_LOGIC;L0 : IN STD_LOGIC;Y : OUT STD_LOGIC
);END mlu;
MLU: Architecture Declarative
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MLU: Architecture DeclarativeSection
ARCHITECTURE mlu_dataflow OF mlu IS
SIGNAL A1 : STD_LOGIC;SIGNAL B1 : STD_LOGIC;SIGNAL Y1 : STD_LOGIC;SIGNAL MUX_0 : STD_LOGIC;SIGNAL MUX_1 : STD_LOGIC;SIGNAL MUX_2 : STD_LOGIC;SIGNAL MUX_3 : STD_LOGIC;
SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);
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ECE 448 FPGA and ASIC Design with VHDL
Modeling Common CombinationalLogic Components
Using Dataflow VHDL
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61ECE 448 FPGA and ASIC Design with VHDL
Wires and Buses
Si l
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Signals
SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);wire
a
bus
b
1
8
M i i d b
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Merging wires and buses
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
d
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Splitting buses
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL c: STD_LOGIC;SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
a
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65ECE 448 FPGA and ASIC Design with VHDL
Fixed Shifters & Rotators
Fi d Shift i VHDL
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Fixed Shift in VHDL
A(3) A(2) A(1) A(0)
0 A(3) A(2) A(1)
A>>1
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL AshiftR: STD_LOGIC_VECTOR(3 DOWNTO 0);
AshiftR
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Fixed Rotation in VHDL
A(3) A(2) A(1) A(0)
A(2) A(1) A(0) A(3)
A
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68ECE 448 FPGA and ASIC Design with VHDL
Buffers
Tri-state Buffer
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(b) Equivalent circuit
(c) Truth table
x f
e
(a) A tri-state buffer
00
11
01
01
ZZ
01
fe x
x f
e = 0
e = 1 x f
Tri-state Buffer
Four types of Tri-state Buffers
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x
e
(b)
x f
e
(a)
x f
e
(c )
x
e
(d)
Four types of Tri state Buffers
Tri state Buffer example (1)
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Tri-state Buffer example (1)
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY tri_state IS
PORT ( ena: IN STD_LOGIC;input: IN STD_LOGIC;output: OUT STD_LOGIC
);
END tri_state;
Tri state Buffer example (2)
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Tri-state Buffer example (2)
ARCHITECTURE dataflow OF tri_state ISBEGIN
output
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73ECE 448 FPGA and ASIC Design with VHDL
Multiplexers
2-to-1 Multiplexer
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2 to 1 Multiplexer
(a) Graphical symbol (b) Truth table
0
1
f s
w 0
w 1
f
s
w
0 w
1
0
1
VHDL code for a 2-to-1 Multiplexer
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VHDL code for a 2 to 1 Multiplexer
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY mux2to1 ISPORT ( w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;END mux2to1 ;
ARCHITECTURE dataflow OF mux2to1 IS
BEGINf
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Cascade of two multiplexers
s1
w 3
w 1
0
1
s2
w 2
0
1 y
VHDL code for a cascade ofl i l
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two multiplexersLIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux_cascade ISPORT ( w1, w2, w3: IN STD_LOGIC ;
s1, s2 : IN STD_LOGIC ;f : OUT STD_LOGIC ) ;
END mux_cascade ;
ARCHITECTURE dataflow OF mux2to1 ISBEGIN
f
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f
s1
w
0w1
00
01
(b) Truth table
w0
w1
s0
w2
w3
10
11
00
1
1
1
0
1
fs1
0
s0
w2
w3
(a) Graphic symbol
4-to-1 Multiplexer
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2-to-4 Decoder
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2 to 4 Decoder
0
01
1
10
1
y3
w1
0
w0
x x
1
1
0
1
1
En
00
1
0
0
y2
01
0
0
0
y1
10
0
0
0
y0
00
0
1
0
w1
En
y3
w0
y2
y1
y0
(a) Truth table (b) Graphicalsymbol
VHDL code for a 2-to-4 Decoder
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VHDL code for a 2 to 4 DecoderLIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY dec2to4 ISPORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END dec2to4 ;
ARCHITECTURE dataflow OF dec2to4 ISSIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGINEnw
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83ECE 448 FPGA and ASIC Design with VHDL
Encoders
Priority Encoder
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Priority Encoder
w0
w3
y0
y1
d
0 0 1
0 1 0
w 0 y 1
d
y 0
1 1
0
1
1
1 1
z
1 x x
0
x
w 1
0 1 x
0
x
w 2
0 0 1
0
x
w 3
0 0 0
0
1
z
w1w2
VHDL code for a Priority Encoder
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VHDL code for a Priority EncoderLIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY priority ISPORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;z : OUT STD_LOGIC ) ;
END priority ;
ARCHITECTURE dataflow OF priority ISBEGIN
y
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