1
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Static Timing AnalysisStatic Timing AnalysisInstructor:Instructor: 陳麒旭陳麒旭
Tel:Tel: 0303--5773693 ext.1495773693 ext.149Email:Email: [email protected]@cic.org.tw
2Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Timing AnalysisTiming AnalysisTiming Analysis
Dynamic Timing Analysis (DTA)Static Timing Analysis (STA)
3Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Dynamic Timing Analysis Dynamic Timing Analysis Dynamic Timing Analysis
So-called SimulationInput vectors are applied during the simulation timeSimulator calculates the logic value and delays
Disadvantages of DTAVirtually impossible to do exhaustive analysis
• Vector creation takes too long• Incomplete timing coverage
Hard to discern the cause of failure because the function and timing are analyzed at the same timeRequires more memory and CPU resources over STA
• Long simulation time• Capacity limited
4Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Static Timing Analysis (1/2)Static Timing Analysis (1/2)Static Timing Analysis (1/2)
A method for determining if a circuit meets timing constraints without having to simulate clock cyclesThree main steps
Break the design into sets of timing pathsCalculate the delay of each path (create timing graph)Check all path delays to see if the given timing constraints are met
IN QD
QN
QD
QN
CLK
OUT
5Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Static Timing Analysis (2/2)Static Timing Analysis (2/2)Static Timing Analysis (2/2)
IN QD
QN
QD
QN
CLK
OUT
6Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Static Timing Analysis ReductionStatic Timing Analysis ReductionStatic Timing Analysis Reduction
IBM’s Hitchcock (70’s) observed that you could exhaustively test all behaviors within a single clock cycle
7Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Advantages of STAAdvantages of STAAdvantages of STA
Exhaustive timing coverage Does not require input vectors More efficient than DTA in memory and CPU resources
Faster operationCapacity for millions of gates
8Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Disadvantages of STADisadvantages of STADisadvantages of STA
For synchronous logic onlyDifficult to learnTricky constraints beyond the boundaries of single clock flip-flop design chips:
Multiple clocksFalse pathsLatchesMulti-cycle paths
Lack of consistent conventions
9Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Review Main Steps of STAReview Main Steps of STAReview Main Steps of STA
Break the design into sets of timing pathsCalculate the delay of each path (create timing graph)Check all path delays to see if the given timing constraints are met
10Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Four Types of Timing PathsFour Types of Timing PathsFour Types of Timing Paths
Start Point: primary input port
End Point:data input pin of sequential devices
Start Point: clock pin of sequential device
End Point:data input pin of sequential devices
Start Point: clock pin of sequential device
End Point:primary output port
Start Point: primary input port
End Point:primary output port
11Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Timing Path ExampleTiming Path ExampleTiming Path Example
How many start points are in this design?How many end points are in this design?How many timing paths are in this design?
12Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Create Timing GraphCreate Timing GraphCreate Timing Graph
Netlist is represented as directed acyclic graph (DAG)Delay values associated with links (Cells & Nets) are calculatedCreate the timing graph of arrival time (AT)Create the timing graph of required time (RT)Create the slack graph
Timing is met when slack is greater than or equal to zero (RT should always be after AT)
13Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Timing Graph – Arrival TimeTiming Graph Timing Graph –– Arrival TimeArrival Time
0.2
0.1
0.15
0.1
0.2 0.1 0.20.1
0.2
0.20.1 0.2
0.1
0.1
0.15 0.1
Tarr = 0.1
Tarr = 0.1
0.3 0.4
0.6
0.7
0.3 0.40.55
0.65 0.85
0.9 1.0
1.2
1.3
1.3
1.451.55
Timing Arc
14Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Timing Graph – Required TimeTiming Graph Timing Graph –– Required TimeRequired Time
0.2
0.1
0.15
0.1
0.2 0.1 0.20.1
0.2
0.20.1 0.2
0.1
0.1
0.15 0.1 Treq = 1.5
Tarr = 1.50.25 0.35
0.55
0.65
0.3 0.40.55
0.65
1.4
0.85
0.95
1.15
1.25
1.4
0.05
0.1
setup time case
15Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Slack GraphSlack GraphSlack Graph
-0.05
-0.05 -0.55
-0.05
0 00
0-0.05
-0.05
-0.05
-0.05-0.05
-0.05
0
-0.05
0.2
Slack = Required Time – Arrival Time
setup time case
16Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Block-based vs. Path-based STA (1/2)BlockBlock--based vs. Pathbased vs. Path--based STA (1/2)based STA (1/2)
Block-based: timing information is associated with discrete design elements (ports, pins, gates)
Slack is calculated on every design elementPath-based: timing information is associated with topological paths (collections of design elements)
Used in Primetime
17Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Block-based vs. Path-based STA (2/2)BlockBlock--based vs. Pathbased vs. Path--based STA (2/2)based STA (2/2)
31
31
21
32
AT=2
AT=5
RAT=10
31
31
21
32
AT=2
AT=5
RAT=10
Path-based:2+2+3 = 7 (OK)2+3+1+3 = 9 (OK)2+3+3+2 = 10 (OK)5+1+1+3 = 10 (OK)5+1+3+2 = 11 (Fail)5+1+2 = 8 (OK)
AT=7RAT=7
AT=9RAT=8
AT=6RAT=5
AT=2RAT=5
AT=5RAT=4
Block-based:Critical path is determinedas collection of gates with the same, negative slack: In our case, we see onecritical path with slack = -1
AT=11RAT=10
18Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Timing ArcsTiming ArcsTiming Arcs
Describes the timing relationship between two nodesWhen traversing the design structure to updateAT and RT, STA is actually traversing throughtiming arcs from node to nodeDefined in cell library
19Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Combinational ArcsCombinational ArcsCombinational Arcs
Combinational arcs (Timing delay)Combinational arcs are the default arcsEach combinational arc has one of three timing sensesTiming senses are specified in the library or automatically derived from the logic function
20Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Setup Timing ArcsSetup Timing ArcsSetup Timing Arcs
Setup arcs (Timing check)Constrains the time before the active clock edge when the data needs to be stable
• setup_rising• setup_falling
CK
D
21Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Hold Timing ArcsHold Timing ArcsHold Timing Arcs
Hold arcs (Timing check)Constraints for the time after the active clock edge when the data still needs to be stable
• hold_rising• hold_falling
22Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Edge Arc TypesEdge Arc TypesEdge Arc Types
Edge arcs (Timing delay)After a launching clock edge, the clock node is converted to a data node
• falling_edge• rising_edge
23Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Preset and Clear TypesPreset and Clear TypesPreset and Clear Types
Preset and Clear arcs (Timing delay)After an active asynchronous signal occurs, the timethe data appears at the output of the register
• positive_preset / negative_preset• positive_clear / negative_clear
These arcs are often disabled
24Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Recovery TypesRecovery TypesRecovery Types
Recovery arcs (Timing check)The amount of time before an active clock edgean asynchronous signal needs to be inactive
• recovery_rising• recovery_falling
25Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Removal ArcsRemoval ArcsRemoval Arcs
Removal arcs (Timing check)The amount of time after an active clock edgean asynchronous signal needs to be inactive
• removal_rising• removal_falling
26Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Three State ArcsThree State ArcsThree State Arcs
Three state enable & disable arcs (Timing delay)Special timing relationship for three state activation
• three_state_enable• three_state_disable
27Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Minimum Pulse Width TypesMinimum Pulse Width TypesMinimum Pulse Width Types
Width arcs (Timing check)The amount of time a signal needs to remain stable
• nochange_high• nochange_low
28Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Timing Verification ItemsTiming Verification ItemsTiming Verification Items
Timing ChecksSetup timeHold timeRecovery timeRemoval timeMinimum pulse widthGlitch detection (clock gating) User-defined
Design Rule ChecksMax capacitanceMax transitionMax fan-out
29Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Clock Gating ChecksClock Gating ChecksClock Gating Checks
QD
QN
QD
QN
CLKU1
Enable
CLK
Enable
Setup Margin Hold Margin
Enable
Distorted Clock WaveformGated_Clock
EnableGlitch due to late arrival time of Enable
Gated_Clock
30Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Data Preparation for STAData Preparation for STAData Preparation for STA
Gate-level Netlist
Block Models
Cell Library
Operating Conditions
Design Data
Library Data
Back-annotated Parasitic
Estimated Wire Load Models
Interconnect Data
Descriptions of Clocks
Boundary Conditions
Timing Exceptions
STA
Timing Constraints
31Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Library DataLibrary DataLibrary Data
Cell Delay modelLinear modelNon-linear model
Operating conditions
32Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Linear Cell Delay ModelLinear Cell Delay ModelLinear Cell Delay Model
Cell Delay = T0 + Ac * CloadT0de
lay
time
(ns)
output capacitance load (pf)
T0 : cell pin to pin intrinsic delay(delay without any loading)
Ac : drive impedance
33Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Non-linear Cell Delay ModelNonNon--linear Cell Delay Modellinear Cell Delay Model
Delay values are stored in the delay tablesDelay tables
Cell delayTransition delay
Vin
Vout
50% 50%
80%20%
Req
Ceq
I1I2Dtransition(I1)
Dcell(I2)
Dc Dtransition(I2)
I3
34Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Delay TablesDelay TablesDelay Tables
Cell Delay Dcell(I2) = f(Dtransition(I1), Ceq)
Transition Delay Dtransistion(I2) = g(Dtransition(I1), Ceq)
OutputCapacitance
Input Transition0 0.5 1
0.1
0.2
0.123 0.234 0.456
0.222 0.432 0.801
index1: input transitionIndex2: output capacitance
Req
Ceq
I1I2Dtransition(I1)
Dcell(I2)
Dc Dtransition(I2)
I3
Vin Vout
35Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Select the Correct Delay TableSelect the Correct Delay TableSelect the Correct Delay Table
According to output transition directionrise tablefall table
Output transition direction depends on unatenessinvert (positive_unate)noninvert (negative_unate)nonunate
• The worst case delay is selected
Consider the clock edge for sequential cellsedge_risingedge_falling
R F
R or FR
36Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Operating ConditionsOperating ConditionsOperating Conditions
The process, voltage, and temperature (PVT) ranges a design encountersSpecified in the technology libraryCell and interconnect delays are scaled
etemperaturnomeTemperaturvoltagenomVoltageprocessnomocess
KKKDD
T
VP
TTVVPPscale
__/_Pr
)1)(1)(1(
−=∆−=∆−=∆
∆+∆+∆+=
delaydelay delay
Process
Best
Worst
Typical
Best
Worst
TypicalBest
Worst
Typical
Voltage Temperature
37Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Data Preparation for STAData Preparation for STAData Preparation for STA
Gate-level Netlist
Block Models
Cell Library
Operating Conditions
Design Data
Library Data
Back-annotated Parasitic
Estimated Wire Load Models
Interconnect Data
Descriptions of Clocks
Boundary Conditions
Timing Exceptions
STA
Timing Constraints
38Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Define Timing ConstraintsDefine Timing ConstraintsDefine Timing Constraints
Design rule constraintsSet fan-out constraintsSet capacitance constraintsSet transition time constraints
Design optimization constraintsDefine clock specificationSpecify boundary conditions (I/O timing requirements)Specify combinational path delay requirementsSpecify timing exceptions
39Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Define Clock SpecificationDefine Clock SpecificationDefine Clock Specification
We need to accurately specify the clock including the clock routing details in the early design stage in order to achieve timing convergenceWhat should be defined?
PeriodWaveformLatency
• Source latency• Network latency
Uncertainty• Jitter• Skew
All register-to-register path are constrained now
40Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Clock Period & WaveformClock Period & WaveformClock Period & Waveform
Period: Clock cycle timeWaveform: Clock rise and fall timeExample:
Period: 10nsRise time: 0nsFall time: 5ns
clock
0 5 10
41Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Clock LatencyClock LatencyClock Latency
A very important part of the clock is the routing effects:
Off Chip cause:• Source latency (delay): the timing a clock signal takes to
propagate from its ideal waveform original point to the clock definition point
On Chip cause:• Budgeted network latency (delay) : the time the clock signal
takes to propagate from the clock definition point to the clock pin of the sequential cells
• Actual insertion delay QD
QN
network latency
(min_rise : max_rise : min_fall : max_fall)source latency
42Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Clock Uncertainty DefinitionClock Uncertainty DefinitionClock Uncertainty Definition
The maximum difference between the arrival of clock signals at sequential cells in one clock domain or between domains
FF
FF
FFFF
P1
P2P3
P4
Arrival(P1) = 0.5nsArrival(P2) = 1nsArrival(P3) = 1.2nsArrival(P4) = 1.3ns
uncertainty = 1.3 – 0.5= 0.8ns
43Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Clock UncertaintyClock UncertaintyClock Uncertainty
A very important part of the clock is the routingOff Chip impact:
• Jitter: typically a small valueOn Chip impact:
• Budgeted skew • Actual skew
44Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Ideal and Computed ClocksIdeal and Computed ClocksIdeal and Computed Clocks
Off chip clock effects are fixed throughout flow: Source Latency Jitter
On chip routing is estimated till clock tree routingBudgeted network latency Budgeted skew
On chip routing is calculated after clock tree routing Actual insertion delay (network latency) Actual skew
45Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Define Timing ConstraintsDefine Timing ConstraintsDefine Timing Constraints
Design rule constraintsSet fan-out constraintsSet capacitance constraintsSet transition time constraints
Design optimization constraintsDefine clock specificationSpecify boundary conditions (I/O timing requirements)Specify combinational path delay requirementsSpecify timing exceptions
46Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
I/O ConstraintsI/O ConstraintsI/O Constraints
After constraining clock, we still need to constrain the I/O
Only comboin needs a "budgeted" arrival timeOnly combout needs a "budgeted" required time
47Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Boundary ConditionsBoundary ConditionsBoundary Conditions
Input driving cellInput transition timeOutput capacitance loadInput delayOutput delay
bQD
QN
INV01Driving Cell 5pf
Output Capacitance LoadInput Transition Time
48Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Input & Output DelayInput & Output DelayInput & Output Delay
An input delay is the specification of an arrival time at an input port relative to a clock edgeAn output delay represents an external timing path from am output or inout port to a register
Input delay = Delayclk-Q + a
Q a
My Design
Q
Output delay = c
Output Block
b c
Input Block
49Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Define Timing ConstraintsDefine Timing ConstraintsDefine Timing Constraints
Design rule constraintsSet fan-out constraintsSet capacitance constraintsSet transition time constraints
Design optimization constraintsDefine clock specificationSpecify boundary conditions (I/O timing requirements)Specify combinational path delay requirementsSpecify timing exceptions
50Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Constraint Combinational Path DelayConstraint Combinational Path DelayConstraint Combinational Path Delay
Set a target maximum delay for output portsOverride the default single-cycle timing for pathsSet a target minimum delay for output portsOverride the default hold relation in a sequential path
IN OutLogic
51Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Define Timing ConstraintsDefine Timing ConstraintsDefine Timing Constraints
Design rule constraintsSet fan-out constraintsSet capacitance constraintsSet transition time constraints
Design optimization constraintsDefine clock specificationSpecify boundary conditions (I/O timing requirements)Specify combinational path delay requirementsSpecify timing exceptions
• False Path• Multi-cycle path
52Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
False PathFalse PathFalse Path
Why are there false path constraints in a design?A path may exist in the circuit but never be used in its normal functional operationA functional path may exist but the timing is very slow or irrelevantA block may be reused and certain signal functions are no longer requiredA path may exist in the circuit but no combination of input vectors may ever exercise itA combinational loop exists in the design that needs to be broken
53Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Unexercised PathUnexercised PathUnexercised Path
A path may exist in the circuit but never be used in its normal functional operation
A test register PROBE is inserted in the circuit to enable chip debugging in the field. Data can be read through the probe register. Data can be written from the probe register. Probing would not occur at speed. (An alternative to scan)
54Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
False PathFalse PathFalse Path
Why are there false path constraints in a design?A path may exist in the circuit but never be used in its normal functional operationA functional path may exist but the timing is very slow or irrelevantA block may be reused and certain signal functions are no longer requiredA path may exist in the circuit but no combination of input vectors may ever exercise itA combinational loop exists in the design that needs to be broken
55Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Irrelevant PathIrrelevant PathIrrelevant Path
A functional path may exist but the timing is so slow or irrelevant
The chip uses a synchronized synchronous reset. The reset cycle has a huge number of cycles before it needs to settle.
56Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Asynchronous PathAsynchronous PathAsynchronous Path
A functional path may exist but the timing is so slow or irrelevant
I have metastabilization registers between those two asynchronous clock zones
57Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
False PathFalse PathFalse Path
Why are there false path constraints in a design?A path may exist in the circuit but never be used in its normal functional operationA functional path may exist but the timing is very slow or irrelevantA block may be reused and certain signal functions are no longer requiredA path may exist in the circuit but no combination of input vectors may ever exercise itA combinational loop exists in the design that needs to be broken
58Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
IP ReuseIP ReuseIP Reuse
A block may be reused and certain signal functions are no longer required
This piece of logic is a custom adder. With design re-use, often the blocks contain all of the potentially useful functions. When the design is implemented in a chip, often particular signals are not implemented
59Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
False PathFalse PathFalse Path
Why are there false path constraints in a design?A path may exist in the circuit but never be used in its normal functional operationA functional path may exist but the timing is very slow or irrelevantA block may be reused and certain signal functions are no longer requiredA path may exist in the circuit but no combination of input vectors may ever exercise itA combinational loop exists in the design that needs to be broken
60Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Logically Impossible PathLogically Impossible PathLogically Impossible Path
A path may exist in the circuit but no combination of input vectors may ever exercise it
A signal cannot travel from the Q output of a_reg through the two muxes to b_regPrimeTime attempts to automatically detect "logically impossible false paths“ (requires many CPU cycles)These situations are quite rare
61Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
False PathFalse PathFalse Path
Why are there false path constraints in a design?A path may exist in the circuit but never be used in its normal functional operationA functional path may exist but the timing is very slow or irrelevantA block may be reused and certain signal functions are no longer requiredA path may exist in the circuit but no combination of input vectors may ever exercise itA combinational loop exists in the design that needs to be broken
62Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Combinational LoopsCombinational LoopsCombinational Loops
A combinational loop exists in the design that needs to be broken
Most STA’s can’t leave combinational loops in the design, as a race condition will occurPrimeTime dynamicallybreaks combinationalloops.
63Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Break Combinational LoopsBreak Combinational LoopsBreak Combinational Loops
Break any reset arc (unusually specified)Break a three-state enable arcBreak at the first loop re-entry pointBreak arcs in the library
64Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Define Timing ConstraintsDefine Timing ConstraintsDefine Timing Constraints
Design rule constraintsSet fan-out constraintsSet capacitance constraintsSet transition time constraints
Design optimization constraintsDefine clock specificationSpecify boundary conditions (I/O timing requirements)Specify combinational path delay requirementsSpecify timing exceptions
• False Path• Multi-cycle path
65Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Multicycle PathsMulticycle PathsMulticycle Paths
Multicycle paths occur because the designer knows that the particular logic function will not be used till a later cycle
66Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Data Preparation for STAData Preparation for STAData Preparation for STA
Gate-level Netlist
Block Models
Cell Library
Operating Conditions
Design Data
Library Data
Back-annotated Parasitic
Estimated Wire Load Models
Interconnect Data
Descriptions of Clocks
Boundary Conditions
Timing Exceptions
STA
Timing Constraints
67Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Interconnect DataInterconnect DataInterconnect Data
Estimated delay information for nets based on a wire load model is used before P&RBack-annotated (Actual) delay information based on the P&R result is often described in the form of
SDF (timing information) – Standard Delay Format• SDF triplet: (min:typ:max)
RSPF – Reduced Standard Parasitic FormatDSPF – Detailed Standard Parasitic FormatSPEF – Standard Parasitic Exchange Format
• SPEF also has syntax that allows the modeling of capacitance between different nets, so it is used by the crosstalk analysis tool
68Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Wireload ModelWireload ModelWireload Model
Very inaccurate!
500um x 500um1000um x 1000um
wire_load (“500”) (resistance : 3.0 /* R per unit length*/capacitance: 1.3 /* C per unit length */area: 0.04 /* area per unit length */slop: 0.15 /* extrapolation slope*/fanout_length ( 1 , 2.1 ) /* fanout-length pairs */fanout_length ( 2 , 2.5)fanout_length ( 3 , 2.8)fanout_length ( 4 , 3.3)
Cwire = (fanout=3, length =2.8) x capacitance coefficient (1.3) = 3.64 load units
Rwire = (fanout=3, length =2.8) x resistance coefficient (3.0) = 8.4 resistance units
AreaNet = (fanout=3, length =2.8) x area coefficient (0.04) = 0.112 net area units
69Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Wireload ModesWireload ModesWireload Modes
70Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Parasitic Model During P&RParasitic Model During P&RParasitic Model During P&R
Compute wire lengthIdeal Manhattan ModelComputed Manhattan ModelGlobal Routing Model
Compute parasitic valueLinear parasitic modelTable lookup parasitic model
Calculate wire delayElmore ModelFinal Layout Model
71Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Ideal Manhattan ModelIdeal Manhattan ModelIdeal Manhattan Model
72Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Computed Manhattan ModelComputed Manhattan ModelComputed Manhattan Model
73Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Global Routing ModelGlobal Routing ModelGlobal Routing Model
74Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Table Lookup Parasitic ModelTable Lookup Parasitic ModelTable Lookup Parasitic Model
Table-Look-Up (TLU) Capacitance modelCapTable• cap_value = f(configuration, width, spacing)
CapModel• Assign CapTable to the reference layer according to the
configuration• Capacitances are categorized into bottom, top and lateral
group
topair
substrate
M2
M1
Poly
lateral
bottomconfiguration2configuration1 configuration3
75Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Elmore ModelElmore ModelElmore Model
76Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Final Layout Model Final Layout Model Final Layout Model
AWE (Extraction Based) Modelp1 , p2 – Polesr1 , r2 - Residues
77Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Perform Static Timing AnalysisPerform Static Timing AnalysisPerform Static Timing Analysis
Specifydesign data& libraries
Gate-level Netlist
Block Models
Cell Library
Operating ConditionsSpecify
interconnect
Back-annotated Parasitic
Estimated Wire Load Models
Specifytiming constraints
Descriptions of Clocks
Boundary Conditions
Timing ExceptionsCheckTiming
ConstraintViolationReports
PathTimingReports
78Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (Assumptions)STA Example 1 (Assumptions)STA Example 1 (Assumptions)
Check setup time violationsAssume all gates have 3ns max rise delay and 2ns min rise delayAssume all gates have 2ns max fall delay and 1ns min fall delayAssume all nets have 2ns max delay and 1ns min delay3ns CLK-Q delay1ns setup time (Ts)1ns hold time (Th)
79Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (Timing Constraints)STA Example 1 (Timing Constraints)STA Example 1 (Timing Constraints)
Clock definitionClock period: 14ns (Dclkp)Clock source latency: 2ns (Dclks)Clock network latency: 3ns (Dclkn)Clock uncertainty: 1ns (Dclku)
IO constraintsInput delay of A, B, C: 1ns (Da , Db , Dc)Output delay of Y: 3ns (DY)
80Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (Timing Paths)STA Example 1 (Timing Paths)STA Example 1 (Timing Paths)
Timing Path 1Timing Path 2Timing Path 3
81Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (AT of Path1 - Rise)STA Example 1 (AT of Path1 STA Example 1 (AT of Path1 -- Rise)Rise)
Timing path 1: PI to clock data inputArrival time at end point: Da+2+3+2+3+2 = 13ns
R
R
R
2
32
3
2
AT = 13
0 1413launch edge
capture edge
source clock (ideal)
target clock (ideal)
AT
Why are the delay values
chosen?
82Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (AT of Path1 - Fall)STA Example 1 (AT of Path1 STA Example 1 (AT of Path1 -- Fall)Fall)
Timing path 1: PI to clock data inputArrival time at end point: Da+2+2+2+3+2 = 12ns
0 1412launch edge
capture edge
source clock (ideal)
target clock (ideal)
AT
Why are the delay values
chosen?
F
F
R
2
22
3
2
AT = 12
83Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (RT of Path1 - R/F)STA Example 1 (RT of Path1 STA Example 1 (RT of Path1 -- R/F)R/F)
Timing path 1: PI to clock data inputRequired time at end point: Dclkp + Dclks + Dclkn - Dclku - Ts = 14+2+3-1-1 = 17ns
0 14launch edge
capture edge
source clock (ideal)
target clock (ideal)
target clock (source)
target clock (source+network)
target clock (source+network+uncertainty)
16
19
18
17
RT
setup time
84Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (Slack of Path1 - Rise)STA Example 1 (Slack of Path1 STA Example 1 (Slack of Path1 -- Rise)Rise)
Timing path 1: PI to clock data inputSlack at end point: RT - AT = 17-13 = 4nsTiming is met since slack is greater than 0
R
R
R
2
32
3
2
AT = 13RT = 17
85Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (Slack of Path1 - Fall)STA Example 1 (Slack of Path1 STA Example 1 (Slack of Path1 -- Fall)Fall)
Timing path 1: PI to clock data inputSlack at end point: RT - AT = 17-12 = 5nsTiming is met since slack is greater than 0
F
R
2
22
3
2
AT = 12RT = 17
F
86Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (AT of Path2 - Rise)STA Example 1 (AT of Path2 STA Example 1 (AT of Path2 -- Rise)Rise)
Timing path 2: clock to clock data inputArrival time at end point: Dclks + Dclkn +3+2+3+2+3+2 = 20ns
R
AT = 20
0 14launch edge
AT
source clock (ideal)
source clock (source+network)
Why are the delay values
chosen?3 R
R2 3
23 2
5 19 20
87Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (AT of Path2 - Fall)STA Example 1 (AT of Path2 STA Example 1 (AT of Path2 -- Fall)Fall)
Timing path 2: clock to clock data inputArrival time at end point: Dclks + Dclkn +3+2+2+2+3+2 = 19ns
0 14launch edge
AT
5 19source clock (ideal)
source clock (source+network)
F
AT = 19 Why are the delay values
chosen?3 F
R2 2
23 2
88Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (RT of Path2 - R/F)STA Example 1 (RT of Path2 STA Example 1 (RT of Path2 -- R/F)R/F)
Timing path 2: clock to clock data inputRequired time at end point: Dclkp + Dclks + Dclkn - Dclku - Ts = 14+2+3-1-1 = 17ns
0 14
capture edge
source clock (source+network)
target clock (ideal)
target clock (source)
target clock (source+network)
target clock (source+network+uncertainty)
16
19
18
17
RT
setup time
launch edge5
89Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (Slack of Path2 - Rise)STA Example 1 (Slack of Path2 STA Example 1 (Slack of Path2 -- Rise)Rise)
Timing path 2: clock to clock data inputSlack at end point: RT - AT = 17-20 = -3nsTiming is not met since slack value is negative
R
AT = 20
3 R
R2 3
23 2
RT = 17
90Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (Slack of Path2 - Fall)STA Example 1 (Slack of Path2 STA Example 1 (Slack of Path2 -- Fall)Fall)
Timing path 2: clock to clock data inputSlack at end point: RT - AT = 17-19 = -2nsTiming is not met since slack value is negative
F
AT = 19
3 F
R2 2
23 2
RT = 17
91Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (AT of Path3 - Rise)STA Example 1 (AT of Path3 STA Example 1 (AT of Path3 -- Rise)Rise)
Timing path 3: clock to POArrival time at end point: Dclks + Dclkn +3+2+3+2= 15ns
AT = 15
0 14launch edge
R
source clock (ideal)
source clock (source+network)
AT
5
2
3R
2
15
3
92Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (AT of Path3 - Fall)STA Example 1 (AT of Path3 STA Example 1 (AT of Path3 -- Fall)Fall)
Timing path 3: clock to POArrival time at end point: Dclks + Dclkn +3+2+2+2= 14ns
AT = 14
0 14launch edge
AT
F
source clock (ideal)
source clock (source+network)
5
2
2F
2
3
93Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (RT of Path3 - R/F)STA Example 1 (RT of Path3 STA Example 1 (RT of Path3 -- R/F)R/F)
Timing path 3: clock to PORequired time at end point: Dclkp - DY = 14-3 = 11ns
0 14source clock (source+network)11
RT
launch edge5
target clock (ideal)
output delay
RT = 11F
2
2F
2
3QD
QN
3
94Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (Slack of Path3 - Rise)STA Example 1 (Slack of Path3 STA Example 1 (Slack of Path3 -- Rise)Rise)
Timing path 3: clock to POSlack at end point: RT - AT = 11-15 = -4nsTiming is not met since slack value is negativeThis is the critical path
AT = 15R
2
3R
2
3QD
QN
RT = 113
95Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 1 (Slack of Path3 - Fall)STA Example 1 (Slack of Path3 STA Example 1 (Slack of Path3 -- Fall)Fall)
Timing path 3: clock to POSlack at end point: RT - AT = 11-14 = -3nsTiming is not met since slack value is negative
AT = 14F
2
2F
2
3QD
QN
RT = 113
96Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (Assumptions)STA Example 2 (Assumptions)STA Example 2 (Assumptions)
Check hold time violationsAssume all gates have 3ns max rise delay and 2ns min rise delayAssume all gates have 2ns max fall delay and 1ns min fall delayAssume all nets have 2ns max delay and 1ns min delay3ns CLK-Q delay1ns setup time (Ts)1ns hold time (Th)
97Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (Timing Constraints)STA Example 2 (Timing Constraints)STA Example 2 (Timing Constraints)
Clock definitionClock period: 14ns (Dclkp)Clock source latency: 2ns (Dclks)Clock network latency: 3ns (Dclkn)Clock uncertainty: 1ns (Dclku)
IO constraintsInput delay of A, B, C: 1ns (Da , Db , Dc)Output delay of Y: 3ns (DY)
98Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (Timing Paths)STA Example 2 (Timing Paths)STA Example 2 (Timing Paths)
Timing Path 1Timing Path 2Timing Path 3
99Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (AT of Path1 – R/F)STA Example 2 (AT of Path1 STA Example 2 (AT of Path1 –– R/F)R/F)
Timing path 1: PI to clock data inputArrival time at end point: Da+1 = 2ns
R/F1
AT = 2
Next Data
0 14launch edge
capture edge
source clock (ideal)
target clock (ideal)
AT
QD
QN
1
2
Why are the delay values
chosen?
100Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (RT of Path1 - R/F)STA Example 2 (RT of Path1 STA Example 2 (RT of Path1 -- R/F)R/F)
Timing path 1: PI to clock data inputRequired time at end point: Dclks + Dclkn + Dclku + Th = 2+3+1+1 = 7ns
0
launch edge
capture edge
source clock (ideal)
target clock (ideal)
RThold time
7
target clock (source)
target clock (source+network)
target clock (source+network+uncertainty)
101Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (Slack of Path1 – R/F)STA Example 2 (Slack of Path1 STA Example 2 (Slack of Path1 –– R/F)R/F)
Timing path 1: PI to clock data inputSlack at end point: AT - RT = 2-7 = -5nsTiming is not met since slack value is negativeThis is the critical path
R/F1
AT = 2QD
QN
1
RT = 7
102Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (AT of Path2 - Rise)STA Example 2 (AT of Path2 STA Example 2 (AT of Path2 -- Rise)Rise)
Timing path 2: clock to clock data inputArrival time at end point: Dclks + Dclkn +3+1+2+1+2+1 = 15ns
Next Data
0 14launch edge
AT
5 19 20source clock (ideal)
source clock (source+network)
R
AT = 15 Why are the delay values
chosen?3 R
R1 2
12 1
103Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (AT of Path2 - Fall)STA Example 2 (AT of Path2 STA Example 2 (AT of Path2 -- Fall)Fall)
Timing path 2: clock to clock data inputArrival time at end point: Dclks + Dclkn +3+1+1+1+2+1 = 14ns
Next Data
0 14launch edge
AT
5
source clock (ideal)
source clock (source+network)
F
AT = 14 Why are the delay values
chosen?3 F
R1 1
12 1
104Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (RT of Path2 - R/F)STA Example 2 (RT of Path2 STA Example 2 (RT of Path2 -- R/F)R/F)
Timing path 2: clock to clock data inputRequired time at end point: Dclks + Dclkn + Dclku + Th = 2+3+1+1 = 7ns
0
launch edge
capture edge
source clock (ideal)
target clock (ideal)
RThold time
7
target clock (source)
target clock (source+network)
target clock (source+network+uncertainty)
105Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (Slack of Path2 - Rise)STA Example 2 (Slack of Path2 STA Example 2 (Slack of Path2 -- Rise)Rise)
Timing path 2: clock to clock data inputSlack at end point: AT - RT = 15-7 = 8nsTiming is met since slack is greater than 0
RT = 7
R
AT = 15
3 R
R1 2
12 1
106Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (Slack of Path2 - Fall)STA Example 2 (Slack of Path2 STA Example 2 (Slack of Path2 -- Fall)Fall)
Timing path 2: clock to clock data inputSlack at end point: AT - RT = 14-7 = 7nsTiming is met since slack is greater than 0
F
AT = 14
3 F
R1 1
12 1
RT = 7
107Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (AT of Path3 - Rise)STA Example 2 (AT of Path3 STA Example 2 (AT of Path3 -- Rise)Rise)
Timing path 3: clock to POArrival time at end point: Dclks + Dclkn +3+1+2+1= 12ns
AT = 12
Next Data
0launch edge
R
source clock (ideal)
source clock (source+network)
AT
5
1
2R
1
12
3
108Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (AT of Path3 - Fall)STA Example 2 (AT of Path3 STA Example 2 (AT of Path3 -- Fall)Fall)
Timing path 3: clock to POArrival time at end point: Dclks + Dclkn +1+1+1= 11ns
AT = 11
Next Data
0launch edge
F
source clock (ideal)
source clock (source+network)AT
5
1
1F
1
11
3
109Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (RT of Path3 - R/F)STA Example 2 (RT of Path3 STA Example 2 (RT of Path3 -- R/F)R/F)
Timing path 3: clock to PORequired time at end point: - DY = -3ns
0source clock (source+network)
RT
launch edge
target clock (ideal)
output delay
RT = -3F
1
1F
1
3QD
QN
-3
110Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (Slack of Path3 - Rise)STA Example 2 (Slack of Path3 STA Example 2 (Slack of Path3 -- Rise)Rise)
Timing path 3: clock to POSlack at end point: AT - RT = 12-(-3) = 15nsTiming is met since slack is greater than 0
AT = 12R
1
2R
1
3QD
QN1
RT = -3
111Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA Example 2 (Slack of Path3 - Fall)STA Example 2 (Slack of Path3 STA Example 2 (Slack of Path3 -- Fall)Fall)
Timing path 3: clock to POSlack at end point: AT - RT = 11-(-3) = 14nsTiming is met since slack is greater than 0
AT = 11F
1
1F
1
3QD
QN1
RT = -3
112Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Handling Multiple ClocksHandling Multiple ClocksHandling Multiple Clocks
Determine the least common multiple (LCM) of the 2 clock periods first and then find the setup and hold relationship
113Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Setup RelationshipsSetup RelationshipsSetup Relationships
Find the Setup Relationship between A rising to B risingThe setup relationship is the closest distance between the launching clock edge (A) to the receiving clock edge (B)
114Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Hold RelationshipsHold RelationshipsHold Relationships
Find the Hold Relationship between A rising to B risingThe hold relationship is the closest distance between the launching edge (A) to the previous receiving edge (B)
115Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA with LatchesSTA with LatchesSTA with Latches
Latches and Flip-Flops are both registers or "storage devices“Latches are level sensitive instead of edge triggered
116Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Time Borrowing Example 1Time Borrowing Example 1Time Borrowing Example 1
If these were flip flops, timing would not be met at b_regWith time borrowing, the middle latch can borrow time from the next stage and meet timing!
117Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Time Borrowing Example 2Time Borrowing Example 2Time Borrowing Example 2
Can time borrowing eliminate negative slack?No, the final data missed the active edge of c_reg.
118Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Time Borrowing Example 3Time Borrowing Example 3Time Borrowing Example 3
Can time borrowing eliminate negative slack?No, c_reg is a flip-flop and the data misses c_reg’s edge
119Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Time Borrowing Example 4Time Borrowing Example 4Time Borrowing Example 4
Can time borrowing eliminate negative slack?Yes! In fact there is extra time before the activating edge of c_reg
120Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Time Borrowing Example 5Time Borrowing Example 5Time Borrowing Example 5
Can time borrowing eliminate negative slack?No. The earliest b_reg can launch the data is at time 5. c_regwill receive the data too late
121Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Four Types of AnalysisFour Types of AnalysisFour Types of Analysis
Single operating condition analysisWorst operating conditionTypical operating conditionBest operating condition
Simultaneous best-case/worst-case analysisOn-Chip variationCase analysis
122Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Single OC AnalysisSingle OC AnalysisSingle OC Analysis
Typically, you need to perform timing analysis for at least two operating conditions to ensure that the design has no timing violations
Best case (minimum path report) (Hold Time Check)Worst case (maximum path report) (Setup Time Check)
CIC 0.18um library examplefast.libtypical.libslow.lib
123Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Best/Worst Case AnalysisBest/Worst Case AnalysisBest/Worst Case Analysis
For most of STA tools, you can simultaneously perform timing analysis for the best-case and worst-case operating conditions.
Max paths analyzed with worst case OC (Setup Time Check)Min paths analyzed with best case OC (Hold Time Check)
Min-max values can be also specified forSDF back-annotated delaysInput and output delaysWire load modelsNet resistance-capacitanceClock latency/transitionDriving cell
124Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
On-Chip Variation AnalysisOnOn--Chip Variation AnalysisChip Variation Analysis
Delays have uncertainty due to the variation of PVT across large diesOn-chip variation allows you to account for the delay variations due to PVT changes across the die, providing more accurate delay estimates.
125Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
Case AnalysisCase AnalysisCase Analysis
Timing analysis with specified logic value conditions on pins or portsLogic constants are propagated to avoid unnecessary timing path analysis (3 paths in this example)
conditional combinational timing arc
10
F3 F
F2 2
22 2
0
126Chip Implementation Center / Design Service Division / Physical Design Section / C.S.ChenStatic Timing Analysis
STA in Cell-based Design FlowSTA in CellSTA in Cell--based Design Flowbased Design Flow
After each run of synthesisSynopsys Design Compiler / Cadence AmbitMagma Blast RTL / Blast Fusion
After each run of physical optimizationSynopsys Physical Compiler / Synopsys SaturnSynopsys Astro / Cadence SE / Cadence SOC Encounter
After each run of P&RSynopsys Apollo / AstroCadence SE / Cadence SOC EncounterMagma Blast Fusion
STA sign-offPrimetime
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