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2006-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are theproperty of their respective owners.
Introduction
The Xilinx LogiCORE IP Block Memory Generatorcore is an advanced memory constructor that generates
area and performance-optimized memories using
embedded block RAM resources in Xilinx FPGAs.
Available through the CORE Generator software,
users can quickly create optimized memories to lever-
age the performance and features of block RAMs in Xil-
inx FPGAs.
Features
Generates single-port RAM, simple dual-port RAM,
true dual-port RAM, single-port ROM, or dual-portROM
Performance up to 450 MHz
Supports data widths from 1 to 1152 bits
Supports memory depths from 2 to 9M words
(limited only by memory resources on selected part)
Supports configurable port aspect ratios for
dual-port configurations
Supports read-to-write aspect ratios in Virtex-4
and Virtex-5 FPGAs
Optimized algorithm for minimum block RAMresource utilization
Configurable memory initialization
Supports individual write enable per byte in
Virtex-5, Virtex-4, and Spartan-3A/3A DSP devices
with or without parity
Optimized VHDL and Verilog behavioral models
for fast simulation times; structural simulation
models for precise simulation of memory behaviors
Selectable operating mode per port: WRITE_FIRST,
READ_FIRST, or NO_CHANGE
Supports built-in Hamming Error CorrectionCapability (ECC)
Supports pipelining of DOUT bus for improved
performance in specific configurations
0
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DS512 October 10, 2007 0 0 Product Specification
LogiCORE IP Facts
Core Specifics
Supported Device
Family
Virtex-5, Virtex-4,
Virtex-II Pro, Virtex-II,
Spartan-3E,
Spartan-3A/3AN/3A DSP,
Spartan-3
Package All
Speed Grade All
Performance Varied, based on core parameters
Core Resources
Block RAM Varied, based on core parameters
DCM None
BUFG None
IOBs/RocketIO None
PPC None
IOB-FF/TBUFs None
Provided with Core
Documentation Product Specification
Design File Formats NGC netlist
Design Tool Requirements
Xilinx Implementation
ToolsISETM9.2i
Simulation Models
(SWIFT-compliant
tool required)
VHDL Structural
Verilog Structural
VHDL Behavioral1
Verilog Behavioral1
Synthesis XST 9.2i
Support
Provided by Xilinx, Inc. @ www.xilinx.com
1. Behavioral models do not precisely model collision behavior. See"Simulation Models" on page 21for details.
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Overview
The Block Memory Generator core uses embedded Block Memory primitives in Xilinx FPGAs to extend
the functionality and capability of a single primitive to memories of arbitrary widths and depths.
Sophisticated algorithms within the Block Memory Generator core produce optimized solutions to pro-
vide convenient access to memories for a wide range of configurations.
The Block Memory Generator has two fully independent ports that access a shared memory space. Both
A and B ports have a write and a read interface. In Virtex-5 and Virtex-4 FPGA architectures, all four
interfaces can be uniquely configured, each with a different data width. When not using all four inter-
faces, the user can select a simplified memory configuration (for example, a Single-Port Memory or
Simple Dual-Port Memory), allowing the core to more efficiently use available resources.
The Block Memory Generator is not completely backward-compatible with the Single-Port Block Mem-
ory and Dual-Port Block Memory cores; for information about the differences, see "Compatibility with
Older Memory Cores" on page 36.
Applications
The Block Memory Generator core is used to create customized memories to suit any application. Typ-ical applications include:
Single-Port Memory: Processor scratch RAM, very large look-up tables
Dual-Port Memory: Content addressable memories, FIFOs, multi-processor storage
Read-Only Memory: Program code storage, initialization ROM
Feature Summary
Memory Types
The Block Memory Generator core uses embedded block RAM to generate five types of memories:
Single-port RAM
Simple dual-port RAM
True dual-port RAM
Single-port ROM
Dual-port ROM
For dual-port memories, each port operates independently. Operating mode, clock frequency, optional
output registers, and optional pins are selectable per port.
Selectable Memory Algorithm
The core concatenates block RAM primitives according to one of the following algorithms:
Minimum Area Algorithm:The memory is generated using the minimum number of block RAMprimitives. Both data and parity bits are utilized.
Fixed Primitive Algorithm:The memory is generated using only one type of block RAM primitive.
For a complete list of primitives available for each device family, see the data sheet for that family.
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Configurable Width and Depth
The Block Memory Generator can generate memory structures from 1 to 1152 bits wide, and at least two
locations deep. The maximum depth of the memory is limited only by the number of block RAM prim-
itives in the target device.
Selectable Operating Mode per Port
The Block Memory Generator supports the following block RAM primitive operating modes: WRITE
FIRST, READ FIRST, and NO CHANGE. Each port may be assigned an operating mode.
Selectable Port Aspect Ratios
The core supports the same port aspect ratios as the block RAM primitives:
In all supported device families, the A port width may differ from the B port width by a factor of 1,
2, 4, 8, 16, or 32.
In Virtex-5 and Virtex-4 FPGA-based memories, the read width may differ from the write width by
a factor of 1, 2, 4, 8, 16, or 32 for each port. The maximum ratio between any two of the data widths
(DINA,DOUTA,DINB,and DOUTB) is 32:1.
Optional Byte-Write Enable
In Virtex-5, Virtex-4, and Spartan-3A/3A DSP FPGA-based memories, the Block Memory Generator
core provides byte-write support for memory widths of 8-bit (no parity) or 9-bit multiples (with parity).
Optional Output Registers
The Block Memory Generator provides two optional stages of output registering to increase memory
performance. The output registers can be chosen for port A and port B separately. The core supports the
Virtex-5, Virtex-4, and Spartan-3A DSP embedded block RAM registers as well as registers imple-
mented in the FPGA fabric. See "Output Register Configurations" on page 42 for more information
about using these registers.
Optional Pipeline Stages
The core provides optional pipeline stages within the MUX, available only when the registers at the
output of the memory core are enabled and only for specific configurations. For the available configu-
rations, the number of pipeline stages can be 1, 2, or 3. For detailed information, see "Optional Pipeline
Stages" on page 17.
Optional Enable Pin
The core provides optional port enable pins (ENAand ENB) to control the operation of the memory.
When deasserted, no read, write, or reset operations are performed on the respective port. If the enable
pins are not used, it is assumed that the port is always enabled.
Optional Synchronous Set/Reset Pin
The core provides optional set/reset pins (SSRAandSSRB) pin per port that synchronously initializethe read output to a programmable value.
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Memory Initialization
The memory contents can be optionally initialized using a memory coefficient (COE) file or by using the
default data option. A COEfile can define the initial contents of each individual memory location, while
the default data option defines the initial content of all locations.
Built-in Hamming Error Correction Capability
Single-Port RAM and Simple Dual-Port RAM memory types support the Virtex-5 Hamming Error Cor-
rection Capability (ECC) of the Virtex-5 block RAM primitives. The ECC memory automatically detects
single- and double-bit errors, and is able to auto-correct the single-bit errors.
Simulation Models
The Block Memory Generator core provides behavioral and structural simulation models in VHDL and
Verilog for both simple and precise modeling of memory behaviors, for example, debugging, probing
the contents of the memory, and collision detection.
Functional Description
The Block Memory Generator is used to build custom memory modules from block RAM primitives inXilinx FPGAs. The core implements an optimal memory by arranging block RAM primitives based on
user selections, automating the process of primitive instantiation and concatenation. Using the CORE
Generator Graphical User Interface (GUI), users can configure the core and rapidly generate a highly
optimized custom memory solution.
Memory Type
The Block Memory Generator creates five memory types: Single-port RAM, Simple dual-port RAM,
True dual-port RAM, Single-port ROM, and Dual-port ROM. Figures 1through 5illustrate the signals
available for each type. Optional pins are displayed in italics.
For each configuration, optimizations are made within the core to minimize the total resources used.
For example, a simple dual-port RAM with symmetric ports can utilize the special simple dual-port
RAM primitive in Virtex-5, which can save as much as fifty percent of the block RAM resources for
memories 512 words deep or fewer. The single-port ROM allows read access to the memory space
through a single port, as shown in Figure 1.
FigureTop x-ref1
Figure 1: Single-port ROM
Single-Port ROM
ADDRA
ENA
SSRA
CLKA
DOUTA
REGCEA
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The dual-port ROM allows read access to the memory space through two ports, as shown in Figure 2.
The single-port RAM allows read and write access to the memory through a single port, as shown in
Figure 3.
FigureTop x-ref2
Figure 2: Dual-port ROM
FigureTop x-ref3
Figure 3: Single-port RAM
Dual-Port ROM
ADDRA
ENA
SSRA
CLKA
DOUTA
DOUTB
REGCEA
ADDRB
ENB
SSRB
CLKB
REGCEB
Single-Port RAM
ADDRA
DINA
ENA
WEA
SSRA
CLKA
DOUTA
REGCEA
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The simple dual-port RAM provides two ports, A and B, as illustrated in Figure 4. Write access to the
memory is allowed via port A, and read access is allowed via port B.
The true dual-port RAM provides two ports, A and B, as illustrated in Figure 5. Read and write
accesses to the memory are allowed on either port.
FigureTop x-ref4
Figure 4: Simple Dual-port RAM
FigureTop x-ref5
Figure 5: True Dual-port RAM
Simple Dual-Port RAM
CLKA
DOUTBADDRB
ENB
SSRB
CLKB
REGCEB
ADDRA
DINA
ENA
WEA
True Dual-Port RAM
ADDRA
DINA
ENA
WEA
SSRA
CLKA
DOUTA
DOUTB
REGCEA
ADDRB
DINB
ENB
WEB
SSRB
CLKB
REGCEB
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Selectable Memory Algorithm
The Block Memory Generator core arranges block RAM primitives according to one of two algorithms:
the minimum area algorithm and the fixed primitive algorithm.
Minimum Area Algorithm
The minimum area algorithm provides a highly optimized solution, resulting in a minimum number ofblock RAM primitives used, while reducing output multiplexing. Figure 6 shows two examples of
memories built using the minimum area algorithm.
In the first example, a 3kx16 memory is implemented using three block RAMs. While it may have been
possible to concatenate three 1kx18 block RAMs in depth, this would require more output multiplex-
ing. The minimum area algorithm maximizes performance in this way while maintaining minimum
block RAM usage.
The second example, a 5kx17 memory, further demonstrates how the algorithm can pack block RAMs
efficiently to use the fewest resources while maximizing performance by reducing output multiplexing.
Fixed Primitive Algorithm
The fixed primitive algorithm allows the user to select a single block RAM primitive type. The core will
build the memory by concatenating this single primitive type in width and depth. It is useful in sys-
tems that require a fixed primitive type. Figure 7depicts two 3kx16 memories, one built using the 2kx9
primitive type, the other built using the 4kx4 primitive type.
FigureTop x-ref6
Figure 6: Examples of the Minimum Area Algorithm
3kx16 memory
2kx9
1kx18
2kx9
5kx17 memory
4kx4 4kx4
2kx9
2kx9
1kx18
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Note that both implementations use four block RAMs, and that some of the resources utilized extend
beyond the usable memory space. It is up to the user to decide which primitive type is best for their
application.
The fixed primitive algorithm provides a choice of 16kx1, 8kx2, 4kx4, 2kx9, 1kx18, and 512x36 primi-
tives. The primitive type selected is used to guide the construction of the total user memory space.
Whenever possible, optimizations are made automatically that use deeper embedded memory struc-
tures to enhance performance. The following table shows the primitives used to construct a memory
given the specified architecture and primitive selection.
FigureTop x-ref7
Figure 7: Examples of the Fixed Primitive Algorithm
Table 1: Memory Primitives Used Based on Architecture
ArchitecturePrimitiveSelection
PrimitivesUsed
Virtex-II1, Spartan-32 16kx1 16kx1
Virtex-II1, Spartan-32 8kx2 8kx2
Virtex-II1, Spartan-32 4kx4 4kx4
Virtex-II1, Spartan-32 2kx9 2kx9
Virtex-II1, Spartan-32 1kx18 1kx18
Virtex-II1, Spartan-32 512x36 512x36
Virtex-4 16kx1 32kx1, 16kx1
Virtex-4 8kx2 8kx2
Virtex-4 4kx4 4kx4
Virtex-4 2kx9 2kx9
Virtex-4 1kx18 1kx18
Virtex-4 512x36 512x36
Virtex-5 16kx1 64kx1, 32kx1, 16kx1
Virtex-5 8kx2 16kx2, 8kx2
Virtex-5 4kx4 8kx4, 4kx4
Virtex-5 2kx9 4kx9, 2kx9
3kx16 memory
2kx9
2kx9
2kx9
2kx9
3kx16 memory
4kx4 4kx4 4kx4 4kx4
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When using data-width aspect ratios, the primitive type dimensions are chosen with respect to the A
port write width. Note that primitive selection may limit port aspect ratios as described in "Aspect
Ratio Limitations" on page 12. When using the byte write feature in Virtex-5, Virtex-4, and Spar-
tan-3A/3A DSP devices, only the 2kx9, 1kx18, and 512kx36 primitive choices are available.
Selectable Width and Depth
The Block Memory Generator generates memories with widths from 1 to 1152 bits, and with depths of
eight or more words. The memory is built by concatenating block RAM primitives, and total memory
size is limited only by the number of block RAMs on the target device.
Write operations to out-of-range addresses are guaranteed not to corrupt data in the memory, while
read operations to out-of-range addresses will return invalid data. Note that the set/reset function
should not be asserted while accessing an out-of-range address as this also results in invalid data on the
output.
Operating Mode
The operating mode determines which data word is presented on the output during a write operation.
Each port is assigned an operating mode. The Block Memory Generator supports the three operating
modes supported by the block RAM primitives. These operating modes are described in detail below.
For more information, refer to the block RAM section of the user guide for the specific device family. Write First Mode: In WRITE_FIRST mode, the input data is simultaneously written into memory
and driven on the data output, as shown in Figure 8. This transparent mode offers the flexibility of
using the data output bus during a write operation on the same port.
Virtex-5 1kx18 2kx18, 1kx18
Virtex-5 512x36 1kx36
Virtex-5 256x72 512x72
1. Virtex-II and its derivative, Virtex-II Pro.2. Spartan-3 and its derivatives, including Spartan-3E and Spartan-3A/3A DSP.
FigureTop x-ref8
Figure 8: Write First Mode Example
Table 1: Memory Primitives Used Based on Architecture (Continued)
ArchitecturePrimitive
Selection
Primitives
Used
aa
WEA
DINA[15:0]
DOUTA[15:0]
CLKA
ADDRA bb
1111
ENA
cc dd
2222
MEM(aa) 1111 2222 MEM(dd)0000
DISABLED READWRITE
MEM(bb)=1111
WRITEMEM(cc)=
2222READ
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Note: The WRITE_FIRST operation is affected by the optional byte-write feature in Virtex-5,Virtex-4, and Spartan-3A/3A DSP devices. It is also affected by the optional read-to-write aspectratio feature in Virtex-5 and Virtex-4. For detailed information, see "Write First ModeConsiderations" on page 13.
Read First Mode: In READ_FIRST mode, data previously stored at the write address appears on
the data output, while the input data is being stored in memory. This read-before-write behavior is
illustrated in Figure 9.
No Change Mode: In NO_CHANGE mode, the output latches remain unchanged during a write
operation. As shown in Figure 10, the data output is still the previous read data and is unaffected
by a write operation on the same port.
Data Width Aspect Ratios
The Block Memory Generator supports data width aspect ratios. This allows the port A data width tobe different than the port B data width, as described in Port Aspect Ratios. In Virtex-5 and Virtex-4
FPGA-based memories, all four data busses (DINA, DOUTA, DINB, and DOUTB) can have different
widths, as described in "Virtex-5 and Virtex-4 Read-to-Write Aspect Ratios" on page 11.
The limitations of the data width aspect ratio feature (some of which are imposed by other optional fea-
tures) are described in "Aspect Ratio Limitations" on page 12. The CORE Generator GUI ensures only
valid aspect ratios as selected.
FigureTop x-ref9
Figure 9: Read First Mode Example
FigureTop x-ref10
Figure 10: No Change Mode Example
aa
WEA
DINA[15:0]
DOUTA[15:0]
CLKA
ADDRA bb
1111
ENA
cc dd
2222
MEM(aa) o ld MEM(bb) old MEM(cc) MEM(dd)0000
DISABLED READWRITE
MEM(bb)=1111
WRITEMEM(cc)=
2222READ
aa
WEA
DINA[15:0]
DOUTA[15:0]
CLKA
ADDRA bb
1111
ENA
cc dd
2222
MEM(aa) MEM(dd)0000
DISABLED READWRITE
MEM(bb)=1111
WRITEMEM(cc)=
2222READ
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Port Aspect Ratios
The Block Memory Generator supports port aspect ratios of 1:32, 1:16, 1:8, 1:4, 1:2, 1:1, 2:1, 4:1, 8:1, 16:1,
and 32:1. The port A data width can be up to 32 times larger than the port B data width, or vice versa.
The smaller data words are arranged in little-endian format, as illustrated in Figure 11.
Port Aspect Ratio Example
Consider a true dual-port RAM of 32x2048, which is the A port width and depth. From the perspective
of an 8-bit B port, the depth would be 8192. The ADDRAbus is 11 bits, while the ADDRBbus is 13 bits.The data is stored little-endian, as shown in Figure 11. Note that Anis the data word at address n, with
respect to the A port. Bnis the data word at address n with respect to the B port. A 0is comprised of B3,
B2, B1, and B0.
Virtex-5 and Virtex-4 Read-to-Write Aspect Ratios
When implementing RAMs targeting Virtex-5 and Virtex-4 FPGAs, the Block Memory Generator
allows read and write aspect ratios. On each port, the read to write data width ratio can be 1:32, 1:16,
1:8, 1:4, 1:2, 1:1, 2:1, 4:1, 8:1, 16:1, or 32:1.
For true dual-port RAMs, the four data buses, DINA,DOUTA,DINB, and DOUTB, can have differentwidths. For single-port RAMs, DINA and DOUTA widths can be independent. The maximum ratio
between any two data buses is 32:1. The widest data bus can be no larger than 1152 bits.If the read and write data widths are different, the memory depth is different with respect to read and
write accesses. The depth ratio is the inverse of the width ratio. The address bus must be large enough
to address the deeper of the two depths, since it is shared by read and write accesses. For the shallower,
the least significant bits of the address bus are ignored. The smaller data words are arranged in lit-
tle-endian format, as illustrated in Figure 12.
Virtex-5 and Virtex-4 Read-to-Write Aspect Ratio Example
Consider a true dual-port RAM of 64x512, which is the A port write width and depth. Table 2lists the
four data port widths and their respective depths for this example.
FigureTop x-ref11
Figure 11: Port Aspect Ratio Example Memory Map
Table 2: Read-to-Write Aspect Ratio Example Ports
Interface Data Width Memory Depth
Port A Write 64 512
Port A Read 16 2048
Port B Write 256 128
Port B Read 32 1024
31 0
B3
A0=
.
.
.
7 0. .7 0. .7 0. .7 0. .
7 0. .7 0. .7 0. .7 0. .
B2
B1
B0
B7
B6
B5
B4
A1=
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The ADDRAwidth is determined by the larger of the A port depths (2048). For this reason, ADDRAis 11bits wide. On port A, read operations utilize the entire ADDRAbus, while write operations ignore theleast significant 2 bits.
In the same way, the ADDRBwidth is determined by the larger of the B port depths (1024). For this rea-son, ADDRBis 10 bits wide. On port B, read operations utilize the entire ADDRBbus, while write oper-
ations ignore the least significant 3 bits.The memory map in Figure 12shows how port B write words are related to port A write words, in a lit-
tle-endian arrangement. Note that AWnis the write data word at address 'n' with respect to port A,
while BWnis the write data word at address 'n' with respect to port B.
BW0is made up of AW3, AW2, AW1, and AW0. In the same way, BR0is made up of AR1and AR0, and
AW0is made up of BR1and BR0.
In the above example, the largest data width ratio is port B write words (256 bits) to port A read words
(16 bits). This ratio is 16:1.
Aspect Ratio Limitations
In general, no port data width may be wider than 1152 bits, and no two data widths can have a ratio
greater than 32:1. However, some optional features further limit data width aspect ratios:
Byte-writes:When using byte-writes, no two data widths can have a ratio greater than 4:1.
Fixed primitive algorithm:When using the fixed primitive algorithm with an N-bit wide primitive,
aspect ratios are limited to 32:N and 1:N from the port A write width. For example, using the 4kx4
primitive type, the other ports may be no more than 8 times (32:4) larger than port A write width
and no less than 4 times (1:4) smaller.
Byte-Writes
The Block Memory Generator provides byte-write support in Virtex-5, Virtex-4, and Spartan-3A/3A DSP
devices. Byte-writes are available using either 8-bit or 9-bit byte sizes. When using an 8-bit byte size, no
parity bits are used and the memory width is restricted to multiples of 8 bits. When using a 9-bit byte size,
each byte includes a parity bit, and the memory width is restricted to multiples of 9 bits.
When byte-writes are enabled, theWE[A|B]bus is N bits wide, where N is the number of bytes inDIN[A|B]. The most significant bit in the write enable bus corresponds to the most significant byte inthe input word. Bytes will be stored in memory only if the corresponding bit in the write enable bus is
asserted during the write operation.
When 8-bit bytes are selected, the DIN and DOUT data buses are constructed from 8-bit bytes, with no
parity. When 9-bit bytes are selected, the DIN and DOUT data buses are constructed from 9-bit bytes,
with the 9th bit of each byte in the data word serving as a parity bit for that byte.
FigureTop x-ref12
Figure 12: Read-to-Write Aspect Ratio Example Memory Map
BW0=
.
.
.
BW1=
255 0
AW3
AW2
AW1
AW7
AW6
AW5
AW4
AW0
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The byte-write feature may be used in conjunction with the data width aspect ratios, which may limit
the choice of data widths as described in Data Width Aspect Ratios. However, it may not be used with
the NO_CHANGE operating mode. The byte-write feature also affects the operation of WRITE_FIRST
mode, as described in Write First Mode Considerations.
Byte-Write Example
Consider a single-port RAM with a data width of 24 bits, or 3 bytes with byte size of 8 bits. The writeenable bus,WEA, consists of 3 bits. Figure 13illustrates the use of byte-writes, and shows the contentsof the RAM at address 0. Assume all memory locations are initialized to 0.
Write First Mode Considerations
When performing a write operation in WRITE_FIRST mode, the concurrent read operation shows the
newly written data on the output of the core. However, when using the byte-write feature in Virtex-5,
Virtex-4, and Spartan-3A/3A DSP devices or the read-to-write aspect ratio feature in Virtex-5 and Vir-
tex-4, the output of the memory cannot be guaranteed.
Collision Behavior
The Block Memory Generator core supports dual-port RAM implementations. Each port is equivalentand independent, yet they access the same memory space. In such an arrangement, is it possible to have
data collisions. The ramifications of this behavior are described for both asynchronous and synchro-
nous clocks below.
Collisions and Asynchronous Clocks
Using asynchronous clocks, when one port writes data to a memory location, the other port must not
read or write that location for a specified amount of time. This clock-to-clock setup time is defined in
the device data sheet, along with other block RAM switching characteristics.
Collisions and Synchronous Clocks
Synchronous clocks cause a number of special case collision scenarios, described below.
Synchronous Write-Write Collisions
A write-write collision occurs if both ports attempt to write to the same location in memory. The result-
ing contents of the memory location are unknown. Note that write-write collisions affect memory con-
tent, as opposed to write-read collisions which only affect data output.
FigureTop x-ref13
Figure 13: Byte-write Example
WEA[2:0]
DINA[23:0]
RAM Contents
CLKA
ADDRA[15:0]
b011
FF EE DD
0000
CC BB AA 33 22 11 00 FF 009988 77 66 55 44
b010 b101 b000 b110 b010
00 EE DD 00 BB DD 33 22 77 33 FF 7799BB 77
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Using Byte-Writes
When using byte-writes, memory contents are not corrupted when separate bytes are written in the
same data word. RAM contents are corrupted only when both ports attempt to write the same byte.
Figure 14illustrates this case. Assume ADDRA= ADDRB= 0.
Synchronous Write-Read Collisions
A synchronous write-read collision may occur if a port attempts to write a memory location and the
other port reads the same location. While memory contents are not corrupted in write-read collisions,
the validity of the output data depends on the write port operating mode.
If the write port is in READ_FIRST mode, the other port can reliably read the old memory contents.
If the write port is in WRITE_FIRST or NO_CHANGE mode, data on the output of the read port is
invalid.
In the case of byte-writes, only bytes which are updated will be invalid on the read port output.
Figure 15illustrates write-read collisions and the effects of byte-writes.DOUTBis shown for when portA is in WRITE_FIRST mode and READ_FIRST mode. Assume ADDRA= ADDRB= 0, port B is alwaysreading, and all memory locations are initialized to 0. The RAM contents are never corrupted in
write-read collisions.
FigureTop x-ref14
Figure 14: Write-write Collision Example
FigureTop x-ref15
Figure 15: Write-read Collision Example
7777 XX00
WEA[3:0]
DINB[31:0]
RAM Contents
CLKA
b1100
DINA[31:0]
WEB[3:0] b0011
b0101
b1010
b1110
b0011
b1111
b0110 b1111
7654 3210 BBAA BBAA AAXX XXAA XXXX XXXX
FFFF 3210 BBBB BBBB 0000 0000 BBBB BBBB 2222 2222
7654 FFFF AAAA AAAA 7777 7777 AAAA AAAA 1111 1111
00XX 00XX
WEA[3:0]
DOUTBAWF
RAM Contents
CLKA
b0000
DINA[31:0]
b0101 b0000 b1100 b1111
3322 00AA
AAAA AAAA 3322 1100 1111 1111
0000 0000
DOUTBARF 0000 0000 00AA 00AA
00AA 00AA 00AA
3322 00AA
b0000
1111 1111
1111 1111
1111 111100AA 00AA0000 0000
XXXX XXXX XXXX
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Optional Output Registers
The Block Memory Generator allows optional output registers, which may improve the performance of
the core. The user may choose to include register stages at two placesat the output of the block RAM
primitives and at the output of the core.
Registers at the output of the block RAM primitives reduce the impact of the clock to out delay of the
primitives. Registers at the output of the core isolate the delay through the output multiplexers,improving the clock-to-out delay of the Block Memory Generator core. Each of the two optional register
stages can be chosen for port A and port B separately. Note that each optional register stage used adds
an additional clock cycle of latency to the read operation.
Figure 16shows a memory configuration with registers at the output of the memory primitives and at
the output of the core for one of the ports.
FigureTop x-ref16
Figure 16: Virtex-II Block Memory: Register Port [A|B] Outputs of Memory Primitives
and Memory Core Options Enabled
Block Memory Generator Core
Latches
Latches
EN
REGCE
MUX
Block RAM Primitives
Block RAM
CLK
SSR
DOUT
S* : The synchronous reset (S) of the flop is gated by CE
Block RAM
Block RAM
Latches
CE
S*
D Q
CE
D Q
CE
D Q
CE
D Q
FALSE
Use REGCE Pin
TRUE
PrimitiveOutputRegisters
CoreOutputRegisters
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For Virtex-5, Virtex-4, and Spartan-3A DSP FPGAs, the Register Port [A|B] Output of Memory Primi-
tives option may be implemented using the embedded block RAM registers, requiring no further
FPGA resources. All other register stages are implemented in FPGA fabric. Figure 17shows an example
of a Virtex-4 or Virtex-5-based memory that has been configured using both output register stages for
one of the ports.
When using the Synchronous Reset Input (SSR), the behavior of the embedded output registers in Spar-
tan-3A DSP differs slightly from the configuration shown in Figure 17. By default, the Block Memory
Generator builds the memory output register in the FPGA fabric to maintain functionality compatibil-
ity with Virtex-4 and Virtex-5 configurations. To force the core to use the embedded output registers in
Spartan-3A DSP, the RAMB16BWER Reset Behavior option is provided.
For a complete description of the supported output options, see "Output Register Configurations" on
page 42.
FigureTop x-ref17
Figure 17: Virtex-5 and Virtex-4 Block Memory with Register Port [A|B] Output of Memory Primitives
and Register Port [A|B] Output of Memory Core Options Enabled
Block Memory Generator Core
CoreOutput
RegistersLatches
Latches
FALSE
Block RAM Primitives
Block RAM EmbeddedOutput Registers
Latches
CE
SSR*
Block RAM EmbeddedOutput Registers
Latches
CE
SSR*
Block RAM EmbeddedOutput Registers
Latches
EN
Use REGCE Pin
REGCE
MUX
CLK
SSR
DOUT
CE
D Q
CE
S*
D Q
S* : The synchronous reset (S) of the flop is gated by CE
TRUE
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Optional Pipeline Stages
The Block Memory Generator core allows optional pipeline stages within the MUX, which may
improve core performance. Users can add up to three pipeline stages within the MUX, excluding the
registers at the output of the core. This optional pipeline stages option is available only when the regis-
ters at the output of the memory core are enabled and only for the following configurations:
Memories with ECC Memories built using the Fixed Primitive algorithm
Memories built using the Minimum Area algorithm, with the following restrictions:
- Virtex-5 based memories with depths greater than 64k
- Virtex-4 based memories with depths greater than 32k
- Virtex-II and Spartan-3 based memories with depths greater than 16k
The pipeline stages are common for port A and port B and can be a value of 1, 2, or 3 if the Register Out-
put of Memory Core option is selected in the GUI for both port A and port B. Note that each pipeline
stage adds an additional clock cycle of latency to the read operation. If the configuration has ECC, the
SBITERR and DBITERR outputs are delayed to align with DOUT. Note that adding pipeline stages
within the MUX improves performance only if the critical path in the design is the data through the
MUX.
The MUX size displayed in the GUI can be used to determine the number of pipeline stages to use
within the MUX. See "Pipeline Stages within Mux" on page 29for detailed information.
Figure 18shows a memory configuration with an 8:1 MUX and two pipeline stages within the MUX.
This figure explains how the 8:1 MUX is pipelined internally with two register stages.
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Optional Register Clock Enable Pins
The optional output registers are enabled by the EN signal by default. However, when the Use REG-CEA/REGCEB Pin option is selected, the output register stage of the corresponding port is controlled
by the REGCEA/REGCEB pins instead.
Thus, the data output from the core can be controlled independent of the flow of data through the rest
of the core. When using the REGCEpin, the last output register operates independently of the ENsig-nal.
FigureTop x-ref18
Figure 18: Memory Configuration with 8:1 MUX and Two Pipeline Stages within the MUX
D Q
D Q
D Q
D Q
2:1
2:1
2:1
2:1
2:1
2:1
2:1
D Q
>
D Q
>
D Q
CE>S*
DOUT
block RAMs
Pipeline Stage 1 Pipeline Stage 2
8:1 MUX
(After pipelining)
Use REGCE Pin
REGCE
SSR
CLK
EN
CoreOutputRegisters
False
True
S*: Synchronous reset (S) of the flop is gated by CE
v
v
v
v
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Optional Synchronous Set/Reset Pins
The synchronous set/reset pins (SSRAand SSRB) control the reset operation of the last register in theoutput stage. For memories with no output registers, the reset pins control the memory output latches.
When SSRand REGCEare asserted on a given port, the data on the output of that port is driven to thereset value defined in the CORE Generator GUI. (The reset occurs on SSR and EN when the Use REGCE
Pin option is not selected.)
For Virtex-4 FPGAs, if the option to use the synchronous set/reset pin is selected in conjunction with
memory primitive registers and without core output registers, then the Virtex-4 embedded block RAM
registers may not be utilized for the corresponding port.
For Spartan-3A DSP FPGAs, the synchronous set/reset behavior may differ when the RAMB16BWER
reset behavior option is selected. However, this option saves resources by using the embedded output
registers available in Spartan-3A DSP RAMB16BWER primitives. See "Output Register Configurations"
on page 42for more information.
Memory Output Flow Control Examples
The combination of the enable (EN), reset (SSR), and register enable (REGCE) pins allow a wide rangeof data flows in the output stage. Figure 19and Figure 20are examples on how this can be accom-
plished. Keep in mind that the SSRand REGCEpins apply only to the last register stage.
Figure 19depicts how SSRcan be used to control the data output to allow only intended data through.Assume that both output registers are used for port A, the port A reset value is 0xFFFF, and that ENandREGCEare always asserted. The data on the block RAM memory latch is labeled LATCH, while theoutput of the block RAM embedded register is labeled REG1. The output of the last register is the out-
put of the core, DOUT.
FigureTop x-ref19
Figure 19: Flow Control Using SSR
REG1
CLKA
ADDRA[7:0] AA BB CC
data(AA) data(BB)
SSR
LATCH data(AA) data(BB) data(CC)
DOUT data(AA) data(BB)
DD
FFFFFFFF
data(CC)
data(DD)
da ta (C C) F FF F
data(DD)
REG1
CLKA
ADDRA[7:0] AA BB CC
data(AA) data(BB)
SSR
LATCH data(AA) data(BB) data(CC)
DOUT data(AA) data(BB)
DD
FFFFFFFF
data(CC)
data(DD)
data(CC) FFFF
data(DD)
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Figure 20depicts how REGCEcan be used to latch the data output to allow only intended data through.Assume that only the memory primitive registers are used for port A, and that ENis always assertedand SSRis always deasserted. The data on the block RAM memory latch is labeled latch, while the out-put of the last register, the block RAM embedded register, is the core output, DOUT.
Built-in Error Correction Capability
For Virtex-5 FPGAs, the Block Memory Generator core supports built-in Hamming Error CorrectionCapability (ECC) for the block RAM primitives. Each write operation generates 8 protection bits for
every 64 bits of data, which are stored with the data in memory. These bits are used during each read
operation to correct any single bit error, or to detect (but not correct) any double bit error.
This operation is transparent to the user. Two status outputs (SBITERR and DBITERR) indicate the
three possible read results: no error, single error corrected, and double error detected. For single-bit
errors, the read operation does not correct the error in the memory array; it only presents corrected data
on DOUT. ECC is only available when the following options are chosen:
Virtex-5
Single-port RAM or Simple Dual-port RAM memory type
When using ECC, the Block Memory Generator constructs the memory from special primitives avail-able in Virtex-5 architectures. The ECC memory block is 512x64, and is composed of two 18k block
RAMs combined with dedicated ECC encoding and decoding hardware. The 512x64 primitives are
used to build memory sufficient for the desired user memory space.
When using ECC, certain other core options are limited as follows:
Byte-write enable is not available
All port widths must be identical
Only Read First Operating Mode is supported
Synchronous Reset (SSR) and the Output Reset Value options are not available
Memory Initialization is not supported
No Algorithm selection is available
FigureTop x-ref20
Figure 20: Flow Control Using REGCE
CLKA
ADDRA[7:0] AA BB CC
REGCE
LATCH data(AA) data(BB) data(CC)
DOUT data(AA) data(BB)
DD
data(DD)
data(CC) data(DD)
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Figure 21illustrates a typical write and read operation for a Virtex-5 FPGA Block Memory Generator
core in simple dual-port RAM with ECC enabled, and no additional output registers.
The Block Memory Generator core does not support the insertion of errors for correction by ECC in
simulation. For this reason, the simulated functionality of ECC is identical to non-ECC behavior with
the SBITERR and DBITERR outputs always equal to 0.
Simulation Models
The Block Memory Generator core provides two types of functional simulation models:
Behavioral Simulation Models (VHDL and Verilog)
Structural/Unisim based Simulation Models (VHDL and Verilog)
The behavioral simulation models provide a simplified model of the core while the structural-basedsimulation models (UniSim) are an accurate modeling of the internal structure of the core. The behav-
ioral simulation models are written purely in RTL and simulate faster than the structural-based simu-
lation models and are ideal for debugging. Moreover, the memory is modeled in a two-dimensional
array, making it easier to probe contents of the memory.
The structural simulation model uses primitive instantiations to more accurately model the behavior of
the core. Collision detection and X generation are better modeled using the structural simulation
model. However, simulation time is longer and debug may be more difficult. The Simulation Files
options in the CORE Generator Project Options determine the type of functional simulation models
generated.
FigureTop x-ref21
Figure 21: Read and Write Operation with ECC in Virtex-5
WEA
DINA
CLKA, CLKB
ADDRA
ADDRB
DOUTB
DBITERR
SBITERR
ENB
ENA
1111 2222
aa
aa
00 ac
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Table 3defines the differences between the two functional simulation models:
Signal List
Table 4provides a description of the Block Memory Generator core signals. The widths of the data ports
(DINA,DOUTA,DINB, and DOUTB) are selected by the user in the CORE Generator GUI. The address
port (ADDRAand ADDRB) widths are determined by the memory depth with respect to each port, asselected by the user in the GUI. The write enable ports (WEAandWEB) are busses of width 1 whenbyte-writes are disabled. When byte-writes are enabled,WEAandWEBwidths depend on the byte sizeand write data widths selected in the GUI.
Table 3: Differences Between Simulation Models
Behavioral ModelsStructural (Unisim) based
Models
When core output is undefined Never generates X Generates X to match core
Out-of-range address accessOptionally flags a warning
messageGenerates X
Collision behaviorDoes not generate X on output,
and flags a warning messageGenerates X to match core
Byte-write coll ision behavior Flags all byte-write collisionsDoes not flag collisions if
byte-writes do not overlap
Table 4: Core Signal Pinout
Name Direction Description
CLKA InputPort A Clock:Port A operations are synchronous to this clock. For
synchronous operation, this must be driven by the same signal as CLKB.
ADDRA InputPort A Address:Addresses the memory space for port A read and write
operations. Available in all configurations.
DINA Input Port A Data Input:Data input to be written into the memory via port A.Available in all RAM configurations.
DOUTA OutputPort A Data Output:Data output from read operations via port A. Available in
all configurations except simple dual-port RAM.
ENA InputPort A Clock Enable:Enables read, write, and reset operations via port A.
Optional in all configurations.
WEA InputPort A Write Enable:Enables write operations via port A. Available in all RAM
configurations.
SSRA InputPort A Synchronous Set/Reset:Resets the port A memory output latch or
output register. Optional in all configurations.
REGCEA InputPort A Register Enable:Enables the last output register of port A. Optional in
all configurations with port A output registers.
CLKB Input
Port B Clock:Port B operations are synchronous to this clock. Available in
dual-port configurations. For synchronous operation, this must be driven by the
same signal as CLKA.
ADDRB InputPort B address:Addresses the memory space for port B read and write
operations. Available in dual-port configurations.
DINB InputPort B Data Input:Data input to be written into the memory via port B.
Available in true dual-port RAM configurations.
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Generating the Core
The Block Memory Generator is available from the CORE Generator. To open the Block Memory core
from the main CORE Generator window, do the following:
Click View by Function > Memories & Storage Elements> RAMs & ROMs
The following section describes the options available from the Block Memory Generator GUI.
CORE Generator Parameter Screens
The Block Memory Generator GUI includes five main screens:
Block Memory Generator Main Screen
Port A Options Screen
Port B Options Screen
Output Registers and Memory Initialization Screen
Simulation Model Options and Information Screen
In addition, all the screens share common tabs and buttons to provide information about the core and
to navigate the Block Memory Generator GUI.
DOUTB OutputPort B Data Output:Data output from read operations via Port B. Available in
dual-port configurations.
ENB InputPort B Clock Enable:Enables read, write, and reset operations via Port B.
Optional in dual-port configurations.
WEB InputPort B Write Enable:Enables write operations via Port B. Available in dual-port
RAM configurations.
SSRB InputPort B Synchronous Set/Reset:Resets the Port B memory output latch or
output register. Optional in dual-port configurations.
REGCEB InputPort B Register Enable:Enables the last output register of port B. Optional in
dual-port configurations with port B output registers.
SBITERR OutputSIngle Bit Error: Flags the presence of a single-bit error in memory which has
been auto-corrected on the output bus.
DBITERR OutputDouble Bit Error: Flags the presence of a double-bit error in memory.
Double-bit errors cannot be auto-corrected by the built-in ECC decode module.
Table 4: Core Signal Pinout (Continued)
Name Direction Description
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Block Memory Generator Main Screen
Component Name
The base name of the output files generated for the core. Names must begin with a letter and be com-
posed of any of the following characters: a to z, 0 to 9, and _. Names can not be Verilog or VHDL
reserved words.
Memory Type
Select the type of memory to be generated.
Single-port RAM
Simple dual-port RAM
True dual-port RAM
Single-port ROM
Dual-port ROM
ECC Options
When targeting Virtex-5, and when either single-port RAM or simple dual-port RAM memory type is
selected, the ECC options become available. Selecting ECC enables built-in Hamming error correction
for the Virtex-5 architecture. See Built-in Hamming Error Correction Capabilityfor more information.
FigureTop x-ref22
Figure 22: Block Memory Generator Main Screen
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When using ECC, the following options are limited:
Byte-write Enable is not available
All port widths must be identical
Only Read First Operating mode is supported
Synchronous Reset (SSR) and the Output Reset Value options are not available
Memory Initialization is not supported
No algorithm selection is available
Write Enable
When targeting Virtex-5, Virtex-4, or Spartan-3A/3A DSP, select whether to use the byte-write enable
feature. Byte size is either 8-bits (no parity) or 9-bits (including parity). The data width of the memory
will be multiples of the selected byte-size.
Algorithm
Select the algorithm used to implement the memory:
Minimum Area Algorithm:Generates a core using the least number of primitives.
Fixed Primitive Algorithm:Generates a core that concatenates a single primitive type toimplement the memory. Choose which primitive type to use in the drop-down list.
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Port A Options Screen
Memory Size (Port A)
Specify the port A write width and depth. Select the port A read width from the drop-down list of valid
choices. The read depth is calculated automatically.
Operating Mode (Port A)
Specify the port A operating mode.
READ_FIRST
WRITE_FIRST
NO_CHANGE
Enable (Port A)
Select the enable type:
Always enabled (noENApin available)
Use ENApin
FigureTop x-ref23
Figure 23: Port A Options
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Output Reset (Port A)
Specify the reset value of the memory output latch and output registers. These values are with respect
to the read port widths. Choose whether a set/reset pin (SSRA) is needed.
Port B Options Screen
Memory Size (Port B)
Select the port B write and read widths from the drop-down list of valid choices. The read depth is cal-
culated automatically.
Operating Mode (Port B)
Specify the port B write mode.
READ_FIRST
WRITE_FIRST
NO_CHANGE
FigureTop x-ref24
Figure 24: Port B Options
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Enable (Port B)
Select the enable type:
Always enabled (noENBpin available)
Use ENBpin
Output Reset (Port B)
Specify the reset value of the memory output latch and output registers. These values are with respect
to the read port widths. Choose whether a set/reset pin (SSRB) is needed.
Output Registers and Memory Initialization Screen
Optional Output Registers
Select the output register stages to include:
Register Port [A|B] Output of Memory Primitives.Select to insert output register after the
memory primitives for port A and port B separately. When targeting Virtex-4 or Virtex-5 FPGAs,
the embedded output registers in the block RAM primitives are used if the user chooses to register
the output of the memory primitives. For other architectures, the registers in the FPGA slices are
used. Note that in Virtex-4, the use of the SSR input prevents the core from using the embedded
output registers. See "Output Register Configurations" on page 42for more information.
FigureTop x-ref25
Figure 25: Output Registers and Memory Initialization Screen
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Register Port [A|B] Output of Memory Core.Select to insert register output of the memory core
for port A and port B separately. The registers in the FPGA slices will be used. Select whether to
have separate enable pins for the last register stage for port A and port B if output registers are
selected for the corresponding port(s).
Use REGCE [A|B] Pin. Select to use a separate REGCEA or REGCEB input pin to control the
enable of the last output register stage in the memory. When unselected, all register stages are
enabled by ENA/ENB.
Use Reset Behavior from RAMB16BWER Primitive. Selecting this option causes the Block
Memory Generator to use the embedded output registers in the Spartan-3A DSP RAMB16BWER
primitives; however, it also changes the behavior of the core during reset. See "Output Register
Configurations" on page 42for more information.
Pipeline Stages within Mux. Available only when the Register Output of Memory Core option is
selected for both port A and port B, and only for specific configurations (see "Optional Pipeline
Stages" on page 17). Select a value of 0, 1, 2, or 3 from the drop-down list.
The MUX size displayed in the GUI can be used to determine the number of pipeline stages to use
within the MUX. For memories with ECC and memories using the Fixed Primitive algorithm, the
MUX size displayed is accurate; for memories using the Minimum Area algorithm, the MUX size
displayed is approximate. In both cases, select the appropriate number of pipeline stages for your
design based on the device architecture.
Memory Initialization
Select whether to initialize the memory contents using a COE file, and whether to initialize the remain-
ing memory contents with a default value. When using asymmetric port widths or data widths, the
COE file and the default value are with respect to the port A write width.
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Simulation Model Options and Information Screen
Structural/UNISIM Simulation Model Options
Select the type of warning messages and outputs generated by the structural simulation model in the
event of collisions.
Behavioral Simulation Model Options
Select the type of warning messages generated by the behavioral simulation model. Select whether the
model should assume synchronous clocks for collision warnings.
Information Section
This section displays an informational summary of the selected core options.
Memory Type: Reports the selected memory type.
Block RAM Resources (18k BRAMs): Reports the exact number of 18k block RAM primitives
which will be used to construct the core. For Virtex-5, each 36k block RAM primitive is counted as
two 18k block RAMs.
Total Port A Read Latency: The number of clock cycles for a read operation for port A. This value is
controlled by the optional output registers options for port A on the previous screen.
FigureTop x-ref26
Figure 26: Simulation Model Options and Information Screen
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Total Port B Read Latency: The number of clock cycles for a read operation for port B. This value is
controlled by the optional output registers options for port B on the previous screen.
Address Width: The actual width of the address bus to each port.
Specifying Initial Memory Contents
The Block Memory Generator core supports memory initialization using a memory coefficient (COE)file or the default data option in the CORE Generator GUI, or a combination of both.
The COE file can specify the initial contents of each memory location, while default data specifies the
contents of all memory locations. When used in tandem, the COE file can specify a portion of the mem-
ory space, while default data fills the rest of the remaining memory space. COE files and default data is
formatted with respect to the port A write width (or port A read width for ROMs).
A COE is a text file which specifies two parameters:
memory_initialization_radix:The radix of the values in the memory_initialization_vector. Valid
choices are 2, 10, or 16.
memory_initialization_vector:Defines the contents of each memory element. Each value is
LSB-justified, separated by a space, and assumed to be in the radix defined bymemory_initialization_radix.
The following is an example COE file. Note that semi-colon is the end of line character.
; Sample initialization file for a; 32-bit wide by 16 deep RAMmemory_initialization_radix = 16;memory_initialization_vector =0 1 2 3 4 5 6 78 9 A B C D E F;
Block RAM Usage
The Information panel (screen 5 of the Block Memory Generator GUI) reports the actual number of
block RAM blocks to be used. This number is always given as the number of 18k block RAM primitives
used.
To estimate this value when using the fixed primitive algorithm, the number of block RAM primitives
used is equal to the width ratio (rounded up) multiplied by the depth ratio (rounded up), where the
width ratio is the width of the memory divided by the width of the selected primitive, and the depth
ratio is the depth of the memory divided by the depth of the primitive selected.
To estimate this value when using the minimum area algorithm, it is not as easy to determine the exact
block RAM count. This is because the actual algorithm performs complex manipulations to produce an
optimal solution. The optimistic estimate is total memory bits divided by 18k (the total number of bits
per primitive) rounded up. Given that the algorithm packs block RAMs very efficiently, this estimate is
often very accurate for most memories.
LUT Utilization and Performance
The LUT utilization and performance of the core are directly related to the arrangement of primitives
and the selection of output registers. Particularly, the number of primitives cascaded in depth to imple-
ment a memory determines the size of the output multiplexer and the size of the input decoder, which
are implemented in the FPGA fabric.
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Note: Although the primary goal of the minimum area algorithm is to use the minimum number of
block RAM primitives, it has a secondary goal of maximizing performance as long as block RAM
usage does not increase.
Resource Utilization and Performance Examples
The following tables provide examples of actual resource utilization and performance for Block Mem-
ory Generator implementations. Each section highlights the effects of a specific feature on resource uti-
lization and performance.
Benchmarks were performed targeting a Virtex-II Pro FPGA in the -5 speed grade (2vp30-ff1152-5), and
a Virtex-4 FPGA in the -10 speed grade (4vlx60-ff1148-10), and a Virtex-5 FPGA in the -1 speed grade
(5vlx30-ff324-1). Better performance may be possible with higher speed grades.
In the benchmark designs described below, the core was encased in a wrapper with input and output
registers to remove the effects of IO delays from the results; performance may vary depending on the
user design. The minimum area algorithm was used unless otherwise noted. The examples below high-
light the use of embedded registers in Virtex-5 and Virtex-4, and the subsequent performance improve-
ment that may result.
Single Primitive
The Block Memory Generator does not add additional logic if the memory can be implemented in a sin-
gle block RAM primitive. Table 5defines performance data for single-primitive memories.
Table 5: Single Primitive Examples
Memory
TypeOptions
Width x
Depth
Resource Utilization Performance
Block
RAMsLUTs1
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
FFsVirtex-II
ProVirtex-4 Virtex-5
True
Dual-Port
RAM
36x512 1 0 0 330 310 300
9x2k 1 0 0 345 335 300
Virtex-4 or
Virtex-5
Embedded
Output
Registers
36x512 1 0 0 N/A 385 395
9x2k 1 0 0 N/A 395 455
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Output Registers
The Block Memory Generator optional output registers increase the performance of memories by iso-
lating the block RAM primitive clock-to-out delays and the data output multiplexer delays.
The output registers are only implemented for output ports. For this reason, when output registers are
used, a single-port RAM requires fewer resources than a true dual-port RAM. Note that the effects of
the core output registers are not fully illustrated due to the simple register wrapper used. In a full-scaleuser design, core output registers may improve performance notably.
In Virtex-4 architectures, the embedded block RAM may be utilized, reducing the FPGA fabric
resources required to create the registers.
Table 6: Virtex-II Pro Output Register Examples
MemoryType
Width xDepth
Output
RegisterOption
Virtex-II Pro
BlockRAMs
FFs LUTs1
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
Performance(MHz)
True Dual-Port
RAM17x5k
5 0 62 215
Primitive 5 92 62 280
Core 5 34 42 270
Primitive, Core 5 132 42 275
Single-Port
RAM17x5k
5 0 31 225
Primitive 5 46 31 280
Core 5 17 21 275
Primitive, Core 5 66 21 280
Table 7: Virtex-4 Output Register Examples
Memory
Type
Width x
Depth
OutputRegister
Option
Virtex-4
BlockRAMs
FFs LUTs1
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
Performance(MHz)
True Dual-Port
RAM17x5k
5 0 62 285
Primitive 5 6 62 375
Core 5 34 42 260
Primitive, Core 5 46 42 370
Single-Port
RAM 17x5k
5 0 35 285
Primitive 5 3 35 395
Core 5 17 25 260
Primitive, Core 5 23 25 385
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In Virtex-5 architectures, the embedded block RAM may be used to reduce the FPGA fabric resources
required to create the registers.
Aspect Ratios
The Block Memory Generator selectable port and data width aspect ratios may increase block RAM
usage and affect performance, because aspect ratios limit the primitive types available to the algorithm,
which can reduce packing efficiency. Large aspect ratios, such as 1:32, have a greater impact than small
aspect ratios. Note that width and depth are reported with respect to the port A write interface.
Table 8: Virtex-5 Output Register Examples
Memory
Type
Width x
Depth
OutputRegister
Options
Virtex-5
BlockRAMs FFs LUTs1
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
Performance(MHz)
True Dual-Port
RAM17x5k
3 0 38 280
Primitive 3 6 44 435
Core 3 34 38 295
Primitive, Core 3 40 44 455
Single-Port
RAM17x5k
3 0 19 275
Primitive 3 3 22 455
Core 3 17 19 305
Primitive, Core 3 20 22 450
Table 9: Virtex-II Pro Aspect Ratio
Memory
Type
Width x
Depth
Port Aspect
Ratio
Virtex-II Pro
BlockRAMs FFs LUTs1
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
Performance(MHz)
True Dual-Port
RAM
17x5k 1:1 5 0 62 215
136x640 1:82
2. A port is 136x640; B port is 17x5k.
9 0 0 275
Table 10: Virtex-4 Aspect Ratio
Memory
Type
Width x
Depth
Data Width
AspectRatio
Virtex-4
BlockRAMs
FFs LUTs1
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
Performance(MHz)
Single-Port
RAM
17x5k1:1 5 0 35 285
1:82
2. Read port is 136x640; write port is 12x5k.
9 0 0 310
136x640 8:13
3. Read port is 17x5k, write port is 136x640.
9 0 0 350
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Algorithm
The differences between the minimum area algorithm and the fixed primitive algorithm are discussed
in detail in "Selectable Memory Algorithm" on page 2. Table 12shows examples of the resource utiliza-
tion and the performance difference between them for two selected configurations for Virtex-II Pro and
Virtex-4 architectures.
Table 13shows examples of the resource utilization and the performance difference between them for
two selected configurations for Virtex-5 architecture.
Table 11: Virtex-5 Aspect Ratio
MemoryType
Width xDepth
AspectRatio
Virtex-5
BlockRAMs
FFs LUTs1
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
Performance(MHz)
Single-PortRAM
17x5k
1:1 3 0 19 300
1:82
2. Read port is 136x640; write port is 17x5k.
5 0 TBD 295
136x640 8:13
3. Read port is 17x5k, write port is 136x640.
5 0 TBD 3054
4. This configuration was generated using the xc5vlx50-ff676-1 part.
Table 12: Memory Algorithm Examples Virtex-II Pro and Virtex-4
MemoryType
Widthx
DepthAlgorithm Type
Resource Utilization Performance (MHz)
Block
RAMFFs LUTs1
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
Virtex-II Pro Virtex-4
Single-Port
RAM
17x5k
Minimum area 5 0 31 220 285
Fixed Primitive using
18x1k block RAM5 0 57 245 235
36x4k
Minimum area 8 0 38 295 290
Fixed Primitive using
36x512 block RAM8 0 152 225 245
Table 13: Memory Algorithm Examples Virtex-5
MemoryType
Width
xDepth
Algorithm Type
Resource UtilizationPerformance
(MHz)
Block
RAMFFs LUTs1
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
Virtex-5
Single-Port
RAM
17x5k
Minimum area 3 0 19 300
Fixed Primitive using
18x1k block RAM3 0 20 285
36x4k
Minimum area 4 0 0 300
Fixed Primitive using
36x512 block RAM4 0 40 280
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Supplemental Information
The following sections provide additional information about working with the Block Memory Genera-
tor core.
Compatibility with Older Memory Cores. Defines the differences between older memory cores and
the Block Memory Generator core.
SIM Parameters. Defines the SIM parameters used to specify the core configuration.
Output Register Configurations. Provides information optional output registers used to improve
core performance.
Compatibility with Older Memory Cores
This section contains important information for users working with a previous version of the Block
Memory Generator core.
Using the Block Memory Generator Migration Kit
The Block Memory Generator core replaces the following two legacy cores:
Dual Port Block Memory (v6.x)
Single Port Block Memory (v6.x)
Cores generated by the Block Memory Generator are not drop-in replacements for the v6.x cores listed
above as there are a number of feature and interface changes in the Block Memory Generator.
To help you migrate designs containing legacy LogiCORE IP v6.x Dual and Single Port Block Memory
cores to the new Block Memory Generator core, Xilinx provides the Block Memory Generator Migra-
tion Kit to manage migration-related tasks without manually editing your design. For information
about using the Migration Kit, see the Block Memory Generator Migration Kit Product Page.
Differences Between Cores
This section describes the differences between the Single and Dual Port Block Memory cores and theBlock Memory Generator. The new Block Memory Generator is not backward compatible with the Sin-
gle and Dual Port Block Memory core in several aspects.
Single Port Block Memory core and the Block Memory Generator do not have the same port names
for a single-port memory configuration.
Dual Port Block Memory core and the Block Memory Generator do not have the same reset pin
name.
XCO files for the previous memory cores are NOT compatible with the Block Memory Generator.
Pin polarity, handshaking, and input register features supported by the previous memory cores are
not supported in the Block Memory Generator.
The behavior of set/reset pin (SSR) and the enable pin (EN) in the Block Memory Generator willdiffer from previous cores when using optional output registers.
The Dual-port Block Memory core supports all combinations of read-only, write-only, and
read/write ports for A & B ports. Some of these combination are only available in the Block
Memory Generator by manually tying-off unused ports of a True Dual-port RAM.
Note: The Block Memory Migration Kit automatically ties-off the appropriate ports when used tomigrate from a Dual-port Block Memory core.
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Port Memory Pin Names
In the Block Memory Generator, the port names have been changed from the older Single Port Block
Memory and Dual Port Block Memory cores to reflect the actual ports on the block RAM primitives.
Table 14and Table 15reflect the changes in port names.
Obsolete Features
Pin Polarity Option
The Block Memory Generator does not support pin polarity options on the clock, enable, write enable
and set/reset input pins. When active low signaling is desired, users can invert the signals prior to the
input of the core.
Handshaking Pins
The Block Memory Generator does not support handshaking pins: ND[A|B], RFD[A|B] andRDY[A|B].
Input Registers
The Block Memory Generator does not support input registers on the DIN, ADDR, and WE input ports.
Table 14: Port Name Changes from Single Port Block Memory Core
Single Port Block Memory v6.2
(Old core)
Block Memory Generator v2.1
(New Core, Single Port Configuration)
DIN DINA
ADDR ADDRA
EN ENA
WE WEA
SINIT SSRA
CLK CLKA
DOUT DOUTA
ND Not supported
RFD Not supported
RDY Not supported
Table 15: Port Name Changes from Dual Port Block Memory Core
Dual Port Block Memory v6.2
(Old core)
Block Memory Generator v2.1
(New Core, Single Port Configuration)
SI NI TA SSRA
SI NI TB SSRB
ND [A|B] Not supported
RFD [A|B] Not supported
RDY [A|B] Not supported
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Read/Write Ports
The Block Memory Generator does not support all combinations of read-only, write-only, and
read/write ports for ports A & B. Use a true dual-port RAM type and manually tie-off unused ports to
achieve configurations with only one write-only or read-only port.
Note: The Block Memory Generator Migration Kit automatically ties-off appropriate ports when used
to migrate from a Dual-port Block Memory core.
Modified Behaviors
Enable Pin
Table 16illustrates the difference in enable behavior between previous cores and the Block Memory
Generator.
Synchronous Reset Pin
In the previous memory cores, the synchronous reset (SINITpin) initializes all memory latches andoutput registers. In the Block Memory Generator, the synchronous set/reset (SSRpin) only resets theregisters in the last output stage. When there are no output register stages present, it will initialize the
memory latches.
Table 16: Old and New Core Differences
Single (or Dual) Port Block Memory v6.2 Block Memory Generator v2.1
Single enable pin that controls the enables of allregisters and memories
Two optional enable pins provided:
REGCEoptionally controls the enables of
the registers in the last output stage
ENcontrols the enables of all other
registers and memory
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SIM Parameters
Table 17defines the SIM parameters used to specify the configuration of the core. These parameters are
only used to manually instantiate the core in HDL, calling the CORE Generator dynamically. This
parameter list does not apply to users that generate the core using the CORE Generator GUI.
Table 17: SIM Parameters
SIM Parameter Type Values Description
1 C_FAMILY StringVirtex2 Virtex4
Virtex5Target device family
2 C_XDEVICEFAMILY String
"Virtex-II" "Virtex-II
Pro" "Virtex4"
"Virtex5"
"Spartan-3A"
"Spartan-3A DSP"
Finest resolution target family derived
from the parent C_FAMILY
3 C_MEM_TYPE Integer
0: Single Port RAM
1: Simple Dual Port
RAM
2: True Dual Port
RAM3: Single Port ROM
4: Dual Port RAM
Type of memory
4 C_ALGORITHM
0 (selectable
primitive),
1 (minimum area)
Type of algorithm
5 C_PRIM_TYPE Integer
0 (1-bit wide)
1 (2-bit wide)
2 (4-bit wide)
3 (9-bit wide)
4 (18-bit wide)
5 (36-bit wide)
6 (72-bit wide,
single-port only)
If fixed primitive algorithm is chosen,
determines which type of primitive to
use to build memory
6 C_BYTE_SIZE Integer 9, 8 Defines size of a byte: 9 bits or 8 bits
7 C_SIM_COLLISION_CHECK StringNone, Generate_X,
All, Warnings_only
Defines warning collision checks in
structural/unisim simulation model
8 C_COMMON_CLOCK Integer 0, 1
Determines whether to optimize
behavioral model collision check by
assuming clocks are synchronous
9 C_DISABLE_WARN_BHV_COLL Integer 0, 1
Disables the behavioral model from
generating warnings due to read-write
collisions
10 C_DISABLE_WARN_BHV_RANGE Integer 0, 1
Disables the behavioral model from
generating warnings due to address
out of range
11 C_LOAD_INIT_FILE Integer 0, 1Defined whether to load initialization
file
12 C_INIT_FILE_NAME String Name of initialization file (MIF format)
13 C_USE_DEFAULT_DATA Integer 0, 1Determines whether to use default
data for the memory
14 C_DEFAULT_DATA String Defines a default data for the memory
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15 C_HAS_MEM_OUTPUT_REGS_A Integer 0, 1
Determines whether port A has a
register stage added at the output of
the memory latch
16 C_HAS_MEM_OUTPUT_REGS_B Integer 0,1
Determines whether port B has a
register stage added at the output of
the memory latch
17 C_HAS_MUX_OUTPUT_REGS_A Integer 0,1
Determines whether port A has a
register stage added at the output of
the memory core
18 C_HAS_MUX_OUTPUT_REGS_B Integer 0,1
Determines whether port B has a
register stage added at the output of
the memory core
19 C_MUX_PIPELINE_STAGES Integer 0,1,2,3
Determines the number of pipeline
stages within the MUX for both port A
and port B
20 C_WRITE_WIDTH_A Integer 1 to 1152 Defines width of write port A
21 C_READ_WIDTH_A Integer 1 to 1152 Defines width of read port A
22 C_WRITE_DEPTH_A Integer 8 to 9011200 Defines depth of write port A
23 C_READ_DEPTH_A Integer 8 to 9011200 Defines depth of read port A
24 C_ADDRA_WIDTH Integer 3 to 24 Defines the width of address A
25 C_WRITE_MODE_A String
Write_First,
Read_first,
No_change
Defines the write mode for port A
26 C_HAS_ENA Integer 0, 1Determines whether port A has an
enable pin
27 C_HAS_REGCEA Integer 0, 1Determines whether port A has an
enable pin for its output register
28 C_HAS_SSRA Integer 0, 1Determines whether port A has an
synchronous reset pin
29 C_SINITA_VAL String Defines initialization/power-on value
for port A output
30 C_USE_BYTE_WEA Integer 0, 1Determines whether byte-write
feature is used on port A
31 C_WEA_WIDTH Integer 1 to 128 Defines width of WEA pin for port A
32 C_WRITE_WIDTH_B Integer 1 to 1152 Defines width of write port B
33 C_READ_WIDTH_B Integer 1 to 1152 Defines width of read port B
34 C_WRITE_DEPTH_B Integer 8 to 9011200 Defines depth of write port B
35 C_READ_DEPTH_B Integer 8 to 9011200 Defines depth of read port B
36 C_ADDRB_WIDTH Integer 3 to 24 Defines the width of address B
37 C_WRITE_MODE_B String
Write_First,
Read_first,
No_change
Defines the write mode for port B
38 C_HAS_ENB Integer 0, 1Determines whether port B has an
enable pin
Table 17: SIM Parameters (Continued)
SIM Parameter Type Values Description
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39 C_HAS_REGCEB Integer 0, 1Determines whether port B has an
enable pin for its output register
40 C_HAS_SSRB Integer 0, 1Determines whether port B has an
synchronous reset pin
41 C_SINITB_VAL String Defines initialization/power-on value
for port B output
42 C_USE_BYTE_WEB Integer 0, 1Determines whether byte-write
feature is used on port B
43 C_WEB_WIDTH Integer 1 to 128 Defines width of WEA pin for port B
44 C_USE_ECC Integer 0,1
Determines ECC options
0 = No ECC
1 = ECC
45 C_USE_RAMB16BWER_RST_BHV Integer 0,1
Determines if the embedded registers
in Spartan-3A DSP RAMB16BWER
primitives are used
Table 17: SIM Parameters (Continued)
SIM Parameter Type Values Description
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Output Register Configurations
The Block Memory Generator core provides optional output registers that can be selected for port A
and port B separately, and that may improve the performance of the core. Because Virtex-5, Virtex-4,
and Spartan-3A DSP block RAM primitives have embedded output registers that previous architec-
tures did not support, the configurations described in the sections that follow are separated into Vir-
tex-4 and Virtex-5, Spartan-3A DSP, and Virtex-II and implementations. Figure 27shows the OptionalOutput Registers section of the Block Memory Generator GUI.
FigureTop x-ref27
Figure 27: Optional Output Registers Section
Port A
Port B
options
options
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Virtex-5 and Virtex-4 Output Register Configurations
To tailor register options for Virtex-5 and Virtex-4 configurations, two selections, one each for port A
and port B, are provided. The embedded output registers are enabled for the corresponding port(s)
when Register Port [A|B] Output of Memory Primitivesis selected. Similarly, registers at the output of
the core are enabled for the corresponding port(s) by selecting RegisterPort [A|B] Output of Memory
Core.
Figures 28through 33illustrate the Virtex-5 and Virtex-4 output register configurations.
Virtex-5 and Virtex-4 Memory with Primitive and Core Output Registers
With both Register Output of Memory Primitives and Register Output of Memory Core options
selected, a memory core is generated with both the Virtex-4 or Virtex-5 embedded output registers and
a register on the output of the core for the selected port(s), as shown in Figure 28. This configuration
may provide improved performance for building large memory constructs.
Port A or Port B
Register Port A Output of Memory Primitives Register Port B Output of Memory Primitives
Register Port A Output of Memory Core Register Port B Output of Memory Core
FigureTop x-ref28
Figure 28: Virtex-4 or Virtex-5 Block Memory Generated with Register Port [A|B] Output of Memory
Primitives and Register Port [A|B] Output of Memory Core Enabled
Block Memory Generator Core
CoreOutput
RegistersLatches
Latches
FALSE
Block RAM Primitives
Block RAM EmbeddedOutput Registers
Latches
CE
SSR*
Block RAM EmbeddedOutput Registers
Latches
C
E
S
SR*
Block RAM EmbeddedOutput Registers
Latches
EN
Use REGCE Pin
REGCE
MUX
CLK
SSR
DOUT
CE
D Q
CE
S*
D Q
S* : The synchronous reset (S) of the flop is gated by CE
TRUE
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Virtex-5 Memory with Primitive Output Registers
When Register Port [A|B] Output of Memory Primitives
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