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Low Noise Amplifier
The material here provided is mainly based on Dr. Chunyu Xins dissertation
ELEN 665Edgar Snchez-Sinencio
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Analog and Mixed-Signal Center, TAMU 2
Ideal characteristics of LNA in Receivers
min F
Large voltage gain to reduce Ftot
Handling large signals without significant distortion
must present 50 ohms to the input source
Real characteristics of LNA in Receivers
F and power consumption trade-offs
Gain and input matching trade-offs Zin
P
F
G
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Analog and Mixed-Signal Center, TAMU 3
Practical Requirements of LNA in Receivers
Signal coming from antenna is very small: -100dBm(3.2uV)~-70dBm(0.1mV), amplification is need for thefollowing stage (mixer) to handle. (Gain requirement)
The received signal should have certain SNR to be reliabledetected. Noise comes from the environment and the circuititself. Noise floor is determined by thermal noise and system
bandwidth (KTB). Noise added by the LNA circuit should beas small as possible. (Noise requirement).
Large signal or blocker can occur at the input of LNA. Large
signal performance of LNA should be good enough. (Linearityrequirement)
Reasonable ( or minimum) power consuming (Power constrain)
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Analog and Mixed-Signal Center, TAMU 4
A Conceptual LNA Structure
LNA consists of:
Input/output match network
Amplifier transistor (s)
Power source
Load
[ ]
=
2212
2111
ss
ssS
Amplifier S matrix:Source reflection coefficient:
s
Load reflection coefficient: L
L
Lin
s
sss
+=22
211211
1
Input reflection coefficient:
s
sout
s
sss
+=11
211222
1
Output reflection coefficient:
Important terms:
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Analog and Mixed-Signal Center, TAMU 5
Remarks on LNAs: Narrow band (NB) LNA are typically used in Wireless CommercialCommunications, i.e. Bluetooth, Wi-Fi, GSM.
For wide band LNA the input matching stage and load areoptimized for a frequency band, thus the input matching and loadimpedance behave as low-Q ( wide bandwidth) filters
For NB the impedance matching and power gain are usually optimizedat one frequency. The output load stage and the input matching usuallyinvolve LC networks.
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Analog and Mixed-Signal Center, TAMU 6
LNA Metrics: Gain Gain is the ratio of output signal and input signal. It defines andsmall signal amplification capability of LNA.
Transducer power gain: Power delivered to the load divided by poweravailable from source.
For IC implementation, LNA input is interfaced off-chip and usuallymatched to specific impedance (50ohm or 75ohm). Its output is not necessary
matched if directly drive the on-chip block such as mixer. This is characterizedby voltage gain or transducer power gain by knowing the load impedance level.
2
22
2
2
212
11
2
11
11
L
L
s
s
T
ss
sG
= For unilateral device
i.e. S12~0
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Analog and Mixed-Signal Center, TAMU 7
LNA Metrics: Two-Port Noise Figure Noise factor is defined by the ratio of output SNR and input SNR.Noise figure is the dB form of noise factor.
Noise figure shows the degradation of signals SNR due to thecircuits that the signal passes.
2
min opts
s
n
o
i
YYG
RFF
SNR
SNRF
+=
=
LNA noise matching:
The source impedance 1/Ys of the LNA can be transformed toan optimal value such that the noise figure is minimum.
FdBNF log10)( =
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Analog and Mixed-Signal Center, TAMU 8
Minimum Noise Figure
][21
:
1
||1
min
2
])()[(
2
22
Coptn
optCn
u
S
optcS
G
RGGBBG
s
un
GGRF
GGG
G
G
BBB
jBGYwhere
F
G
GYYRF
S
nCSSC
++=
=+=
==
+=
+=
+++=
++++
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Analog and Mixed-Signal Center, TAMU 9
LNA Metrics: Why are gain and low noise critical?
totNFSNRdBmNoisefloorySensitivit ++= )(
-174dBm+10logBW
System SNR is determined byBER requirement of a specific
modulation scheme, for example:
16dB12dB16QAM21dB17dB64QAM
11dB7dBQPSK
1e-61e-3
LNA
afterLNA
LNAtot G
F
FF
1
+=
LNAs noise factor directly appears inthe total noise factor of the system.
LNAs gain suppress the noise comingfrom following stages
Noise factor of cascaded system:
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Analog and Mixed-Signal Center, TAMU 10
ELEN 665 (ESS)
TWO-PORTNOISECOMPONENTS
Noiseless
Network.
CurrentGain = Ai
iout
vn
in
Ysins
iin
ucn
cccucn
nn
ns
nsn
source,o
total,o
nssource,onsnnstotal,o
vvv
vYi;iii
vi
i
vYi
N
NF
iN;vYiiN
+=
=+=
++==
=++=
correlatedpartiallyareandwhere
12
2
222
2
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Analog and Mixed-Signal Center, TAMU 11
kTB
vR
kTB
iG,
kTB
vR
kTB
vR,
kTB
iG
G
RYYG
G
YRRYYGF
kTB
i
YkTB
v
kTB
vYY
kTB
i
F
i
vYYi
i
YvvYYiF
nn
ns
s
u
u
cc
uu
s
nscu
s
sucscu
ns
suc
scn
ns
nscu
ns
sucscu
4
and44
44
where
11
4
444
1
11
Then
2
22
22
222
2
222
22
2
222
2
22222
=
==
==
+++=
++++=
+++
+=
+++=
++++=
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Analog and Mixed-Signal Center, TAMU 12
( ) ( )[ ] ( )
[ ]
+
++=++=
+==
==
=
=
+++++++=
+=
cc
n
uncoptnmin
c
n
usopt
scopt
s
s
uSscscscu
s,cs,cs,c
GGR
GRGGRF
GR
GGG
BBB
G
G
RBGRBBGGGF
,jBGY
21
2
2
s
2222
2121
then
0B
Fand0
F
ifNow
:admittancesourceOptimal
1
then
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Analog and Mixed-Signal Center, TAMU 13
( ) ( )[ ]
[ ]2122
22
2
22
22
tcoefficiennCorrelatio
54
channelslongandsaturationfor324
4
sources.oaccount twintotaketohavewemodel,noiseMOSFETFor the
ndng
*
ndng
do
gs
ggng
m
donddond
optsopts
s
nmin
ii
ii
c
g
Cg;BgkTi
;g
BgkTv;BgkTi
BBGGG
RFF
=
==
=
==
++=
2
2
4 m
donn
g
g
kTB
vR
==
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Analog and Mixed-Signal Center, TAMU 14
( )
( )[ ] ( )2
22
222
2
15
2121
15
5
1
1
0
51
5
cGGRF
cCGR
GG
jBGjBGY
BB
c
g
;g
cC
G
gg
gR
~G
jBcCjY
CcggCj
iigCjY
T
coptnmin
gsc
n
uopt
coptoptoptopt
copt
gs
m
Tgo
gs
u
mm
don
c
cgsc
gs
do
mgs
nd
ngc
mgsc
+++=
=+=
=+=
=
=
=
=
=
+=+=
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Analog and Mixed-Signal Center, TAMU 15
LNA Metrics: Non-linearity model
Wanted Signal-102dBm
IM3
f=2f1-f2
In-band blocker
-23dBm
f1 f2
f1 f2f1 f2
f2-f1 2f2-f12f1-f2f1+f2
2f1 2f2
Output spectrum with two tone input
Usually distortion term: 2f1-f2, 2f2-f1fall in band. This is characterized by 3rd
order non-linearity.
Large in-band blocker can desensitizethe circuit. It is measured by 1-dBcompression point.
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Analog and Mixed-Signal Center, TAMU 16
LNA Metrics: Linearity measurement
P1dB@input
P1dB@output1dB
Pout (dB)
Pin (dB)
1dB compression:
Measure gain compression for large input signal IIP3/IIP2:
Measure inter-modulation behavior
Relationship between IIP3 and P1dB
For one tone test: IIP3-P1dB=10dB
For two tone test: IIP3-P1dB=15dB
Fund
amental
IM3 IM2
IIP2
OIP2
OIP3
IIP3
Pout (dBm)
Pin(dBm)
IIP3~ -10dBm~8dBm
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Analog and Mixed-Signal Center, TAMU 17
CMOS LNA Topologies
M1
M2
Rs
VBB
INPUT
ZLOUTPUT
VDD
M1
Rf
INPUT
RL
OUTPUT
VDD
R1
11 R
R
RZ
L
f
in
+
sin RZ =
1
1
m
ing
Z =
M1INPUT
RL
OUTPUT
VDD
VBB
INPUT
VBB
C1
Lg
ZL
OUTPUT
VDD
Ls
( )s
gs
m
gs
sgin L
C
g
Cj
LLjZ +++=
1
sm RgF
1
142+
+1F
4.8dB < 2dBModerate
Resistive Termination CommonGate
Shunt-seriesFeedback
SourceDegeneration
> 6dBNF:
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Analog and Mixed-Signal Center, TAMU 18
LNA Topologies (contd)
Narrowband LNA: inductive degenerated Broadband LNA: common-gate and series-shunt feedback
Bipolar LNAs also have corresponding configurations
Focusing on inductive degenerated LNA
Input match
Noise match
Linearity
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Analog and Mixed-Signal Center, TAMU 19
A Popular Narrow Band LNA:
Inductive Source Degenerated LNA
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Analog and Mixed-Signal Center, TAMU 20
Source Degenerated LNA
( )s
gs
m
gs
sgin LC
g
CjLLjZ +++=
1
Input impedance
INPUT
VBB
Cgs
Lg
ZL
OUTPUT
VDD
Ls
( ) gssgo
CLL +
=1
gs
mT
C
g=
sTo LZ =
Zo: 50Ohm, 75OhmWo: 900MHz, 1.9GHz, 2.4GHz, 5GHz
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Analog and Mixed-Signal Center, TAMU 21
SOURCE DEGENERATED LNA ANALYSIS
LgIo
s
Ls
IinZin
Vin Lg
Cgs
Ls
Io
gmVgs
LG
+Ls
Cgs
gs
sm
C
LgZin
Writing KCL and KVL
( ) (2)1
(1)1
soin
gs
sgin
in
gs
mm
gs
ingsmo
sLIIsC
LLsV
IsC
gg
sCIVgI
+
++=
===
Solving (1) and (2)
( )gs
sm
gs
SG
in
inin
CLg
sCLLs
IVZ +++== 1
( ) ( )gs
Sm
gs
SGinC
Lg
CLLjjZ +
+=
1
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Analog and Mixed-Signal Center, TAMU 22
Matching occurs when Z(jo)=Rs , Rs is the resistor associated in the inputvoltage source. That is
( )( )
S
gso
G
gs
Sms
gsSG
o
gso
oSG
LC
L
C
Lg
R
CLL;
CLL
=
=
+=
=+
2
2
1
:thatimplieswhich
and
11
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Analog and Mixed-Signal Center, TAMU 23
Source Degenerated LNA (contd)
( ) NQSgLsgLgsT
LsT
gs
sgin RRRRL
Rj
CjLLjZ,1
11
++++++++=
Input impedance-non-idealities
( )
+
=
LsT
gssg
o
R
CLL
1
//
1
gs
mT
C
g=
Inductance loss: RLg: offset Zin
RLs: offset Zin and w0Gate resistance Rg: offset Zin
Ln
WR
R
shpoly
g 2
,
12=
NQS gate resistance: Rnqs: offset Zinm
NQSgg
R5
1, =
Cgs
Lg
Ls
RLg
RLsZIN
NQSgLsgLgsTin RRRRLZ ,++++=
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Source Degenerated LNA (contd)
+++=
T
o
Ls
g
s
L
QR
R
R
RF
1
Noise factor
Cgs
Lg
Ls
RLg
RLsZIN
gssos
gso
L
CRR
LLQ
1=
+=
( )222
155
21 LL QQc +++=
D.K. Shaeffer, T.H. Lee, A 1.5V 1.5GHz CMOS Low Noise Amplifier, IEEE JSSC, Vol. 32, No. 5. May 1997
There is a optimal QL to minimize FIs this F the minimum achievable one?
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Analog and Mixed-Signal Center, TAMU 25
Inductive Source degeneration:
The degeneration inductance modifies the input reflection coefficientwithout affecting the optimal input reflection coefficient for minimumnoise figure.
Achieve minimum noise figure: trading input match
2
min opts
s
n YYG
RFF +=
Source Degenerated LNA (contd)
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Source Degenerated LNA (contd)
( )( )
eff
effeff
eff
MOSstrongIIP
VVV
VV
3
812
3
42,,3 >++=
Linearity
thGSeff VVV = LEsat
1=
-8
-4
0
4
8
12
16
20
0.4 0.5 0.6 0.7 0.8 0.9 1
VGS
IIP3 (dBm)
( )3
22
222
,3
112
3
16)(
++=
o
DLNAIIP
P
PVV
effV= DDso
satsato VR
EvP 2
3
=
Esat ~ 1V/um L~0.35um-0.18umMOS transistors IIP3 v.s. gate drive voltage
Different width of transistor
IIP3 independent of W
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Analog and Mixed-Signal Center, TAMU 27
Source Degenerated LNA (contd)
Differential v.s. Single-ended
reject common mode noiseand interferer
double area and current
shield the bond wire
need balun at input
common-mode stability
linearity limited by biascurrent
Differential Single-ended
compact layout size
less power for same NFand linearity
susceptive to bond wireand PCB trace
drive single-balance
mixer
output balun drivedouble-balance mixer
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Analog and Mixed-Signal Center, TAMU 28
Differential LNA Common-mode Stability
Issue
VBB
2C2
C1C1
Lg Lg
LsLs
M1 M1
VBB
C2
C1
Lg
Ls
M1
Zin,com
Typical differential LNA Common-mode half circuit
( )21
2
121
21,
CC
gL
C
g
CCj
CCLLjZ ms
msgcomin
+
+++=
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Differential LNA Common-mode Stability
Issue (contd)
( )21
2
121
21,
CC
gL
C
g
CCj
CCLLjZ ms
msgcomin
+
+++=
=
2
2
1
,
1
CL
C
gR s
mcomin
Real part:
For passive termination, the real part of the source impedance willalways be positive. IF Rin,com happens to be negative and cancel the real
part of source impedance, oscillation MAYoccur.
When design differential LNA, not only pay attention to differentialoperation, but also check common-mode stability!
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Analog and Mixed-Signal Center, TAMU 30
Variant of Inductive Degenerated LNA
Vo
VBB
VIN
LSN
LSP LD
nMOS-pMOS shunt input
Current reuse to save power
Larger area due to two degenerationinductor if implemented on chip
NF: 2dB, Power gain: 17.5dB, IIP3: -6dBm, Id: 8mA from 2.7V power supply
F. Gatta, E. Sacchi, et al, A 2-dB Noise Figure 900MHz Differential CMOS LNA, IEEE JSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444-1452
Single-ended version of current-reuse LNA (bias not shown)
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Variant of Inductive Degenerated LNA
(contd)
Vo
VBB
VIN
LSN
LD
InterstageInductor
Inter-stage Inductor gain boost
Inter-stage inductor withparasitic capacitance formimpedance match network between
input stage and cascoded stage
boost gain lower noise figure. Input match condition will be
affected
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Analog and Mixed-Signal Center, TAMU 32
Design Procedure for Inductive
Source Degenerated LNA
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Targeting Structure
VIN
VB
Cgs
Lg
VDD
Ls
M1
M2
Rs
RL
Vo
+=
T
nfF
01
( )[ ]
gss
ddnf
CR
Q
QcQ
0
22
2
1
14212
1
=
++=
5=
d
Noise factor equations:
thgs VVIIP 3
Linearity:
s
LTV
RRjA
=
0
Voltage Gain:
Inductive degeneratedCMOS LNA
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Analog and Mixed-Signal Center, TAMU 34
Targeted Specifications
< 10mA from 1.8VPower
20 dBVoltage gain
-8 dBmIIP3
1.6 dBNoise Figure2.4 GHz ISM BandFrequency
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Analog and Mixed-Signal Center, TAMU 35
Step 1: Know your process
A 0.18um CMOS Process:
tox = 4.1e-9 m = 3.9*(8.85e-12)F/m = 3.274e-2 m^2/V.s Vth = 0.52 V
= gm/gdo / ~ 2 ~ 3
c = -j0.55
Process related
Noise related
Important design guide plots obtained from simulation ormeasurements
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Step 2: Obtain design guide plots
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 60 120 180 240 300 360 420 480 540 600
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Current density (A/m)
do
m
gg
Wgm
Wgdo
thgs VV
Gateoverdrivevoltage(V)and
gm/Wa
ndgd
o/W(
mS/m)
gm, gdo, , Vgs-Vthvs. current density plot
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Analog and Mixed-Signal Center, TAMU 37
Step 2: Obtain design guide plots (contd)
gdo increases all the way with current density Iden
gm saturates when Iden larger than 120A/m Velocity saturation, mobility degradation ---- short channel effects Low gm/current efficiency
High linearity
deviates from long channel value (1) with large Iden
Insights:
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Analog and Mixed-Signal Center, TAMU 38
Step 2: Obtain design guide plots (contd)
10
15
20
2530
35
40
4550
0.0 0.2 0.4 0.6 0.8 1.0 1.20.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.41.5
Gate overdrive voltage (V)
Cut-offfrequency(GHz)
Capacitanced
ensity(fF/m)Tf
WCgs
fT and Cgsvs. gate overdrive voltage
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Step 2: Obtain design guide plots (contd)
fT increases with Vod when Vod is small and saturatesafter Vod > 0.3V --- short channel effects
Cgs/W increases slowly after Vod > 0.2V
fT begins to degrade when Vod > 0.8V
gm saturates
Cgs increases
Insights:
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Analog and Mixed-Signal Center, TAMU 40
Step 2: Obtain design guide plots (contd)
3
4
5
6
7
89
10
11
12
13
14
15
1 2 3 4 5 6 7 8
47A/m
88A/m
135A/m
184A/m
300A/m
Quality factor
Noisefactorsc
alingcoefficient
Current density
nfvs input Q and current density
+=
T
nfF
01
gss CRQ
021
=
2-D plots fordesign reference
3-D plot for visualinspection
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Analog and Mixed-Signal Center, TAMU 41
Step 2: Obtain design guide plots (contd)
Insights:
Iden
- F
Q- F
For large Iden ( 300 A/m) there is an optimal value
of Q --- maybe too large for a practical design
For fixed Iden, increasing Q will reduce the sizeof transistor thus reduce total power ---- noise
figure will become larger
Design trade-offs
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Analog and Mixed-Signal Center, TAMU 42
Step 2: Obtain design guide plots (contd)
Linearity plots :IIP3 vs. gate overdrive and transistor size
-2
0
2
4
68
10
12
14
1618
0 0.1 0.2 0.3 0.4 0.5
20x2.5m 30x2.5m 40x2.5m
Gate overdrive voltage (V)
IIP3(d
Bm)
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Analog and Mixed-Signal Center, TAMU 43
Step 2: Obtain design guide plots (contd)
MOS transistor IIP3 only, when embedded into actual circuit: Input Q will degrade IIP3
Non-linear memory effect will degrade IIP3
Output non-linearity will degrade IIP3 IIP3 is a very weak function of device size
Generally, large overdrive means large IIP3
But the relationship between IIP3 and gate overdrive is not monotonic
There is a local maxima around 0.1V overdrive
Insights:
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Analog and Mixed-Signal Center, TAMU 44
Step 3: Estimate fT
and calculate nf
10
15
20
25
30
35
40
45
50
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
Gate overdrive voltage (V)
Cut-offfrequ
ency(GHz)
Capacitanced
ensity(fF/m)Tf
WCgs fo = 2.4 GHz F = 1.45
Small current budget ( < 10mA )does not allow large gate over drive :
0.2 V ~ 0.4 V
fT ~ 40 GHz
( ) 5.71 == To
nf f
f
F
mfFWCgs /3.1=
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Step 4: Determine Iden, Q and Calculate
Device Size
-2
0
2
4
6
8
1012
14
16
18
0 0.1 0.2 0.3 0.4 0.5
20x2.5m 30x2.5m 40x2.5m
Gate overdrive voltage (V)
IIP3(dBm)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 60 120 180 240 300 360 420 480 540 6000.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Current density (A/m)
do
m
gg
Wgm
Wgdo
thgs VV
Gateoverdrivevoltage(V)and
gm/Wa
ndgdo/W(m
S/m)
Select Iden = 70 A/m If Q = 4, IIP3 will have enough margin:
Estimated IIP3:IIP3( read from curve ) 20log(Q)~ -4dBm
Specs require: -8 dBm
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Step 4: Determine Iden, Q and Calculate
Device Size (contd)
3
4
5
6
7
8
9
10
1112
13
14
15
1 2 3 4 5 6 7 8
47A/m
88A/m
135A/m
184A/m
300A/m
Quality factor
Noisefactorscalingcoefficient
Current density
Q=4 and Iden = 70A/m meet thenoise factor requirement
fFQR
Cos
gs 166~2
1
=
mmfF
fFW
128
/3.1
166==
mAmAmIDS 9.8)/(70128 ==
Now we can do calculations:
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Step 5: Calculate Lg, LS and Required Load
Verify cut-off frequency
gm is about 50mA/V for the determined
current density and device size
fT = gm/(Cgs*2pi) = 48 GHz ---Verified !
nHR
LT
ss 2.0=
nHLC
L sgso
g 2612 =
s
L
o
TV
R
RjA
=
= 30sVT
oL RAR
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Step 6: Simulation Verification
Usually simulation-hand calculation iterations arenecessary to obtain satisfactory design
40 Ohm30 OhmRL16nH26nHLg
0.2nH0.2nHLs
151fF166fFCgs50.7mA/V50mA/Vgm
8mA8.9mAIds
127.5um128umWSimulationCalculationParameters
Deviate fromhand-calculationmost
Possiblereason:
Cgdisnot
consideredfor
handcalculation
S 6 Si l i ifi i ( d)
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Step 6: Simulation Verification (contd)
-20.0
-15.0
-10.0
-5.0
0.0
5.0
10.0
15.0
20.0
25.0
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60
0.78
0.80
0.82
0.84
0.86
0.88
Input Frequency (GHz)
Noise
Figure(dB)
S11andAV(dB)
-100
-80
-60
-40
-20
0
20
-40 -35 -30 -25 -20 -15 -10 -5 0
Input Power (dBm)
Output
Voltage(dBV)
P1dB=-20 dBm
IIP3=-6.4 dBm
S11
AV
NF
Simulation plots for IIP3, Av, NF and S11
S 6 Si l i V ifi i ( d)
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Step 6: Simulation Verification (contd)
-20dbm---P1dB
1.8V1.8VPower Supply
-17 dB---S11
-6.4 dBm-8 dBmIIP3
21 dB20 dBVoltage gain
8 mA< 10mACurrent drain
0.8 dB1.6 dBNoise FigureSimulatedTargetParameter
Comparison between targeted specs and simulation results
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Summary for LNA Design Procedure
Design mixed with simplified equations andsimulation plots normalized to unity device size help to
gain insights and consider all the important designspecification at the same time.
Several iterations is generally required from hand
calculation to simulation to arrive at satisfactory oroptimal design.
Secondary effects such as gate poly resistance can be
considered during simulation and can also be consideredby add more margin in the design specifications.
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LNA in BiCMOS Technology
Ad f BiCMOS P
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Advantages of BiCMOS Process
Higher gm/DC current (Low Power)
Translinear property
Outstanding Vbe matching between adjacent devices
Highly accurate low- and high-frequency equivalent circuit models basedon physical device behavior
Design flexibility due to availability of multiple device types
Availability of higher quality passive devices (thick metal inductors, high-
value MIM capacitors, etc.) is more common in BiCMOS processes. First-pass design success thanks to high-quality equivalent circuit models.
Wider dynamic range operation for a given lithographic generation.
Higher speed devices available in BiCMOS for a given lithographic
generation.
While pure CMOS process has higher level system integration and lower cost which in some
cost-sensitive designs will out run BiCMOS process.
V i ti f Bi l LNA
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Variations of Bipolar LNAs
Cascode LNA Increased Gain Potentially Unstable Lowered Headroom
Matched LNA Increased Gain Potentially Very Unstable Lowered Headroom Complexity
Transformer Feedback Lower Gain Improved Linearity Excellent Headroom
P i i l f O t f b d T i ti
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Principle of Out-of-band Termination
( )[ ] ( ) ( ) ( ) 2,Re61
33
11 =
AHZIIP
( ) ( ) ( )[ ] 223
22,
22
3 kkg
g +=
For BJT g3 is positive, by tuning out-of-band termination impedance
at 2 and , can be made small thus increase IIP3.( ) 2,
Volterra Analysis gives:
In-band property, determinedby LNA specs
Out-of-band parameters, can
be modified w/o affecting in-band property
Inp t Termination Techniq es
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Input Termination Techniques
IIP3 improves for a
narrow range of
Slow gain switchingExtra externalcomponents
Stability issues High NF Lower gain
Extra externalcomponent
Extra pin
Example: Cellular Band LNA Design
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Example: Cellular-Band LNA Design
V. Aparin, P. Gazzerro, Z. Jianjun, S. Bo, S. Szabo, E. Zeisel, T. Segoria, S. Ciccarelli, C. Persico, C. Narathong, R. Sridhara, A
highly-integrated tri-band/quadmode SiGe BiCMOS RF-to-baseband receiver for wireless CDMA/WCDMA/AMPS applicationswith GPS capability, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, pp.234-5
Two gain modes
Out-of-band termination improvelinearity: IIP3=+11.7dBm/+23.0dBm
Power gain: 15.7dB/-3.1dB
Noise figure: 1.4dB/3.2dB
Current: 5.4mA/0
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Wide Band LNA
Design considerations
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Design considerations
Broadband impedance match: resistive termination,common gate, feedback
Noise figure is usually high
Broad gain flatness requires resistive load
M1
M2
Rs
VBB
INPUT
ZLOUTPUT
VDD
M1
Rf
INPUT
RL
OUTPUT
VDD
R1
M1
INPUT
RL
OUTPUT
VDD
VBB
Resistive Termination Common Gate Shunt-series Feedback
Broad Band LNA: Noise Cancellation
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Broad Band LNA: Noise Cancellation
F. Bruccoleri, E.A.M. Klumperink, B. Nauta, Noise Cancelling in Widband CMOS LNAs, ISSCC 2002 Session 24.6
0.25um CMOS
NF: 2.4dB
-3dB BW: 2M-1.6GHz
IIP3: 0dBm
Voltage Gain: 13.7dB
Distributed Amplifier as LNA
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Distributed Amplifier as LNA
Why distributed?
GBW Limits for traditional amplifier: gm/C
In distributed circuits the parasitic cap C is absorbedinto the distributed structure, So breaking the gain-bandwidth relationship.
Ideally bandwidth should be infinity
In practice bandwidth will be limited by the loadingcharacter of the transmission line.
Distributed Amplifier as LNA (contd)
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Distributed Amplifier as LNA (cont d)Transmission line modeling on Silicon
Coplanar Strip line
Micro strip line
Shrinking of feather size make dielectricmaterial thicker.
Top metal far away from lossy siliconsubstrate.
Tline loss is reduced
Distributed Amplifier as LNA (contd)
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Distributed Amplifier as LNA (cont d)
Characteristic Impedance of Coplanar Stripline
60
70
80
90
100
110
120
130
4 8 12 16 20 24 28
Line spacing (m)
Zo(Ohms)
5
8
11
14
20
30
40
50
60
70
4 9 14 19 24 29
Width of signal line (M1)
Zo
(O
hm
s)
Transmission line modeling on Silicon
Characteristic Impedance of Micro Stripline
Loss: 0.8dB/mm at 30GHz
Distributed Amplifier as LNA (contd)
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Distributed Amplifier as LNA (cont d)
Artificial or real T-line?
Artificial line uses lumped inductors and capacitors: havegood model from foundry.
Real T-line uses metal lines to form energy transmissionpath: currently no models from foundry, has to be modeled bydesigners.
The quality of lumped on-chip inductors limits thefrequency operation: low Q and low self-resonate frequency.
For higher and higher frequency, spiral inductor structurecan not be modeled use lumped inductance any more.
Artificial line: low frequency operation ( 10GHz)
Distributed Amplifier as LNA (contd)
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Distributed Amplifier as LNA (cont d)
Distributed LNA
Cgs and Cds absorbed into the T-line
Under phase sync condition, maximum gain obtained :
Optimal number of sections (loss line) :
Input
Output
T
dZL
dZ
T
gZsZ g
x0
dx0
2dl 2dl
2gl
2gl
dl
gl
4
22 g
c
d
cm ZZgNG =
( )
ggdd
ggdd
ll
llN
=
lnln
Distributed Amplifier as LNA (contd)
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Distributed Amplifier as LNA (cont d)
Distributed LNA
-30
-25
-20
-15
-10
-5
0
5
10
15
1 3 5 7 9 11 13 15 17 19 21 23 25 27
S21
S11
S22
Frequency (GHz)
S21,
S11,andS22(d
B)
3
5
7
9
11
13
15
17
2 4 6 8 10 12 14 16 18 20 22 24 26
Frequency (GHz)
NoiseFigure(dB)
Extremely wide band and gain flatness (1 20 GHz)
Good matching over wide band (1 15 GHz)
High noise figure at lower portion of frequency
Wide-band LNA Using LC Lumped
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Wide band LNA Using LC Lumped
Matching NetworkIn the literatures
MOS Implementation [1] Bipolar Implementation [2]
[1] A. Bevilacqua and A. M. Niknejad, An Ultra-Wideband CMOS LNA for 3.1 to 10.6GHz Wireless Receivers, ISSCC 2004.
[2] A. Ismail and A. Abidi, A 3 to 10GHz LNA using a Wideband LC-ladder Matching Network, ISSCC 2004
Insight of LC Lumped Matching Network
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Insight of LC Lumped Matching Network
--An Alternative Implementation Method
Impedance match based on LC ladder network An alternative method: using the well-known Smith Chart
More straight forward and have well defined performance
Required VSWR can be drawn on Smith Chart
Visualize the matching goal
Wide-band Match Procedure Using
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g
Smith Chart
VB
RB
TLine
L1C1
L2Cc
M1
VB
RB
Cc
M1
S11
VB
RB
L2Cc
M1
S11
VB
RBL1
C1
L2Cc
M1
S11
S11
VB
RBL1
C1
L2Cc
M1
S11
Start
Step1
Step2
Step3
Finish
Step 1: Series inductance makes theconductance at the frequency edge
has the same real part
Step 2: Parallel inductor andcapacitor brings the frequency edge
S11 close together (forms a circle)
Step 3: Series inductance againbrings the circle center to pure
resistance point
Step4: A quarter-wave transmission
line is used to rotate the circle tothe center of the smith chart.
Implementation of Lumped Matched
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LNA
VB
RB
RFIN
Quarter wave
transmission line
Bondwire
L1C1
L2
CcM1
M2
Ld
Rd
VDD
Cc RFOUT
L3
C2
Current drain: 5mA from 1.8V power supply
Simulation Results of the Lumped
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Matched LNA
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Design Examples
BT/WiFi Receiver Block Diagram
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Bandwidth compatible (2.4GHz)
Sharing Front-end is possible (save power)
Multi-standard system delivers flexibility
15dB
Attenuator(-15dB)
RFFilter
Q Mixer
LNA
I Mixer
Synthesizer
& VCO
090
LPF
LPF
ADC
ADC
18dB
Signal LevelMeasurement
GainControl
Pmin -20dBm
LNA switch gain at -40dBm
Differential LNA using BJT cascode
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Proposed LNA
Inductor degeneration
Cascoded BJT: better matching
On-chip input matching
Noise figure: 1.6dB
Power/Voltage gain: 15dB
Power consumption: 16mW
NMOS attenuator for low gain(-15dB)
Differential structure
MOS transistor is more linear
LNA_cas_bias
Vo+
Vo-
VDD
LNA_bypass
Ls Ls
LdLd
LNA bypass switches and attenuator
LNA_rf_bias
i_tail
Cm
Vin+
Vin-M1 M2
M5
M6
M7
M8
M9
M3 M4
Q1 Q2
Rb Rb
Bond wire
Cd Cd
Vbb
Rb Rb
Differential LNA using BJT cascode (contd)
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1nH
3nH
570um
58
0um
LNA Layout
Symmetrical layout
Deep trench lattice under spiralinductor
Inductors are placed far apart
to avoid coupling (~200um) Differential inputs aredecoupled by GSGSG pattern
M1, M2Q1, Q2
Gain S.W.
G G GSS
Testing Setup
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Input matching (S11)
S-parameter networkanalyzer (HP 8719ES)
Testing board
High gain mode Low gain mode
S11 better than -11dB
* LNA is tested together with mixer
Testing Setup (contd)
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Gain of the front-end
Signal generator Testing board
Conversion gain: 33dB
* LNA is tested together with mixer
RF IN
IF OUT I&Q
Oscilloscope
Testing Setup (contd)
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IIP3/IIP2
Signal generator
Testing board
* LNA is tested together with mixer
Spectrum
Analyzer
RF IN
IF OUT I&Q
Powercombiner
-50 -45 -40 -35 -30 -25 -20 -15 -10-80
-60
-40
-20
0
20
40
60
2-Tone Input Power (dBm)
Output(dBm)
IIP3=-13dBm
-60 -50 -40 -30 -20 -10 0 10 20
-60
-40
-20
0
20
40
60
80
2-Tone Input Power [dBm]
Output(dBm)
IIP2=10dBm
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