1 Chapter 9 Counters 計數器 1.Asynchronous Counter Operation 非同步式計數器的運作 2.Synchronous Counter Operation 同步式計數器的運作 3.Up/Down Synchronous Counters

1

Chapter 9 Counters

計數器1. Asynchronous Counter Operation 非同步式計數器的運作2. Synchronous Counter Operation 同步式計數器的運作3. Up/Down Synchronous Counters 上 / 下數的同步式計數器4. Design of Synchronous Counters 同步式計數器的設計5. Cascaded Counters 串接計數器6. Counter Decoding 計數器的解碼7. Counter Applications 計數器的應用8. Troubleshooting 檢修9. Logical Symbols with Dependency Notation 具有相依註標的邏輯符

號10. Programmable Logic 可程式邏輯Digital System Application 數位系統的應用

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2Figure 8--40 The J-K flip-flop as a divide-by-2 device. Q is one-half the

frequency of CLK.Thomas L. FloydDigital Fundamentals, 8e

Flip-Flop Applications 正反器的用途

除法器J K Clk Q Q

0 0 Q0 Q0不變

0 1 0 1 Reset

1 0 1 0 Set

1 1 Q0 Q0轉態

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3

Figure 9--1 A 2-bit asynchronous binary counter.

Thomas L. FloydDigital Fundamentals, 8e

1. 非同步式計數器的運作

Figure 9--2 Timing diagram for the counter of Figure 9-1. As in previous chapters, output waveforms are shown in green.

1

0

1 1

1 0

0

Page 4: 1 Chapter 9 Counters 計數器 1.Asynchronous Counter Operation 非同步式計數器的運作 2.Synchronous Counter Operation 同步式計數器的運作 3.Up/Down Synchronous Counters

4Figure 9--3 Three-bit asynchronous binary counter and its timing diagram for one

cycle. Thomas L. FloydDigital Fundamentals, 8e

1. 非同步式計數器的運作

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5

Figure 9--4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.

Thomas L. FloydDigital Fundamentals, 8e

1. 非同步式計數器的運作

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6Figure 9--5 Four-bit asynchronous binary counter and its timing diagram.

Thomas L. FloydDigital Fundamentals, 8e

1. 非同步式計數器的運作

例題 9-1 如圖 9-5 所示為一個 4 位元的非同步二進制計數器 , 每一個正反器都是負緣觸發而且有一個10ns 的極際延遲時間 . (1) 設計各正反器輸出的時序圖 , (2) 算出從 Clock 輸入加訊號進去到 Q3 輸出的延遲時間 , (3) 算出最高工作頻率 .

Sol:(2) tp(Total) = 4 x 10ns = 40ns

(3) fmax = 1/ tp(Total) = 1/40ns = 25MHz

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7Thomas L. FloydDigital Fundamentals, 8e

1. 非同步式計數器的運作

Figure 9--6 An asynchronously clocked decade counter with asynchronous recycling.

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8Thomas L. FloydDigital Fundamentals, 8e

例題 9-2 證明一個非同步的計數器如何除 12, 從二進制的 0000 算到1011.

1. 非同步式計數器的運作

Figure 9--7 Asynchronously clocked modulus-12 counter with asynchronous recycling.

很尖銳的脈波

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9

FigureA--21 The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)

Thomas L. FloydDigital Fundamentals, 8e

1. 非同步式計數器的運作

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10

Figure A--22 Two configurations of the 74LS93A asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.)

Thomas L. FloydDigital Fundamentals, 8e

1. 非同步式計數器的運作

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11

Figure A-23 74LS93A connected as a modulus-12 counter.

Thomas L. FloydDigital Fundamentals, 8e

1. 非同步式計數器的運作

例題 9-3 證明74LS93A 如何作為一個除 12的計數器 .

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12

A 2-bit synchronous binary counter.

Thomas L. FloydDigital Fundamentals, 8e

2. 同步式計數器的運作

Figure 9--10 Timing diagram for the counter of Figure 9-11.

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13Figure 9--9 Timing details for the 2-bit synchronous counter operation (the

propagation delays of both flip-flops are assumed to be equal).Thomas L. FloydDigital Fundamentals, 8e

2. 同步式計數器的運作

第一個脈波第二個脈波

第三個脈波第四個脈波

解釋前一頁每次 Clock 來時 Q0及 Q1的變化

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14

Figure 9--11 A 3-bit synchronous binary counter.

Thomas L. FloydDigital Fundamentals, 8e

2. 同步式計數器的運作

Figure 9--12 Timing diagram for the counter of Figure 9-14.

Page 15: 1 Chapter 9 Counters 計數器 1.Asynchronous Counter Operation 非同步式計數器的運作 2.Synchronous Counter Operation 同步式計數器的運作 3.Up/Down Synchronous Counters

15Thomas L. FloydDigital Fundamentals, 8e

2. 同步式計數器的運作

FF2 在 Q0Q1同時為 1時 ,下一個脈波來會改變狀態 , FF3 則在 Q0Q1Q2同時為 1時 ,下一個脈波來才會改變狀態 ,

Figure 9--13 A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas.

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16

Figure 9--14 A synchronous BCD decade counter..

Thomas L. FloydDigital Fundamentals, 8e

2. 同步式計數器的運作

Figure 9--15 Timing diagram for the BCD decade counter (Q0 is the LSB).

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17

Figure A--24 The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)

Thomas L. FloydDigital Fundamentals, 8e

2. 同步式計數器的運作

Page 18: 1 Chapter 9 Counters 計數器 1.Asynchronous Counter Operation 非同步式計數器的運作 2.Synchronous Counter Operation 同步式計數器的運作 3.Up/Down Synchronous Counters

18Figure A--25 Timing example for a 74HC163.Thomas L. FloydDigital Fundamentals, 8e

2. 同步式計數器的運作

Page 19: 1 Chapter 9 Counters 計數器 1.Asynchronous Counter Operation 非同步式計數器的運作 2.Synchronous Counter Operation 同步式計數器的運作 3.Up/Down Synchronous Counters

19Figure A--26 The 74LS160 synchronous BCD decade counter. (The qualifying label

CTR DIV 10 indicates a counter with ten states.)Thomas L. FloydDigital Fundamentals, 8e

2. 同步式計數器的運作

Page 20: 1 Chapter 9 Counters 計數器 1.Asynchronous Counter Operation 非同步式計數器的運作 2.Synchronous Counter Operation 同步式計數器的運作 3.Up/Down Synchronous Counters

20Figure A--27 Timing example for a 74LS160.Thomas L. FloydDigital Fundamentals, 8e

2. 同步式計數器的運作

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21

Figure 9--16 A basic 3-bit up/down synchronous counter.

Thomas L. FloydDigital Fundamentals, 8e

3. 上 / 下數的同步式計數器

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22Figure 9--17 Thomas L. FloydDigital Fundamentals, 8e

3. 上 / 下數的同步式計數器

Page 23: 1 Chapter 9 Counters 計數器 1.Asynchronous Counter Operation 非同步式計數器的運作 2.Synchronous Counter Operation 同步式計數器的運作 3.Up/Down Synchronous Counters

23Figure A--28 The 74HC190 up/down synchronous decade counter.

Thomas L. FloydDigital Fundamentals, 8e

3. 上 / 下數的同步式計數器

Page 24: 1 Chapter 9 Counters 計數器 1.Asynchronous Counter Operation 非同步式計數器的運作 2.Synchronous Counter Operation 同步式計數器的運作 3.Up/Down Synchronous Counters

24Thomas L. FloydDigital Fundamentals, 8e

3. 上 / 下數的同步式計數器

Figure A--29 Timing example for a 74HC190.

Page 25: 1 Chapter 9 Counters 計數器 1.Asynchronous Counter Operation 非同步式計數器的運作 2.Synchronous Counter Operation 同步式計數器的運作 3.Up/Down Synchronous Counters

25Figure 9--18 General clocked sequential circuit.

Thomas L. FloydDigital Fundamentals, 8e

4. 同步式計數器的設計

激勵線

狀態變數線

輸入線與狀態變數線加到組合邏輯電路產生激勵訊號線

Previous State Present State Next State

Page 26: 1 Chapter 9 Counters 計數器 1.Asynchronous Counter Operation 非同步式計數器的運作 2.Synchronous Counter Operation 同步式計數器的運作 3.Up/Down Synchronous Counters

26Figure 9--19 State diagram for a 3-bit Gray code counter.

Thomas L. FloydDigital Fundamentals, 8e

4. 同步式計數器的設計

步驟一 : 畫出狀態圖

Page 27: 1 Chapter 9 Counters 計數器 1.Asynchronous Counter Operation 非同步式計數器的運作 2.Synchronous Counter Operation 同步式計數器的運作 3.Up/Down Synchronous Counters

27Figure 9--20 Examples of the mapping procedure for the counter sequence

represented in Table 9-7 and Table 9-8.Thomas L. FloydDigital Fundamentals, 8e

4. 同步式計數器的設計步驟二 : 寫出下一狀態表 .步驟三 : 寫出正反器的暫態表 .步驟四 : 根據下一狀態表及正反器的暫態表填寫卡諾圖 .

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28Figure 9--21 Karnaugh maps for present-state J and K inputs.

Thomas L. FloydDigital Fundamentals, 8e

4. 同步式計數器的設計

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29

步驟五 : 寫出各正反器的輸入端之邏輯表示式J0 = Q2Q1 + Q2Q1 = Q2 xor Q1K0 = Q2Q1 + Q2Q1 = Q2 xor Q1J1 = Q2Q0K1 = Q2Q0J2 = Q1Q0K2 = Q1Q0

Figure 9--22 Three-bit Gray code counter.

Thomas L. FloydDigital Fundamentals, 8e

4. 同步式計數器的設計

步驟六 : 畫出電路圖

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30

Figure 9--23

Output Transitions

QN QN+1

Flip-Flop Inputs

J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

Thomas L. FloydDigital Fundamentals, 8e

4. 同步式計數器的設計

例題 9-5 使用 JK 正反器 , 設計一個如圖 9-32所示不按照二進制計數順序的計數器 .

Present State

Q2 Q1 Q0

Next State

Q2 Q1 Q0

0 0 1 0 1 0

0 1 0 1 0 1

1 0 1 1 1 1

1 1 1 0 0 1

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31Figure 9--24

Thomas L. FloydDigital Fundamentals, 8e

4. 同步式計數器的設計

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32

Figure 9--25

Thomas L. FloydDigital Fundamentals, 8e

J0 = 1, K = Q2J1 = K1 = 1J2 = K2 = Q1

4. 同步式計數器的設計

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33

Figure 9--26 State diagram for a 3-bit up/down Gray code counter.

Thomas L. FloydDigital Fundamentals, 8e

例題 9-6 試設計一個 3位元的格雷碼同步式上下數計數器 , 當 UP/DOWN為 1時往上數 , 為 0時往下數 .

4. 同步式計數器的設計

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34

Present State

Next State

Y=0(Down) Y=1(Up)

Q2 Q1 Q0 Q2 Q1 Q0 Q2 Q1 Q0

0 0 0

1 0 0

0 0 1

0 0 1 0 0 0 0 1 1

0 1 1 0 0 1 0 1 0

0 1 0 0 1 1 1 1 0

1 1 0 0 1 0 1 1 1

1 1 1 1 1 0 1 0 1

1 0 1 1 1 1 1 0 0

1 0 0 1 0 1 0 0 0

Output Transitions

QN QN+1

Flip-Flop Inputs

J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

4. 同步式計數器的設計

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35

Figure 9--27 J and K maps for Table 9-11. The UP/DOWN control input, Y, is treated as a fourth variable.

Thomas L. FloydDigital Fundamentals, 8e

4. 同步式計數器的設計

Page 36: 1 Chapter 9 Counters 計數器 1.Asynchronous Counter Operation 非同步式計數器的運作 2.Synchronous Counter Operation 同步式計數器的運作 3.Up/Down Synchronous Counters

36Figure 9--28 Three-bit up/down Gray code counter.Thomas L. FloydDigital Fundamentals, 8e

步驟五 : 寫出各正反器的輸入端之邏輯表示式

步驟六 : 畫出電路圖

4. 同步式計數器的設計

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37

Figure 9--29 Two cascaded counters (all J and K inputs are HIGH).

Thomas L. FloydDigital Fundamentals, 8e

5. 串接計數器

Figure 9--30 Timing diagram for the cascaded counter configuration of Figure 9-38.

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38

Figure 9--31 A modulus-100 counter using two cascaded decade counters.

Thomas L. FloydDigital Fundamentals, 8e

5. 串接計數器

Figure 9--32 Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs.

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39

Figure 9--33

Thomas L. FloydDigital Fundamentals, 8e

例題 9-7 試算出圖 9-42 中兩個電路全部各除多少 ?

Sol:9-42(a)

8 x 12 x 16 = 15369-42(b) 10 x 4 x 7 x 5 = 1400

5. 串接計數器

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40

Figure 9--34 A divide-by-100 counter using two 74LS160 decade counters.

Thomas L. FloydDigital Fundamentals, 8e

5. 串接計數器

例題 9-8 使用 74LS160 計數器設計一個電路 , 將 1MHz 的訊號從 Clock 端輸入 , 輸出端得到 10KHz.

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41

Figure 9--35 A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D0 is

the LSB in each counter).

Thomas L. FloydDigital Fundamentals, 8e

5. 串接計數器

從 63C0 算到 FFFF, 即除以 40,000.63C0H = 25,536.40,000 = 65535 – 25536 + 1

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42

• 解題步驟 (n,m,x,y 皆為正整數 )– 決定所需位元數 n （ x: 所需除數）

– 決定所需 74161 個數 m

– 換算計數器初始值 y （換算成 16 進位值）

– 畫電路圖

xn 2log

4

nm

4

(2 1) 1

2

m

x y

y x

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43

• 計數器之解碼– 對計數器序列中任何指定狀態實作其解碼邏

輯– 使用閃控法（ Strobe ）消除解碼時的脈衝

干擾

計數器解碼器Output=1

At counter = 6

6. 計數器的解碼

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44

Figure 9--36 Decoding of state 6 (110).

Thomas L. FloydDigital Fundamentals, 8e

6. 計數器的解碼

Page 45: 1 Chapter 9 Counters 計數器 1.Asynchronous Counter Operation 非同步式計數器的運作 2.Synchronous Counter Operation 同步式計數器的運作 3.Up/Down Synchronous Counters

45Figure 9--37 A 3-bit counter with active-HIGH decoding of count 2 and count 7.

Thomas L. FloydDigital Fundamentals, 8e

6. 計數器的解碼

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46

Figure 9--38 A basic decade (BCD) counter and decoder.

Thomas L. FloydDigital Fundamentals, 8e

6. 計數器的解碼

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47Figure 9--39 Outputs with glitches from the decoder in Figure 9-38. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.

6. 計數器的解碼

Decoding Glitches

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48

Figure 9--40 The basic decade counter and decoder with strobing to eliminate glitches.

Thomas L. FloydDigital Fundamentals, 8e

6. 計數器的解碼

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49Figure 9--41 Strobed decoder outputs for the circuit of Figure 9-49.

Thomas L. FloydDigital Fundamentals, 8e

6. 計數器的解碼

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50

Figure 9--42 Simplified logic diagram for a 12-hour digital clock. Logic details using specific devices are shown in Figures 9-52 and 9-53.

Thomas L. FloydDigital Fundamentals, 8e

7. 計數器的應用

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51

Figure 9--43 Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).

Thomas L. FloydDigital Fundamentals, 8e

7. 計數器的應用

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52Figure 9--44 Logic diagram for hours counter and decoders. Note that on the counter

inputs and outputs, the right-most bit is the LSB.Thomas L. FloydDigital Fundamentals, 8e

7. 計數器的應用

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Figure 9--45 Functional block diagram for parking garage control.

Thomas L. FloydDigital Fundamentals, 8e

7. 計數器的應用

車輛停車控制 : 最多可停 100 輛 , 當停滿 100 輛時指示燈亮起 , 同時柵欄放下 , 當不滿 100 輛時指示燈滅掉 , 同時柵欄收起 .

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Figure 9--46 Logic diagram for modulus-100 up/down counter for automobile parking control.

Thomas L. FloydDigital Fundamentals, 8e

7. 計數器的應用

車輛停車控制

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55Figure 9--47 Parallel-to-serial data conversion logic.

Thomas L. FloydDigital Fundamentals, 8e

7. 計數器的應用

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56Figure 9--48 Example of parallel-to-serial conversion timing for the circuit in Figure 9-47.

7. 計數器的應用

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Figure 9--49 Example of a failure that affects following counters in a cascaded arrangement.

Thomas L. FloydDigital Fundamentals, 8e

8. 檢修

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Figure 9--50 Example of a failure in a cascaded counter with a truncated sequence.

Thomas L. FloydDigital Fundamentals, 8e

8. 檢修

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59Figure 9--51Thomas L. FloydDigital Fundamentals, 8e

例題 9-10 分析圖 9-60測量的結果是否正確 , 如果不正確 , 那錯在哪裡 ?

Sol: Truncated modulus = full modulus – preset modulus = 164 - 82C016 = 65536 -32472 = 32064The correct frequency = 10MHz / 32064 = 311.88HzModulus = fin / fout = 10MHz / 637.76Hz = 15680Truncated modulus = full modulus – preset modulus = 65536 – 15680 = 49856 = C2C016

比較 82C016 與 C2C016 就知道錯在哪裡了 .

8. 檢修

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60Figure 9--52Thomas L. FloydDigital Fundamentals, 8e

例題 9-11 觀察圖 9-61 的波形看計數器是否正確 ?Sol:Q2 正確的波形應為紅線的波形 , 所以若 Q2的波形像綠線的部分則 Q2 的波形是錯的 . 仔細比較 Q1 及 Q2 的波形 , 發現兩者一樣 , 會發生這種情況 , 可能是 AND 下半部內部斷線 , 相當於接HIGH, 因此 AND Gate 等於沒有作用所致 .

8. 檢修