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Y.B. Nithin Kumar, E. Bonizzoni, A. Patra, F. Maloberti: "Two-Path Delay Line Based Quadrature Band-Pass ΣΔ Modulator"; IEEJ International Analog VLSI Workshop, Bali, 2-‐4 November 2011, pp. 65-‐69.
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Two-Path Delay Line Based Quadrature Band-PassΣ∆ Modulator
Nithin Kumar Y.B.∗†, Edoardo Bonizzoni∗, Amit Patra†, and Franco Maloberti∗
∗Department of Electronics, University of Pavia, Via Ferrata, 1 - 27100 Pavia - ITALY†Department of Electrical and Electronics, IIT Kharagpur - INDIA
E-mail: [email protected], [email protected], [email protected], [email protected]
Abstract—This paper presents a new concept for an effectivequadrature band-pass Σ∆ modulator and discusses the high levelimplementation for a third order two-path scheme based ondelay line. The methodology uses an architecture which locksIF frequencies to the sampling frequency. Robustness of thestructure against the mismatch is analyzed. Simulations at thebehavioural level verify the architecture implementation whichuses a novel switched capacitor scheme.
Index Terms—Analog-to-Digital conversion, band-pass Σ∆modulation, complex filters.
I. Introduction
Rapid developments in semiconductor technology supportminiaturization of integrated communication devices with lowpower. These inexpensive devices known as Wireless SensorNetwork (WSN) can be used to sense, compute and trans-mit the valuable information for applications in the field ofspace, buildings, home, transportation, biometrics, healthcareetc. The main advantage of WSN lies in the ability of selfconfiguration, which can be monitored remotely. Unlimitedpotential of WSN resulted in different protocols depending onthe application [1]. One of the fast evolving WSN applicationsis in healthcare sector. Wireless Body Area Network (WBAN)is a special purpose WSN that operates autonomously formedical monitoring, which may be planted inside the bodyas well as outside.
By using a WBAN system, hospital can monitor bloodpressure, blood glucose, ECG, body temperature etc. of apatient without affecting its normal life. A typical WBANsystem consists of microprocessor, data storage, sensors, ADC,transceiver and an energy source [2]. The main requirementof sensor network is to operate at low power. ADC is oneof the main power hungry blocks in the receiver architecture.Considering spectral efficiency and low power, the best can-didate for low power architecture is quadrature band-pass Σ∆
modulator [3].The generalized quadrature receiver architecture is shown
in Fig. 1. Unlike a real band-pass Σ∆ modulators, the zerosof quadrature noise transfer function (NTF) do not need tobe complex conjugate. Zeros can be distributed around theintermediate frequency (IF) from DC to fS /2, being fS thesampling frequency. Thus, it provides twice the noise shapingwith respect to real band-pass Σ∆ modulators [3]. However,quadrature architectures are vulnerable to path mismatches
Qu
ad
ratu
re filte
r
RF amplifier
and filter
90
Quadrature
sigma
delta
modulator
De
cim
atio
n a
nd
DS
P
R
Q
Fig. 1. Generalized quadrature receiver architecture.
between I and Q paths. As a result, quantization noise inthe image band is folded into signal band thus degrading theperformance. A possible solution would be to place one of thezeros of quadrature NTF at image location [3], [4] or selectingsignal band near to DC such that quantization noise at imagelocation is still shaped [5] .
This paper extends the study reported in [6] and presentsan architectural solution and its implementation for third orderquadrature Σ∆ modulator. The circuit operates at IF = 5 fN/6,which is near to fN = fS /2, which relaxes image require-ments. This work presents a new delay line based two pathtime interleaved modulator and its switched capacitors imple-mentation. The circuit has been simulated at the behaviourallevel with non ideal blocks and achieves more than 70 dBSNR for 100 kHz bandwidth and more than 55 dB SNR for2.5 MHz bandwidth with clock frequency of 20 MHz.
The following Section reviews the basic scheme for adelay based second order quadrature modulator. It also verifiessignal-to-noise ratio (SNR) as a function of bandwidth forWBAN systems requirements. Synthesis of third order NTFwith realization techniques and robustness against mismatchesanalysis are discussed in Section III. Section IV presents anovel third order two-path modulator scheme while Section Villustrates an efficient switched capacitor implementation. Fi-nally, Section VI draws some conclusions.
II. Basic Second Order Architecture and Limitations
Consider one of the possible NTFs [6] with zeros on theunity circle at the positions e jφi , i = 1, n. The NTF is
NT F =
n∏
1
[1 − e jφi
z
]= 1 +
a1
z+ · · · + e j
∑ni φi
zn (1)
Proceedings of the 2011 IEEJ Int. Analog VLSI Workshop, Bali, Indonesia, November 2-4, 2011
65
z-1-+-+
[k((εr)+(εq))]
z-1++XR YR
z-1-
+ -+
[k((εr)-(εq))]
z-1++XQ YQ
(εr)
(εq)
Fig. 2. Second order quadrature band-pass Σ∆ architecture forNTF = 1 + z−1k(1 − j) − jz−2 with IF = 3 fN/4.
0 0.02 0.04 0.06 0.08 0.1 0.12 0.1460
62
64
66
68
70
72
74
76
78SNR vs Bandwidth of the 2nd order Sigma−Delta Modulator
Normalized Frequency(bw/fs)
SNR
[dB]
5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10
x 106
−150
−100
−50
0PSD of the 2nd order Sigma−Delta Modulator
Normalized Frequency
PSD
[dB
]
Fig. 3. Simulated SNR as a function of the signal bandwidth. The insetshows the detail of the signal band.
With zeros on the unity circle, the last term has modulus oneand phase that is the addition of the phase of all the zeros.The method developed [6] and in this paper limits the zeropositioning to situations for which
∑ni φi = 0, π/2, π, 3π/2 or
correspondingly the last coefficient of (1) is 1, j,−1 or − j. Thereason for this choice is that the first and the last term can beimplemented with minimal number of hardware. For n = 2, itis possible to implement following NTF as proposed in [6].
NT F = 1 + z−1k(1 − j) − jz−2 (2)
In this work the specification of SNR for 100 kHz band-width is more than 65 dB and more than 50 dB for 2.5 MHzbandwidth. However, the resulting k = 1.375 with samplingfrequency of 20 MHz just satisfies medium specificationrequest. Fig. 2 shows the block diagram that implements theabove NTF. SNR as a function of the bandwidth is given inFig. 3. The inset shows the zoomed region of the signal band.Moreover, the accuracy of the components used to realizethe coefficient k critically affects the SNR. Possible mismatchcauses a shift in the zeros but they will remain in the unitcircle with center frequency still locked to sampling frequency.Nevertheless, a shift of zeros augments the noise level in thesignal band and makes this solution not affordable for theconsidered specifications.
III. Third Order Quadrature Band-Pass Σ∆ ModulatorIt is more effective to have an extra zero at the center of the
signal band or near to the IF in order to satisfy higher SNR
z-1 z-1- ++ +
[k2(εr)-k1(εq)]
-+
[k1(εr)-k2(εq)]
z-1++XR YR
z-1 z-1+ ++ +
[k1(εr)+k2(εq)]
-+
[k2(εr)+k2(εq)]
z-1+-XQ YQ
(εr)
(εq)
XR1
XQ1
YR1
YQ1
Fig. 4. Third order quadrature band-pass Σ∆ architecture (IF = 5 fN/6) forNTF = 1 − z−1(k1 + jk2) + z−2(k2 + jk1) − jz−3.
−1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1−140
−120
−100
−80
−60
−40
−20
0PSD of the 3rd order Sigma−Delta Modulator
Normalized Frequency
PS
D [d
B]
Fig. 5. PSD of the 5 fN/6-IF third order quadrature band-pass modulator fork1 = 0 and k2 = 0 using the architecture of Fig. 4.
for lower bandwidth requirement. Consider the architectureshown in Fig. 4. It is the building scheme of the final design.Supposing to use coefficients k1 = 0 and k2 = 0, i.e withoutinjection of quantization error between delays, it realizes
NTF = 1 − ( j)z−3 (3)
Note that in the signal band of interest around IF = 5 fN/6there is only one zero and other two zeros located at fN/6 and− fN/2 are not useful in enhancing the SNR. The simulatedoutput spectrum is given in Fig. 5. In order to shift two ofthe zeros towards the signal band, we inject k1 = −2.5981 andk2 = 1.5 on the intermediate points of Fig. 4. This moves zerosat IF = 5 fN/6. The NTF is
NTF = 1 − z−1(k1 + ( j)k2) + z−2(k2 + ( j)k1) − ( j)z−3 (4)
−1 −0.5 0 0.5 1
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
Real Part
Imag
inar
y P
art
Fig. 6. Location of the complex zeros for k1 = −2.5 and k2 = 1.444.
Proceedings of the 2011 IEEJ Int. Analog VLSI Workshop, Bali, Indonesia, November 2-4, 2011
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−1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1−150
−100
−50
0PSD of the 3rd order Sigma−Delta Modulator
Normalized Frequency
PS
D [d
B]
Fig. 7. PSD of the 5 fN/6-IF third order quadrature band-pass modulator fork1 = −2.5 and k2 = 1.444 using the architecture of Fig. 4.
0 0.02 0.04 0.06 0.08 0.1 0.12 0.1465
70
75
80
85
90
95
100
105SNR vs Bandwidth of 3rd order Sigma−Delta Modulator
Normalized Frequency(bw/fs)
SNR
[dB]
6 6.5 7 7.5 8 8.5 9 9.5 10
x 106
−150
−100
−50
0PSD of the 3rd order Sigma−Delta Modulator
Normalized Frequency
PSD
[dB
]
Fig. 8. SNR versus Bandwidth plot of a third order quadrature band-passΣ∆ architecture. Inset shows zoomed region of signal band.
Distributing the zeros around desired IF. Fig. 6 shows thezeros placement for k1 = −2.5 and k2 = 1.444. The simulatedspectrum is given in Fig. 7 while Fig. 8 shows SNR as afunction of bandwidth. The performance mainly depends onthe notch at IF = 5 fN/6 (inset diagram shows the zoomedregion of the signal band).
The SNR obviously depends on the accuracy of the injectionparameters k1 and k2. Fig. 9 shows the histogram plot (300samples) for the mismatch variation in coefficients k1 and k2with standard deviation SD = 5 ∗ 10−3. Notice that more than90% of the samples results in a SNR higher than 60 dB fora bandwidth of 2.5 MHz. It is also worth to analyze the sen-sitivity of the modulator with respect to coefficients variation.The 3D plot shown in Fig. 10 confirms the robustness of thearchitecture.
IV. Delay Line Based Two Path Third OrderModulator
For the circuit implementation, this paper uses a two-pathscheme. The solution costs an increased hardware but savessignificant power (nearly 50%) [7]. There are architecturesavailable in the literature, which use multi-path scheme forlow-pass [7] or band-pass modulator [8], [9], but all realiza-tions are integrator based solution.
The block diagram of Fig. 11 shows the two-path quadraturemodulator. Each modulator operates at half the samplingfrequency ( fS /2). Let us now consider again the architectureshown in Fig. 4. It uses three delay based cross coupled
54 56 58 60 62 64 66 680
10
20
30
40
50
60
70
80
SNR[dB]
Sam
ples
Fig. 9. Histogram plot for mismatch analysis with 5% variance.
1.431.44
1.451.46
1.47 −2.515−2.51
−2.505−2.5
−2.495−2.49
−2.485
54
56
58
60
62
64
66
68
56
58
60
62
64
66
k1k2
SN
R [d
B]
Fig. 10. 3D mismatch analysis plot showing SNR versus variation incoefficients k1 and k2.
quadrature filters. We duplicate the core of the scheme of Fig.4 for both even and odd paths to obtain circuits dedicated to thegeneration of YQ1e, YR1e, YQ1o, and YR1o (shown for YQ1e andYR1e in Fig. 12). Quadrature input signals XR1 and XQ1 result infiltered quadrature outputs YR1 and YQ1. Notice that XR1e goesthrough six delays to reach the output YQ1e. Similarly, inputXQ1e propagates through six delays to reach the output YR1e.A suitable transformation gives rise to schemes with doubledelays only. Fig. 13 shows the final even path scheme of thefilter after rearranging the blocks. Odd path has similar blockrearrangement. All the injection of the quantization error arerearranged such that they will foresee at least one single delay,necessary for the quantization. The obtained scheme requires12 delay blocks that run at fS /2. The circuit of Fig. 4 uses 6delays running at fS . Since reducing by 2 the clock frequencydiminishes the power of active elements by 4, the two-patharchitecture reduces by 2 the expected consumed power.
ΣΔ
ΣΔ
XRXQ
YRYQ
fs/2
XRe
XQe
XRo
XQo
YRe
YQe
YRo
YQo
Fig. 11. Generalized two path quadrature band-pass modulator. Σ∆ is thescheme of Fig. 4.
Proceedings of the 2011 IEEJ Int. Analog VLSI Workshop, Bali, Indonesia, November 2-4, 2011
67
z-1 z-1- ++ +
[k2(εr)-k1(εq)]
-+
[k1(εr)-k2(εq)]
z-1
z-1 z-1+ ++ +
[k1(εr)+k2(εq)]
-+
[k2(εr)+k2(εq)]
z-1
XR1e
XQ1e YQ1e
z-1 z-1- ++ +
[k2(εr)-k1(εq)]
-+
[k1(εr)-k2(εq)]
z-1
z-1 z-1+ ++ +
[k1(εr)+k2(εq)]
-+
[k2(εr)+k2(εq)]
z-1
XR1e
XQ1e
YR1e
Fig. 12. Doubling the core of the scheme of Fig. 4.
z-2- ++ +
[k2(εr)-k1(εq)]
-+
[k1(εr)-k2(εq)]
z-2 ++
[k1(εr)+k2(εq)]
-+
[k2(εr)+k2(εq)]
XR1e
XQ1eYQ1e
z-2 z-2++
[k2(εr)-k1(εq)]
-+
[k1(εr)-k2(εq)]
z-2 ++
[k1(εr)+k2(εq)]
-+
[k2(εr)+k2(εq)]
XR1e
XQ1e
YR1e
z-1
z-1
++ z-2
z-1
z-1
z-1
-+
z-1
Fig. 13. Double delay based architecture after block reduction.
The possible mismatch between the even and odd paths isnot problematic because it generates tones at fS /4. Mismatchesbetween I and Q paths give rise to tones at the image positionas it happens for any quadrature solutions. Simulation resultswith mismatches lead to the spectrum of Fig. 14. The proposedmethod possibly allows us to add an extra zero at the imageposition to improve the image rejection.
V. Switched Capacitor Implementation
The architecture implementation uses switched capacitor.Flip-around method is chosen over the conventional method-ology to reduce the slew rate problem as it requires onlyone capacitor for realization. Capacitor is already chargedduring the sampling phase, hence op-amp performance canbe relaxed. Because of the band-pass operation, the scheme isinsensitive to offset of the op-amps. Fig. 15 with its clockingscheme realizes a single delay. During phase φ1, input voltageVin is sampled onto capacitor C and during the other phase,
−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−150
−100
−50
0PSD of 3rd order Sigma−Delta Modulator with path mismatch
Normalized Frequency
PSD
[dB]
Fig. 14. Simulated output spectrum of the two-path scheme with nominalmismatches.
C
+
_
Vcm Vcm
VinVout
Φ1
Φ2
Φ1
Φ1
Φ2
Φ2
Fig. 15. Flip-around technique for single delay realization.
φ2, capacitor is connected between output of the operationalamplifier (op-amp) Vout and input negative terminal of the op-amp.
The scheme of Fig. 15 operates during phase φ2 only.The complementary phase could be possibly used for offsetcancellation. Since offset is not an issue, we use the solutionreported in each stage of Fig. 16 to further relax the op-ampspecifications. During clock period 1, capacitor C′ is in thesampling mode, C′′ is in the wait mode, and C′′′ is in the flip-around mode. During clock period 2, C′ goes in the wait mode,C′′ flips around and C′′′ samples the new input. Similarlyfor the clock period 3. The solution is such that a capacitorremains in feedback around the op-amp for an entire clockperiod.
The proposed solution has been simulated at the behaviourallevel in Cadence environment and results totally confirm whatachieved in Matlab-SimulinkTM. Both simulations include mis-matches and op-amps non idealities (finite gain, bandwidth andslew-rate).
VI. Conclusion
This work extensively studied a quadrature band-pass Σ∆
modulator based on a new design concept. The IF, locked tothe sampling frequency, can be located in a limited numberof fractional values of fS . The feature grants the benefit of anIF programmability just by changing fS . The architecture isrobust against mismatches that just move NTF zeros whose
Proceedings of the 2011 IEEJ Int. Analog VLSI Workshop, Bali, Indonesia, November 2-4, 2011
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CI
+
_
Vcm
Vcm
VRin
S1
S1
I1
I1
Vcm
S2
S2
I2
I2
Vcm
S3
S3
I3
I3
S1& I2
S2& I3
S3& I1
Φ1
Φ2
+
_
Vcm
Vcm
S1
S1
I1
I1
Vcm
S2
S2
I2
I2
Vcm
S3
S3
I3
I3
+
_
Vcm
Vcm
VRout
S1
S1
I1
I1
Vcm
S2
S2
I2
I2
Vcm
S3
S3
I3
I3
2T 2T 2T
T
CII
CIII CIII
CII
CI CI
CII
CIII
Fig. 16. Six delays implementation based on flip-around cell and driving phases.
position, within limits, remains on the unity circle. The zeroat IF is mismatch insensitive. Architectural details and circuitsolutions are provided. The effectiveness of the proposedscheme was proved by simulations at the behavioural level.
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[3] S. A. Jantzi, K. W. Martin, and A. S. Sedra, ”Quadrature bandpass Σ∆modulation for digital radio”, IEEE Journal of Solid-State Circuits, vol.32, no. 12, pp. 1935 - 1950, Dec. 1997.
[4] R. Schreier, N. Abaskharoun, H. Shibata, D. Paterson, S. Rose, I. Mehr,Luu, ”A 375-mW Quadrature Bandpass Σ∆ ADC With 8.5-MHz BW and90-dB DR at 44 MHz”, IEEE Journal of Solid-State Circuits, vol. 41, no.12, pp. 2632 - 2640, Nov. 2006.
[5] Lucien J. Breems, Robert Rutten, Robert H. M. van Veldhoven and Gerardvan der Weide,”A 56 mW Continuous-Time Quadrature Cascaded Σ∆Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band”, IEEEJournal of Solid-State Circuits, vol. 42, no. 12, pp. 2696-2705, Dec. 2007.
[6] Nithin Kumar Y.B., Selcuk Talay, and Franco Maloberti, ”On the Designof Band-Pass Quadrature Σ∆ Modulators”, Proc. of IEEE Asia PacificConf. on Circuits and Systems, pp. 1228-1231, Dec. 2008.
[7] Erkan Bilhan and Franco Maloberti, “A Wideband Sigma-Delta Modula-tor With Cross-Coupled Two-Paths” IEEE Transactions on Circuits andSystems-I, vol. 56, no. 5, pp. 886893, May 2009.
[8] Feng Ying and Franco Maloberti, ”A Mirror Image Free Two-Path Band-pass Σ∆ Modulator with 72dB SNR and 86dB SFDR”, IEEE InternationalSolid-State Circuits Conference Dig. Tech. Pap., pp. 84-85, Feb. 2004.
[9] Ivano Galdi, Edoardo Bonizzoni, Piero Malcovati, Gabriele Manganaro,and Franco Maloberti, ”40 MHz IF 1 MHz Bandwidth Two-Path Band-pass Σ∆ Modulator with 72 dB DR Consuming 16 mW”, IEEE Journalof Solid-State Circuits, no. 7, vol. 43, pp. 1648-1656, July 2008.
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