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MOS Transistor Theor

VLSI DesignVLSI Design

By Dr. Yaseer A. DurraniDept. of Electronics Engineering

University of Engineering & Technology, Taxila

Outline Semiconductor IC Chip pn-Junction Transistor I-V Characteristics RC Delay Model Transistor Families

2

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Silicon Chip A pattern of interconnected switches & gates on surface of crystal of

semiconductor (typically Si) Silicon is a Group IV semiconducting material

Crystal lattice: covalent bonds hold each atom to four neighbours These switches & gates are made of:

Areas of n-type silicon Areas of p-type silicon Areas of insulator Lines of conductor (interconnects) joining areas together

, , , , , Geometry of these areas is known as layout of the chip Connections from chip to outside world are made around the edge of the chip to

facilitate connections to other devices

3

Semiconductor is a solid material that has electrical conductivity in betweenconductor & insulator Similar to insulators Less Larger energy band gaps

Doping is the process of intentionally introducing impurities into extremelypure/intrinsic semiconductor in order to change its electrical properties Number of dopant atoms needed to create a difference in ability of a

semiconductor to conduct is very small Small number of dopant atoms are added (order of 1 every 100,000,000

Semiconductor

, More dopant atoms are added (order of 1 in 10,000) then doping is said to

be heavy, or high. This is often shown as n+ for n-type dopant or p+ for p-type doping

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p-n Junction A p-n junction is a boundary or interface b/w two types of semiconductor

material, p-type & n-type, inside a single crystal of semiconductor

pn junctions are elementary "building blocks" of most semiconductorelectronic devices such as diodes, transistors, solar cells, LEDs, ICs Common type of transistor, bipolar junction transistor, consists of two pn

junctions in series, in the form npn or pnp Its main electrical property is that it rectifies (allow current to flow easily in one

direction only)

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p-type n-type

anode cathode

Type of junctions Homojunction: is a semiconductor interface that occurs b/w layers of similar

semiconductor material, these materials have equal band gaps but typicallyhave different doping

Heterojunction: is interface that occurs b/w two layers or regions of dissimilarcrystalline semiconductors. These semiconducting materials have unequal bandgaps as opposed to a homojunction

8

Image of nanoscale heterojunctionb/w iron oxide & cadmium sulfide

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Holes diffused to metalurgical junction & combine with electrons. They leavebehind -vely charged acceptor, while electrons diffused & leave behind +velycharged donor

Diffusion process can not go on forever, because, increasing amount of fixedcharge wants to electrostatically attract the carriers that are trying to diffuseaway & equlibrium is reached

Fixed charge produce an electric field which slows down the diffusion process Fixed charge region is called depletion/space charge region

Idealized p-n Junction

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Contact Potential When p & n-type materials are joined, electrons & holes diffuse due to their

large carrier concentration gradients at junction where holes diffuse from p-side into n-side, & electron diffuse from n to p. Thus, concentration gradientscreates a diffusion component of current from p to n region

+++-

-- -+

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++

- -- - -

++++

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Transistors as ideal switches An ON transistor passes a finite amount of current

Depends on terminal voltages Derive current-voltage (I-V) relationships

Transistor gate, source, drain all have capacitance I = C (V/t) ->t = (C/I)V Capacitance and current determine speed

13

NMOS Capacitor Gate & body form MOS capacitor Operating modes

Accumulation Depletion Inversion

polysilicon gate

(a)

silicon dioxide insulator

p-type body+-

Vg< 0

+-

0 < Vg< V

t

depletion region

(b)

(c)

+-

Vg> Vt

depletion region

inversion region

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Terminal Voltages Mode of operation depends on Vg, Vd, Vs

Vgs = Vg Vs Vgd = Vg Vd

Vds = Vd Vs = Vgs - Vgd Source & drain are symmetric diffusion terminals

However, Vds 0 Three- regions of operation

Cutoff, Linear, & Saturation

Vg

V s V d

Vgd

Vgs

Vds

+-

+

-

+

-

NMOS Saturation RegionChannel pinches off if Vds > Vgs Vt.I inde endent of V i.e. current saturates

+-

Vgs

> Vt

n+ n+

+-

Vgd

< Vt

Vds> V

gs-V

t

p-type body

b

g

s d Ids

+-

Vgs

= 0

n+ n+

+-

Vgd

p-type bodyb

g

s d

NMOS Cutoff RegionAssume Vs = VbNo channel, if Vgs = 0Ids = 0

+-

Vgs

> Vt

n+ n+

+-

Vgd

= Vgs

+-

Vgs

> Vt

n+ n+

+-

Vgs

> Vgd

> Vt

Vds

= 0

0 < Vds

< Vgs

-Vt

p-type body

p-type bodyb

g

s d

b

g

s dIds

NMOS Linear RegionChannel forms if Vgs > Vt

No Currernt if Vds = 0

Linear Region:If Vds > 0, Current flowsfrom d to s ( e- from s to d)Ids increases linearlywith Vds if Vds > Vgs Vt.Similar to linear resistor

Similar to current source

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I-V Characteristics In Linear region, Ids depends on

How much charge is in the channel How fast is the charge moving

Channel Charge: MOS structure looks like parallel plate capacitor whileoperating in inversion Gate oxide (dielectric) channel

Qchannel = CV C = C

g

= ox

WL/tox

= Cox

WL V = Vgc Vt = (Vgs Vds/2) Vt Cox = ox/ tox

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2gate oxide(good insulator, ox= 3.9)

polysilicongate

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Carrier Velocity Carrier Velocity

Charge is carried by e- Carrier velocity vproportional to lateral E-field b/w source & drain

v= E, is mobility, E = Vds/L Time for carrier to cross channel: t=L/v NMOS Linear I-V

How much charge Qchannel is in the channel How much time teach carrier takes to cross

NMOS Saturation I-V If V < V channel inches off near drain

channel

ox 2

2

ds

dsgs t ds

dsgs t ds

QI

t

W VC V V V

L

VV V V

=

=

=

ox=

WC

L

When Vds > Vdsat = Vgs Vt

Now drain voltage no longer increases current

NMOS IV Summary

Shockley1st

order transistor models (valid for Large channel devices only

( )2

2

2

dsatds gs t dsat

gs t

VI V V V

V V

=

=

( )2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V V

VI V V V V V

V V V V

<

= 17

Example For a 0.6m process

From AMI Semiconductor tox = 1 0 0 = 350 cm2/V*s Vt = 0 . 7 V

Plot Ids vs. Vds Vgs = 0 , 1 , 2 , 3 , 4 , 5 Use W/L = 4/2

1423.9 8.85 10W W W

0 1 2 3 4 50

0.5

1

1.5

2

2.5

Ids

(mA)

Vgs

= 5

Vgs

= 4

Vgs

= 3

Vgs

= 2

Vgs

= 1

8100 10

oxL L L

= = =

ds

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PMOS I-V All dopings & voltages are inverted for PMOS Mobility p is determined by holes

Typically 2-3x lower than that of electrons n

120 cm2/V*s in AMI 0.6 m process Thus PMOS must be wider to provide same current

In this class, assume n/ p = 2

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Gate Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important

Creates channel charge necessary for operation Source & drain have capacitance to body

Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain

diffusion Approximate channel as connected to source Cgs = oxWL/tox = CoxWL = CpermicronW

polysilicongate

Cpermicron is typically about 2 fF/m

n+ n+

p-type body

W

L

tox

SiO2gate oxide

(good insulator, ox= 3.90)

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Dynamic Behavior of the Transistor Propagation Delay, Tp: defines how quickly output is affected by input

Measured between 50% transition from input to output tpLH defines delay for output going from low to high

tpHL defines delay for output going from high to low Overall delay, tp, defined as the averageof tpLH and tpHL Rise and fall time, Tr & Tf: Defines slope of the signal

Defined b/w 10% and 90% of the signal swing Propagation delay and rise and fall times affected by the fan-out due to

larger capacitance loads

Standard method to measure gate delay is based on ring oscillator: 2Ntp >> tf + tr for proper operation

tpH L

tpL H

t

t

Vin

Vou t

50 %

50 %

tr

10 %

90 %

tf

tpH L

tpL H

t

t

Vin

Vou t

50 %

50 %

tr

10 %

90 %

tf

v 0 v 1 v 2 v 3 v 4 v 5

v0 v 1 v5

T = 2 tp N

Ring Oscillator21

Switch Model of Dynamic Behavior

VDD

Rp

Vout

CL

VDD

R

VoutCL

Gate response time is determined by the time to charge CL through Rp(discharge CL through Rn)

VDD

Vout

CLIav

tpH L = C LVswing /2

Iav

CL

kn VDD~

Technique-1

Vin = 0 Vin = V DD

in= DD

VDD

Vout

Vin= V DD

Ron

CL

tpHL = f(Ron.CL)

= 0.69 RonCL

t

Vou t

VDD

RonCL

1

0.5

ln(0.5)

0.36

)/( LonCRt

OHout eVV

=

Technique-2 22

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How can the designer build a fast gate? tpHL = f(Ron*CL) Keep output capacitance, CL, small

low fan-out

Keep interconnections short (floor-plan your layout!) Decrease on-resistance of transiston Increase W/L ratio Make good contacts (slight effect)

3

23

0 0 .5 1 1 .5 2 2 .5

x 1 0-1 0

-0.5

0

0 .5

1

1 .5

2

2 .5

t ( sec)

Vout(

V) tp = 0.69 CL (Reqn+Reqp)/2tpHL tpLH

Transient Response

Inverter Transient Response

Vin

tf trtpHL tpLH

VDD=2.5V0.25mW/Ln = 1.5W/Lp = 4.5Reqn= 13 k ( 1.5)Reqp= 31 k ( 4.5)

tpHL = 36 psec

tpLH = 29 psec

so

tp = 32.5 psec

t (sec) x 10-10

From simulation: tpHL = 39.9 psec & tpLH = 31.7 psec

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Propagation Delay Analysis - Switch Model

V

Propagation delay depends on input patterns Example: Two input NAND gate

Two PMOS transistors are ON

Delay: 0.69x(Rp/2)xCL Only one PMOS transistor ON then Delay: 0.69xRpxCL

Large number of transistors (2N) increases overall capacitance of gate Series connection of transistors in PUN/PDN of gate causes additional slow down

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VDD

CL

FCL

CL

F

F

Rp

Rp Rp Rp

Rp

Rn

Rn

Rn Rn Rn

AA A

A

A

A

B B

B

B

Inverter 2 input NAND 2-input NOR

t p = 0.69 Ron C L

(assuming that C Ldominates!)

= RON

Analysis of Propagation DelayVDD

CL

F

Rp Rp

Rn

Rn

A

A B

B

1. Assume Rn=Rp= resistance of minimumsized NMOS inverter

2. Determine Worst Case Input transition(Delay depends on input values)

3. Example: tpLH for 2input NAND- Worst case when only ONE PMOS Pulls

up the output node

- For 2 PMOS devices in parallel, theresistance is lower

VDD

CL

F

A B

B

2

1 1

VDD

A

B

C

D

A 2

2

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4

F

26

2-input NAND

4. Example: tpHL for 2input NAND- Worst case : TWO NMOS in series

tpLH = 0.69RpCL

tpHL = 0.69(2Rn)CL

AD

B C

122

Here it is assumed that Rp=Rn

Design for worse case

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Elmore Delay

R1

C1

R2

C2

Ri-1

Ci-1

Ri

Ci

RN

CN

Vin

N

1 2 i-1i

Elmore delay is equivalent to first-order time constant of n/w Time constant represents simple approx. of actual delay b/w source

node and node i

27Delay Optimization

Approx RC model of digital cir circuits

= = =

==

N

i

i

j

N

i

iiijiDN RCRC1 1 1

RC Delay Model Use equivalent circuits for MOS transistors

Ideal switch + capacitance and ON resistance NMOS has resistance R, capacitance C PMOS has resistance 2R, capacitance C

Capacitance proportional to width Resistance inversely proportional to width

kg

d

g

d

kCR/k

d

s

kC

kC

2R/k

s

s

kCkC s

d

kC

k1 Capacitance

C = Cg = Cs = Cd = 2 fF/m of gate width Values similar across many processes

Resistance R 6 K*m in 0.6um process Improves with shorter channel lengths

Unit transistors

May refer to minimum contacted device (4/2 ) Or maybe 1 m wide device Doesnt matter as long as you are consistent 28

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Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter

C

2C

2C

R

2

1A

Y

C

2C

C

2C

C

2C

RY

2

1

Cd = 6RC

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Transistor Families CMOS: Displace bipolar technology in digital applications are as follows:

CMOS logic circuits dissipate much less power than bipolar logic circuits High input impedance of MOS transistor allows designer to use charge

storage for temporary storage of information in both logic & memory circuits Feature size (i.e., minimum channel length) of MOS transistor has

decreased which permits very tight circuit packing & integration Bipolar: Two logic-circuit families based on bipolar junction transistor are in

some use at present: TTL & ECL

BiCMOS: Combines the high operating speeds possible with BJTs with lowpower dissipation & other excellent characteristics of CMOS Gallium Arsenide (GaAs): High carrier mobility results in very high speeds

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Transistor Families Resistortransistor logic (RTL)

Direct-coupled transistor logic (DCTL) Resistortransistor logic (RCTL)

Diodetransistor logic (DTL) Complemented transistor diode logic (CTDL) High-threshold logic (HTL)

Emitter-coupled logic (ECL) Positive emitter-coupled logic (PECL) Low-voltage positive emitter-coupled logic(LVPECL)

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Transistortransistor logic (TTL) P-type metaloxidesemiconductor logic (PMOS) N-type metaloxidesemiconductor logic (NMOS)

Depletion-load NMOS logic

Complementary metaloxidesemiconductor logic (CMOS) Bipolar complementary metaloxidesemiconductor logic (BiCMOS) Integrated injection logic (I2L)

Transistor Families

Family DescriptionPropagation

delay (ns)

Togglespeed(MHz)

Power/gate@1MHz (mW)

Typical supplyvoltage V (range) Year Remarks

RTL Resistortransistor logic

__ 4 10 3.3 1963 First CPU built f rom used RTL.

DTL Diodetransistor logic

__ __ 10 5 1962 Introduced by Signetics, Fairchild 930line became industry standard in 1964

CMOS AC/ACT 3 125 0.5 3.3 or 5 (2-6 or 4.5-5.5)

1985 ACT has TTL Compatible levels

CMOS HC/HCT 9 30 0.5 5 (2-6 or 4.5-5.5) 1982 HCT has TTL compatible levels

CMOS 4000B/74C 30 5 1.2 10V (3-18) 1970 Approximately half speed & power at 5V

TTL Original series 10 25 10 5)4.75-5.25( 1964 Several manufacturers

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TTL L 33 3 1 5)4.75-5.25( 1964 Low power

TTL H 6 43 22 5)4.75-5.25( 1964 High speed

TTL S 3 110 19 5)4.75-5.25( 1969 Schottky high speed

TTL LS 10 33 2 5)4.75-5.25( 1976 Low power Schottky high speed

TTL ALS 4 34 1.3 5)4.5-5.5( 1976 Advanced Low power Schottky

TTL F 3.5 100 5.4 5)4.75-5.25( 1979 Fast

TTL AS 2 105 8 5)4.5-5.5( 1980 Advanced Schottky

TTL G 1.5 1125(1.125GHz)

1.65-3.6 2004 First GHz 7400 series logic

ECL ECL III 1 500 60 -5.2)-5.19--5.21( 1968 Improved ECL

ECL MECL I 8 31 -5.2 1962 first IC commercially produced

ECL ECL 10K 2 125 25 -5.2)-5.19--5.21( 1971 Motorola

ECL ECL 100K .75 350 40 -4.5)-4.2--5.2( 1981ECL ECL 100KH 1 250 25 -5.2)-4.9--5.5( 1981

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Field Effect Transistors (FET) Field effect devices are voltage controlled by action of electric field, rather than

carrier injection FETs have weak electrical signal coming in through one electrode creates an

electrical field through the rest of transistor

FET transistor uses an electric field to control the shape & conductivity of achannel of one type of charge carrier in a semiconductor material

FETs are unipolar, as they involve single-carrier-type operation FET behaves like bipolar transistor with important difference that gate has a very

33

FET Types N Channel (as NPN transistor) P Channel (as PNP transistor) N & P channel each come as:

Enhancement mode (just IGFET) Depletion mode (IGFET or JFET)

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Basic Operation of JFET JFET operation can be compared to a water spigot: Source of water pressure: Accumulated electrons at ve pole of applied voltage

from Drain to Source Drain of water: Electron deficiency (or holes) at +ve pole of applied voltage from

Drain to Source Control of flow of water: Gate voltage that controls the width of n-channel, which

in turn controls the flow of electrons in n-channel from Source to Drain

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JFET If channel is doped with donor impurity, n-type material is formed & channel

current will consist of electrons If channel is doped with acceptor impurity, p-type material will be formed &

channel current will consist of holes N-channel devices have greater conductivity than p-channel types, since

electrons have higher mobility than do holes; thus n-channel JFETs areapproximately twice as efficient conductors compared to their p-channel

counterparts Magnitude of current is controlled by voltage applied to gate, which is reverse-

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biased

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An Insulated Gate FET

Source Gate Drain

SubstrateNType

P Type

Insulator

Metal

Source Gate Drain

SubstrateNType

P Type

Insulator

Metal

Insulated Gate FETn-Channel Enhancement mode

Source Gate+ Drain

SubstrateNType

P Type

Insulator

Metal

Channel

n-Channel enhancement

JFET

Source Gate+ Drain+

SubstrateNType

P Type

Insulator

Metal

Channel

N enhance FET atPinchoff

N enhance FETbeyond Pinchoff

Source Gate+ Drain++

SubstrateNType

P Type

Insulator

Metal

Channel

n-Channel Depletion modeFET ON No gate bias

Source Gate Drain

SubstrateNType

P Type

Insulator

Metal

Channel

n-Channel Depletionmode FET off

Source Gate- Drain

SubstrateNType

P Type

Insulator

Metal

NoChannel

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MOSFET MOSFETMetalOxideSemiconductor Field-Effect Transistor is a transistor

used for amplifying or switching electronic signals Source & Drain terminals are specified by operation voltage MOSFET has four-terminals: Source (S), Gate (G), Drain (D), Body (B) Body (or substrate) of MOSFET often is connected to source terminal, making it

three-terminal MOSFET is by far the most common transistor in both digital and analog circuits,

though the bipolar junction transistor was at one time much more common

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BJTBipolar Junction Transistors is current controlled device consists of two pn-junctions

Three region: Base, Collector , Emitter

Operational modes are Base-Emitter & Base-Collector voltages When there is no base current, almost no collector current flows When base current flow, collector current can flow BJT consists of N-type material with P-type on either side, or visa-versa

PNP P-type N-type P-typeNPN N-type P-type N-type

BJTs

39

VMOS VMOS Vertical MOSFET increases the surface area of the device Advantage:

This allows the device to handle higher currents by providing it moresurface area to dissipate the heat

VMOSs also have faster switching times

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CMOS CMOS Complementary Metal Oxide Semiconductor employs both PMOS &

NMOS devices CMOS Complementary MOSFET p & n-channel MOSFET on same substrate

If substrate is p-type, PMOS transistors are formed in n-well (n-type body need) If substrate is n-type, NMOS transistors are formed in p-well (p-type body need) Substrate & well are connected to voltages which reverse bias the junctions for

device isolation Advantage:

Lower power consumption Higher input impedance Faster switching speeds

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BJT Vs. CMOS Advantages of Bipolar over CMOS

Switching speed Currents drive per unit area Noise performance Analog capability Input/output speed

Advantages of CMOS over Bipolar

Power dissipation Noise margin Packing density Ability to integrate large complex functions with high yields

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BiCMOS BiCMOS technology combines Bipolar & CMOS transistors onto a single IC

where the advantages of both can be utilized BiCMOS technologies have tended to evolve from CMOS processes in order to

obtain the highest CMOS performance possible Bipolar processing steps have been added to core CMOS flow to realize the

desired device characteristics BiCMOS gates can be an efficient way of speeding up VLSI circuits

Advantages:

Lower power dissipation than Bipolar Flexible input/outputs High performance analog Latch up immunity

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BiCMOS Structure NMOS device, built on top of P+substrate PMOS transistor, built in an N-well approximately 5um deep P+substrate is used to reduce latch up susceptibility by providing low impedance

patch through a vertical pnp device Polysilicon gates are used for both the PMOS & NMOS transistors

Simplest way to add npn bipolar transistor to CMOS structure is by using PMOSN-well as collector of Bipolar device & introducing an additional mask level for P-

base region P-base is approx 1-um deep with doping level of about 1e17 atoms/cm^3 N+source/drain ion implantation step is used for emitter & collector contact of

bipolar structure P+source/drain ion implantation step is used to create a P+ base contact to

minimize the base series resistance

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CMOS Nanoelectronics Key of success of CMOS nanoelectronics: additive technology features

Ultra-thin body FET Double- (or Multi-) gate FET

Strained Si (bulk, on insulator) Ge (bulk, on insulator) High-k gate dielectrics Metal gates Crystal orientation

45

Emerging Devices New technologies based on something other than electronic charge

thatextend the scaling of information processing technologies throughmultiple generations beyond 2019

Provide a path to scale CMOS to the end of Roadmap using new transistorstructural designs & new materials Transport-Enhanced FETs: Enhance the velocity of carriers

Ultra-thin Body SOI FETs: Thin transistor body is employed Source/Drain Engineered FETs: Engineering the source/drain Multiple Gate FETs:

N-Gate (N>2) FETs: Use more than two gates to improve electrostatic control Double-gate FETs: Use two isolated gates for low-power & mixed-signal

processing

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Emerging Devices

Resonant tunnel devices

Molecular devices

ng e-e ec ron rans s ors

Spin transistors 47