VHDL and Control Ckt Designpemclab.cn.nctu.edu.tw/W3news/開授課程-old/電力...3 1. Introduction...

1

VHDL and Circuit Design for Digital Controller

任課教師: 蔡明發博士

九十三學年度第二學期

Part 1

2

Contents

Ref1:VHDL 數位電路設計蕭如宣編著 (儒林)Ref2: Daniel D. Gajski, Principles of Digital Design, Prentice Hall, 1997 (全華)

1. Introduction to VHDL2. Adder / Subtractor3. Shifter4. PWM-Signal Generator5. PI Controller Circuit Design

3

1. Introduction to VHDL

• A hardware description language (HDL) allows a digital system to be designed and debugged at a higher level before conversion to thegate and flip-flop level.

• The two most popular HDLs are VHDL and Verilog.• VHDL is a HDL to describe the behavior and structure of digital

system.• VHDL: VHSIC Hardware Description Language• VHSIC: Very High Speed Integrated Circuits• VHDL was originally developed for the military to allow a uniform

method for specifying digital systems. • The VHDL has become an IEEE standard, and it is widely used in

industry.

4

VHDL語言的發展

年第一季

1983

1984

1985

1986

1987

1992

1993

美國國防部提出要求

和TI, IBM及Intermetrics公司簽約

第二季第三季第四季

開始工作

V2.0 V5.0 V6.0

VHDL分析和標準化小組第一次會議

V7.2 IEEE開始標準化工作

語言參考手冊第一次原稿

語言參考手冊第二次原稿 1076/A

評審 1076/A 語言參考手冊1076/B IEEE std 1076-1987通過

再次投票通過

再次投票通過 IEEE std 1076-1993通過

5

VHDL程式的組成架構

1. 單體 (Entity): 電路外觀描述

2. 架構 (Architecture): 電路內部功能描述

3. 配置 (Configuration)

4. 套件 (Package)

5. 元件庫 (Library)

一個基本的設計單元都由兩部分構成:

單體宣告(Entity Declaration)和架構 (Architecture)

6

VHDL 的電路單體(Entity)

A

BYNAND2

ENTITY NAND2 isPORT(A,B: IN bit;

Y : OUT bit );END NAND2;

ENTITY用來宣告電路的外部包裝，也就是設計體的介面ENTITY的描述以「Entity...IS...Port…End」來表示

VHDL的基本架構-1

7

• 以「Architecture..of..IS...Begin..End」來表示• 用以描述 ENTITY 所涵蓋的電路行為特性和動作

VHDL的電路架構( Architecture)

architecture Dataflow of NAND2 isbegin

C

9

資料型態與運算子-2

• 資料型別– 邏輯訊號

在邏輯訊號中，我們用 std_logic 和 bit 來宣告邏輯位元，另外用std_logic_vector 和 bit_vector 來宣告多位元的邏輯訊號。在VHDL中，標準邏輯（STD_LOGIC）訊號型式定義是：

type std_logic is ( ‘X’ -- Forcing unknown‘0’ -- Forcing zero‘1’ -- Forcing one‘Z’ -- High impedance‘W’ -- Weak unknown‘L’ -- Weak zero‘H’ -- Weak one‘-’ ); -- Don’t care

10


在VHDL語法中，一群BIT即可以構成Bit_Vector，而一群Std_Logic也可組成Std_Logic_Vector序列。

S1 S0

Y1

Y0

Y2

Y3

SIGNAL S: std_logic_vector(1 downto 0);SIGNAL Y: std_logic_vector(3 downto 0);

SIGNAL S: std_logic_vector(1 downto 0);SIGNAL Y: std_logic_vector(3 downto 0);

SIGNAL S1,S0: std_logic;SIGNAL Y3,Y2,Y1,Y0: std_logic;

SIGNAL S1,S0: std_logic;SIGNAL Y3,Y2,Y1,Y0: std_logic;

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– 數值訊號» 整數:VHDL語言中的整數數值範圍從到，它是以32位元的

bit_vector來定義整數的範圍的。例如:

Signal A：Integer; --32位元數值宣告Signal B,C：Integer range 0 to 7; -- 3位元數值宣告Variable INT_S:Integer; --32位元數值宣告

» 無號整數(UNSIGNED)序列宣告:宣告成整數的訊號是一種數值型式，跟宣告成位元(bit、bit_vector)型式的邏輯訊號事實上是不能夠直接作資料互換的；在VHDL語言中

另外提供了Unsigned指令宣告，它同時具有邏輯和數值的特性，因此既可作邏輯處理又可作數值運算。

例如:Signal A：Std_logic;Signal B,C：Unsigned(3 downto 0);

12


• 運算子

– 邏輯運算子

– 關係運算子

– 算術運算子

Y

13

架構描述的三種基本模式 (VHDL Design Modeling)

• Data-Flow (資料流模式)concurrent signal assignment (select, conditional )

• Behavior (行為模式)Sequential signal assignment (like high level

language)

• Structure (結構模式)description of COMPONENT and WIRE

* Mix of above three

14

A Two-Input OR Gate Using Data-Flow Description

Library Ieee;Use ieee.std_logic_1164.all;

entity or2 isport ( a, b :in std_logic;

c :out std_logic);end or2;

Architecture a of or2 isbegin

c

15

Example-1: A Half Adder Description Using Data-Flow Model

library ieee;use ieee.std_logic_1164.all;

entity Hadder isport ( A, B : in std_logic;

Cout, Sum : out std_logic);end Hadder;

Architecture a of halfadder isbegin

Sum

17

The Circuit and Simulation Test of the One-Bit Full Adder

Hadder Hadder

18

Example-2:The Full Adder Description Using Data-Flow Model

entity FullAdder isport (X, Y, Cin : in bit; --Inputs

Cout, Sum : out bit); --Outputsend FullAdder;

architecture Equation of FullAdder isbegin -- Concurrent Assignments

sum

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The Full Adder gdf file using two half adders and an OR gate

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Example-2a:The Full Adder Using VHDL Structure Description-1


entity Fadder isport (a, b, cin : in std_logic;

Co, So : out std_logic);end Fadder;

architecture structure of Fadder iscomponent Hadder

port (a, b : in std_logic;cout, sum : out std_logic);

end component;signal s1, s2, s3 : std_logic;begin

ha0: Hadder port map (a => a, b => b, cout => s2, sum => s1);ha1: Hadder port map (a => s1, b => cin, cout => s3, sum => So);Co

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Example-2b:The Full Adder Using VHDL Structure Description-2


entity Fadder_1a isport (a, b, cin : in std_logic;

Co, So : out std_logic);end Fadder_1a;

architecture structure of Fadder_1a iscomponent Hadder

port (a, b : in std_logic;cout, sum : out std_logic);

end component;signal s1, s2, s3 : std_logic;begin

ha0: Hadder port map (a, b, s2, s1);ha1: Hadder port map (s1, cin, s3, So);Co

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A Four-bit Ripple-Carry Full-Adder

FA

1A 1B

1s

FA

0A 0B

0s

FA

2A 2B

2s

FA

3A 3B

3s

outc 0c1c2c3c ic4c

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Example-3: Structural Description of the 4-bit Adder Using Mapping with Order

entity Adder4 isport (A, B : in bit_vector (3 downto 0); Ci : in bit; --Inputs

S : out bit_vector (3 downto 0); Co : out bit; --Outputsend Adder4;architecture Structure of Adder4 iscomponent FullAdder

port (X, Y, Cin : in bit; -- InputsCout, Sum : out bit); -- Outputs

end component;signal C : bit_vector (3 downto 1);begin -- Concurrent Assignments

FA0 : FullAdder port map (A(0), B(0), Ci, C(1), S(0));FA1 : FullAdder port map (A(1), B(1), C(1), C(2), S(1));FA2 : FullAdder port map (A(2), B(2), C(2), C(3), S(2));FA3 : FullAdder port map (A(3), B(3), C(3), Co, S(3));

end Structure;

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Example-4: Structural Description of a 4-bit Adder Using Mapping with Order with For … Generate

entity Adder4_a isport (A, B : in bit_vector (3 downto 0); Ci : in bit; --Inputs

S : out bit_vector (3 downto 0); Co : out bit; --Outputsend Adder4_a;architecture Structure of Adder4_a iscomponent FullAdder

port (X, Y, Cin : in bit; -- InputsCout, Sum : out bit); -- Outputs

end component;signal C : bit_vector (4 downto 0);begin -- Concurrent Assignments

C(0)

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2:1 Multiplexer Circuit and Simulation Test

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VHDL Data-Flow Description of A 2:1 Multiplexer

Entity MUX2_a isport

(a, b, s : in bit;F : out bit);

end MUX2_a;

architecture maxpld of MUX2_a isbegin

F

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Conditional Signal Assignment-1

Entity MUX2_b isport

(a, b, s : in bit;F : out bit);

end MUX2_b;

architecture maxpld of MUX2_b isbegin

F

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Sequential Statement

• IF-THEN-ELSE• CASE• LOOP• ASSERT• WAIT

32

IF-THEN-ELSE (1)

IF condition THENsequential_statements

{ ELSIF condition THENsequential_conditions }

[ ELSEsequential_statements ]

END IF;

• Example : 2-1 Mux語法:

library ieee;use ieee.std_logic_1164.all;entity mux2_c is

port (a, b, s: in std_logic;F : out std_logic);

end mux2_c; architecture behav of mux2_c isbegin

process (s, a, b)begin

if s = '0' thenF

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MUX2 Behavior Description using Case-When

library ieee;use ieee.std_logic_1164.all;entity mux2_d is


end mux2_d; architecture behav of mux2_d isbegin

process (s, a, b)begin

case s iswhen '0' =>

F

F

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4:1 Multiplexer Circuit and Simulation Test

36

MUX4 Structural Description Using Port Mapping with Name Association

--structural descriptionlibrary ieee;use ieee.std_logic_1164.all;entity mux4_b is

port (a, b, c, d: in std_logic;s1, s0: in std_logic;F : out std_logic);

end mux4_b; architecture struc of mux4_b iscomponent mux2_b


end component; signal F1, F2: std_logic;begin

m0: mux2_b port map (a=>a, b=>b, s=>s0, F=>F1);m1: mux2_b port map (a=>c, b=>d, s=>s0, F=>F2);m2: mux2_b port map (a=>F1, b=>F2, s=>s1, F=>F);

end struc;

37

MUX4 Structural Description Using Port Mapping with Order

--structural descriptionlibrary ieee;use ieee.std_logic_1164.all;entity mux4_b1 is

port (a, b, c, d: in std_logic;s1, s0: in std_logic;F : out std_logic);

end mux4_b1; architecture struc of mux4_b1 iscomponent mux2_b


end component; signal F1, F2: std_logic;begin

m0: mux2_b port map (a, b, s0, F1);m1: mux2_b port map (c, d, s0, F2);m2: mux2_b port map (F1, F2, s1, F);

end struc;

38

MUX4 Structural Description Using

--Behavior descriptionlibrary ieee;use ieee.std_logic_1164.all;entity mux4_c is

port (a, b, c, d: in std_logic;s: in std_logic_vector (1 downto 0);F : out std_logic);

end mux4_c;

architecture behav of mux4_c isbegin

F

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MUX4 Behavior Description Using If-Then-Else

--Behavior descriptionlibrary ieee;use ieee.std_logic_1164.all;entity mux4_d is

port (a, b, c, d: in std_logic;s: in std_logic_vector (1 downto 0);F : out std_logic);

end mux4_d; architecture behav of mux4_d isbegin

process (s, a, b, c, d)begin

if s = "00" then F

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VHDL process – Example (7) : dff

ARCHITECTURE behavior OF dff ISBEGIN

PROCESSBEGIN

IF(CLR = ‘0’) THENQ

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2. An 8-Bit Full Adder

44

8-Bit Adder/Substractor

M F

0 X + Y

1 X - Y

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VHDL Behavior Description for an 8-Bit Adder/Subtractor

--Behavior descriptionlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity add_sub8 is

port (a, b: in std_logic_vector(7 downto 0);m: in std_logic;y : out std_logic_vector(7 downto 0));

end add_sub8;

architecture behav of add_sub8 isbegin

process (m, a, b)variable temp:std_logic_vector(8 downto 0); begin

temp := “000000000”;if m = '0' then

temp := a + b;else

temp := a - b;end if;

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VHDL Behavior Description for an 8-Bit Adder/Subtractor (cont’d)

if temp(8) = '0' then -- check overflowif temp(7) = '0' then

y

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3. An 8-Bit Shifter (using MUX4 and MUX2)

S2 S1 S0 F Comment

0 0 X D No shift (不移)0 1 X Not used1 0 0 Shl(D) Shift left (左移)1 0 1 Rtl(D) Rotate left (左旋轉)1 1 0 Shr(D) Shift right (右移)1 1 1 Rtr(D) Rotate right (右旋轉)

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Simulation Test of the 8-Bit Shifter

No shift Not used Shift left(Rin=1)

Rotate left Shift right Rotate right

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8-Bit Shifter using VHDL

entity shift8_2 isport(d: in bit_vector(7 downto 0); Lin, Rin: in bit;

S: in bit_vector(2 downto 0); f: out bit_vector(7 downto 0));end shift8_2;architecture behav of shift8_2 isbegin

f

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The Block Diagram for PWM Signal Generation

Comparator

Up-Counter

LatchPWM

Vo

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2-Bit Comparator Design

x1 y1 x0 y0 G L

0 0 0 0 0 00 0 0 1 0 10 0 1 0 1 00 0 1 1 0 00 1 0 0 0 10 1 0 1 0 10 1 1 0 0 10 1 1 1 0 11 0 0 0 1 01 0 0 1 1 01 0 1 0 1 01 0 1 1 1 01 1 0 0 0 01 1 0 1 0 11 1 1 0 1 01 1 1 1 0 0

Truth Table X1 y1X0 y0

00 01 11 10

00

01

11

10

1

1

1

1 1 1

''''

001

00111

yxyyxxyxG

++=

X0 y000 01 11 10

00

01

11

10

1

1

1

1 1 1001

00111

''''

yxyyxxyxL

++=

X1 y1

If X > Y then G=1, else if X < Y then L=1, else G=L=0.

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Circuit of the 2-Bit Comparator

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Block Diagram of a 5-Bit Comparator

x1 y1x0

y0Cmp2

G L

x1 y1x0

y0Cmp2

G L

x1 y1x0

y0Cmp2

G L

x1 y1x0

y0Cmp2

G L

A4 B4 A3 B3 A2 B2 A1 B1 A0 B0

G L

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Circuit of the 5-Bit Comparator

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VHDL Model for the PWM Signal Generation

entity pwm_4b1 isport( RST, clk1 : in STD_LOGIC ;

VAREF : in STD_LOGIC_VECTOR(9 downto 0) ;--0~1023PWMout : out STD_LOGIC);

end pwm_4b1;architecture RTL of pwm_4b1 issignal CNT : STD_LOGIC_VECTOR(9 downto 0);begin

process( CLK1, RST )begin

if (RST='1') thenCNT '0') ; PWMout

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Dead-Time Compensation to Avoid the Shoot Through of the DC Link

pwm1

pwm2Q1 Q3

Q2 Q4

Without dead-time compensation

pwm1

pwm2

With dead-time compensation

Dead time Dead time

DC Link

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VHDL Code for the Dead-Time Compensation of PWM-1

architecture RTL of dead_time issignal DTCNT, CNT1: STD_LOGIC_VECTOR(2 downto 0);begin

DTCNT

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5. An R-C Circuit as a Controlled Plant

+−

Ω= K10R

µF10=C

+

−

ovsv.101where

,1

11

11

1

)()(

)(

0

0

==

+=

+=

+==

RC

ssRCsC

R

sCsvsv

sGi

op

ω

ω

dBpjG )( ω

0100 =ω

./20 decdB−

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A PI Controller Design

01

1

ωs

++−e

sk

k ip +

By Pole-Zero Cancellation Technique

00 /11

)1(

/11)(

ωω ss

skk

k

ssksk

sG ip

iip

ol +

+=

+

+=

Let 100 == ωi

p

kk

thensk

sG iop =)(

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The Bode Plot of the Open-Loop Gain and the Closed-Loop Gain

sk

sG iol =)(

i

i

i

i

i

cl

ksks

k

sk

sk

sG+

=+

=+

=1

1

1)(

ωik

iklog20

dBol jG )( ω

ωik

iklog20

dBcl jG )( ω

./20 decdB−

./20 decdB−

0dB

62

Simulink Simulation Block Diagram with Bandwidth of 100 rad/s

Let 10

100=⇒

=

p

i

Kk

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Comparison of the Step Responses without and with Closed-Loop Control

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

0.2

0.4

0.6

0.8

1

Time, sec

y1, V

olt

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

0.2

0.4

0.6

0.8

1

Time, sec

y2, V

olt

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The Sampling Control System

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Step Response using the Sampling Control with T=0.001

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

0.2

0.4

0.6

0.8

1

Time, sec

y, V

olt

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

5

10

15

Time, sec

uc, V

olt

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Implementation Block of the PI Controller

11 −−+

zTk

k ip +−Tki

pk

1−z

++

+++−

)()1()(1 1

kTekkykyzTk

ey

i

i

+−=⇒−

=−

e e y(k)

y(k-1)ov

refv

ov

refv cu cu

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The Interface Circuit of the Sampled Control System

Ω= K10R

µF10=C

+

−

ov

A/D

OPAmp

2+D/A

ADC0804

ADC0800

CPLD

1R

2R

V)10(±

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Register-Transfer-Level Block Diagram

ALU ÷× /

Datapath outputs

Mux

MemoryRFRegister

Register

DatapathInputs

Bus1Bus2

Bus3

Next-StateLogic

OutputLogic

D Q

D Q

D Q

clk

Controlinputs

Status signals

Controlsignals

Control Unit Datapath

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Circuit Block of a PI Controller

Reference

Control Unit Data path

control

status

Output

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VHDL Codes of the PI Control

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pi_ctrl_8 isport(

CLK : in STD_LOGIC;RST : in STD_LOGIC;pi_com: in STD_LOGIC_VECTOR(7 downto 0);--

refFEB : in STD_LOGIC_VECTOR(7 downto 0);KP : in STD_LOGIC_VECTOR(7 downto 0);KI : in STD_LOGIC_VECTOR(7 downto 0);pi_out : out STD_LOGIC_VECTOR(7 downto 0));

end pi_ctrl_8 ;

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VHDL Codes of the PI Control (cont’d-1)

architecture RTL of pi_ctrl_8 isTYPE state_type is (idle,s1,s2,s3,s4,s5);signal state : state_type ;component add_sub8

port(m : in STD_LOGIC ;a : in STD_LOGIC_VECTOR(7 downto 0);b : in STD_LOGIC_VECTOR(7 downto 0);y : out STD_LOGIC_VECTOR(7 downto 0));

end component;signal CTL : STD_LOGIC ;signal as_a,as_b,as_z : STD_LOGIC_VECTOR(7 downto 0);component mult8a_sign

port(a : in STD_LOGIC_VECTOR(7 downto 0);b : in STD_LOGIC_VECTOR(7 downto 0);y : out STD_LOGIC_VECTOR(7 downto 0));

end component;signal mult_a, mult_b, mult_z : STD_LOGIC_VECTOR(7 downto 0);signal CNT : STD_LOGIC_VECTOR(7 downto 0);signal CEN : STD_LOGIC ;signal err_temp, ydelay_temp : STD_LOGIC_VECTOR(7 downto 0);

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beginA1 : mult8a_sign port map (mult_a, mult_b, mult_z);A2 : add_sub8 port map (CTL, as_a, as_b, as_z);

process( RST, CLK )variable SR : STD_LOGIC_VECTOR(7 downto 0);begin

SR := "00001110" ;-- wait for samplingif ( RST='1' ) then

state

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case state iswhen idle =>

if (CEN='1') then state

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