文档名称 文档密级F28032 Abnormal during the Rectifier output short and full load switching test

Issues Description:

During the rectifier output 58V&50A output shorting test with external RELAY： switch from

short to 50A full load frequently, F28032 of DCDC will turn off abnormally with CAN not

triggered and GPIO abnormally triggered(Normally worked as 50% duty 146ms period square

ware).

1、 Test Procedure and waveform

1) Figure 1& 2 shows the DSP GPIO worked abnormally, and the GPIO would output 3.6ms

square waveform with 400us low state.

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FIGURE 1&2 F28032 Abnormal waveform

CH2:F28032 GPIO CH3：Aux Power Input CH4：PDU output current

2) Meanwhile test the XRS signal while the abnormal shown up. XRS signal keep high state

with 3.3V。

FIGURE 3 XRS signal waveform

CH1：XRS CH2:GPIO CH4：PDU output current

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文档名称 文档密级3) Test the XRS/GPIO states with test source code for IDLE/STANDBY/HALT states:

change the SysCtrlRegs.LPMCR0.bit.LPM value for the F28032 C28 states which make

the F28032 enter to IDLE/STANDBY/HALT states, test the GPIO states with the scope

link to different C28 states, which is different from the issues description;

FIG.4 CH1：GPIO（HALT） FIG.5 CH1：GPIO（STANDBY）

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FIG.6 CH1：GPIO（IDLE）

4) Test the VDDIO/CLKOUT/XRS of F28032 while the abnormal happened. Figure 7

shown that while the F28032 abnormal happened, the CLKOUT frequency dropped from

60Mhz to 1.34Mhz, and then CLKOUT turn to 0Mhz, and the VDDIO will with bigger

ripple(lowest is 2.836V), Figure8 shows that the CLKOUT would output 1.3Mhz

waveform every 3.5ms, and the VDDIO is about 3.3V, but the F28032 can’t work

normally.。

FIG7 CH2:VDDIO CH3: XRS CH4:CLOCK_OUT

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FIG8 CH2:VDDIO CH4:CLOCK_OUT

5) Change to using internal OSC1 as system clock source, the CLKOUT output 15Mhz waveform(1/4 of

60Mhz System Clock)，Using external OSC(20Mhz), and the clkout frequency is 60Mhz same as

system clock. Figure 9 shows that while abnormal happened with the software configuration, the

CLKOUT would output 48us@15Mhz frequency, and then 397us@1.2Mhz every 3.5ms.

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FIG9 CH4:CLOCK_OUT

Monitor the CLKOUT signal for the power up sequency(From Loader to APP), the CLKOUT

output 15Mh, keep low for a while and then output 3.34ms 1.25Mhz frequency, and then

60Mhz Frequency.

6) Change clock source to internal OSC1 in bootloader and APP, test the PDU output shorten and full load

situation for about 1hour, the F28032 worked normally.

Support Need:

1) From the test procedure, the abnormal state is not recorded like LIMP/STANDBY/HALT/IDLE mode,

could BU side give comments for the CPU states and how to identify the CPU states?

2) According to customer’s feedback, the abnormal seems happened while the VDDIO with larger ripper and

external OSC, any comments for the reasons of the abnormal? Should higher the VDDIO and add more

capacitors for VDDIO filter?

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