Embedding the MicroBlaze soft processor core on the Digilent board NEXYS 3

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Table of Contents

Target of Document..........................................................................................................................3

Overview............................................................................................................................................3

Create Repository..............................................................................................................................4

Build a New System in XPS (Xilinx Platform Studio).....................................................................5

Add a new Internal Peripheral.......................................................................................................17

Creating a New Internal Peripheral.......................................................................................................17

Adding an External Connection..............................................................................................................29

Modify the “user_logic.vhd” File...........................................................................................................................29

Modify the “name_new_peripheral.vhd“...............................................................................................................32

Modify the “name_new_peripheral.mpd”..............................................................................................................35

Include New Peripheral in the System...................................................................................................37

Build a New SDK Project................................................................................................................45

Create a PlanAhead Project............................................................................................................59

Implementation in the Board..........................................................................................................66

Different links.................................................................................................................................66

Listings............................................................................................................................................68

Appendix..........................................................................................................................................71

Hello_World..............................................................................................................................................71

Listing 1..................................................................................................................................................................71

LED_Flash................................................................................................................................................71

Listing 2..................................................................................................................................................................72

Remote_ robot...........................................................................................................................................72

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Target of DocumentThe goal of this document is to explain how to build a project using the MicroBlaze soft processor core with NEXYS 3. The MicroBlaze system is a virtual microprocessor which works similarly to real processors such as the Arduino or 8051 etc. It is implemented in the general-purpose memory and logic fabric of Xilinx FPGAs. The following document will describe how to run a variety of programs using MicroBlaze, including: HelloWorld to UART, sw to LEDs/7segment display and the controlling of a robotic arm. These programs will be run on the NEXYS 3 (FPGA: Spartan6) board designed by Digilent, but it is also possible to use the same tutorial to create a MicroBlaze system with Spartan 3.

OverviewThe project requires the use the Xilinx Embedded Development Kit (EDK). This is an integrated development environment for creating embedded processing systems. The kit includes the Xilinx Platform Studio and the Software Development kit,

1) Xilinx Platform Studio (XPS) [Creating an Embedded Hardware System].This software is used to create the MicroBlaze system on the NEXYS 3 device. It allows the hardware designer to easily build, connect and configure embedded processor-based systems; this ranges from basic state machines to soft processor cores such as MicroBlaze.

2) Software Development Kit (SDK) [Creating Software for the Embedded System].This software is used for creating the embedded application on MicroBlaze.(Note, as the SDK is built on Java, there may be errors encountered due to the version of Java currently installed. It is important to have an up to date Java version that does not interfere with the SDK).

Once the MicroBlaze system has been created, in XPS the application C program can be written using the SDK.

The project also requires the use of Digilent Adept software, which will program the NEXYS 3. Separate software is needed for this because SDK and PlanAhead program through the JTAG cable and Adept programs through the UART cable.

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FlowchartThe following flowchart has been generated to better describe the process of creating applications for MicroBlaze.

Create Repository Create a new folder on the hard disk for saving the project data. Within this folder, create the following folders:

1) ‘PlanAhead’2) ‘SDK_Project’3) ‘XPS_Project’

Next, download the support files for the system; “Nexys3 Board support files for EDK BSB wizard. Supports EDK 13.2-14.4 for both AXI and PLB buses” on the Digilent website at either link:

http://www.digilentinc.com/Data/Products/NEXYS3/Nexys3_BSB_Support_v_2_7.zip

or

http://www.digilentinc.com/Support/Support.cfm?ProdCat=NEXYS3&DocType=Reference+Designs

Extract the folder titled ‘Nexys3_PLB_BSB_Support’ from the zip folder and copy into the repository, as seen in Figure 1.

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Figure 1: Repository Example

Build a New System in XPS (Xilinx Platform Studio) Now we will create a new MicroBlaze system in the internal architecture of the FPGA. Open XPS software.

Figure 2: XPS Start-Up Menu

Click on the “Create New Project Using Base System Builder”, a new window appears (Figure 3).

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Figure 3: Create New XPS Project Window

Select where the XPS project is saved (in repositories XPS folder) and write the name of the system i.e ‘system_nexys3 or system_remoterobot_nexys3’ for example. Choose PLB system. PLB it is the name of the bus used by MicroBlaze to communicate with the other peripherals.

Import the board configuration. In the repository open the Nexys3_PLB_BSB folder and select the lib folder ‘Nexys3_PLB_BSB_Support\lib’. The following window should be displayed, Figure 4.

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Figure 4: Configuration of Create New XPS Project window

Click “OK”, a new window appears, Figure 5.

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Figure 5: Base System Builder Welcome Window

Chose “I would like to create a new design”, click “Next”, a new window appears, Figure 6.

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Figure 6: Base System Builder Board Select Window

If you want select a board, chose the board in the Board tab. We chose to use a Digilent board NEXYS 3. This board automatically appears as the data was imported when the system was created.

If you want select a particular FPGA click on “I would like to create a system a custom board”. When you have chosen your board or your FPGA click “Next” and a new window appears, Figure 7.

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Figure 7: Base System Builder System Window

Next, choose how many processors are in the project. We choose to use only one processor. Click “Next” and a new window appears, Figure 8.

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Figure 8: Base System Builder Processor Window

Here, choose the main characteristics of the MicroBlaze system. We can choose the clock frequency and the local memory allocated for storage.

We have chosen an 83.33MHz frequency and 64KB memory. When you have finished selecting this element, click “Next” and a new window appears, Figure 9.

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Figure 9: Base System Builder Peripheral Window

Here, we choose the peripherals included in the new system. The peripherals in the right column are already included in the system and the peripherals on the left are not included.

Click “< Remove” to remove peripherals, and the following are the only remaining ones:

- DIP_Switches_8Bits- Digilent_SevSeg_Disp- LEDs_8Bits- Push_Buttons_4Bits- RS232_Uart_1

Dlmb_cntlr and ilmb_cntlr need to be included, Figure 10. FD 09.05.2023 12/78 V02

Figure 10: Configuration of Base System Builder Peripheral Window

When the internal peripherals have been chosen, click “Next” and a new window appears, figure 11.

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Figure 11: Base System Builder Cache Window

This window allows you to configure the external memory. If you haven’t chosen to use additional memory, this window is empty. Click “Next” and a new window appear, figure 12.

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Figure 12: Base System Builder Summary Window

A summary of the main characteristics of the generated system are displayed and the location of the file created. Click “Finish” this window closes and you arrive in the XPS software, Figure 13.

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Figure 13: XPS management MicroBlaze project

Now, the MicroBlaze system is configured with the use of the on board switches, buttons, LED’s and 7segment and UART. There are two options:

1) An external peripheral is not needed for the project application. The application can be run using the existing configured system i.e switches. This section includes an example of Hello World, a switch button LED light up program.Click on the “Generate BitStream” then you click on the “Export SDK” and see the Built new SDK project.

2) An external peripheral is needed for the project application. The application must communicate with board input/output pins.This section includes an example application of driving a robotic arm.Jump to Add a new internal peripheral section.

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Add a new Internal PeripheralThe MicroBlaze system has been created in the previous stage. Now, you are adding a new peripheral and you are modifying this peripheral for driving an external board or system i.e drive a robot.

To create a new peripheral can be divided into three parts:

1) Creating the new peripheral.2) Modifying a different file to allow a signal to output from the FPGA. 3) Include the new peripheral in the XPS System.

Creating a New Internal Peripheral

In the XPS software, click on the “Create and Import Peripheral” icon, or click “Hardware\Create or Import Peripheral”. A new window appears, Figure 14.

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Figure 14: Create and Import Peripheral Welcome Window

Click “Next” and a new window appears, Figure 15.

Figure 15: Create and Import Peripheral, Peripheral Flow Window

In this window, you can choose to create a new peripheral or to import a peripheral. We choose to “Create template for a new peripheral”. Click “Next”, a new window appears, Figure 16.

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Figure 16: Create Peripheral, Repository or Project Window

Next, choose the location for saving the new peripheral (in the EDK repository or a XPS repository). We chose the XPS repository. Click “Next”, a new window appears, Figure 17.

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Figure 17: Create Peripheral, Name and Version Window

Now, you write the name of your new peripheral. We choose the name “ip_remot_robot”. If you want, you can write a description of your new peripheral. Click “Next” and a new window appears, Figure 18.

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Figure 18: Create Peripheral, Bus Interface Window

Next, choose the communication bus to be used by MicroBlaze to communicate with the new peripheral. The MicroBlaze system was created with the PLB Bus in Build a New System in XPS (Xilinx Platform Studio), therefore choose to use ‘Processor Local Bus (PLB v4.6)’ PLB Bus with the new peripheral. Click “Next” and a new window appears, Figure 19.

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Figure 19: Create Peripheral, IPIF (IP Interface) Services

Next, configure the new peripheral. Choose if the new peripheral has a “Software reset”, “user logic memory space”, “Read/Write FIFO” etc… We have chosen to select only “User logic software register” and “Include data phase timer”. Click “Next” and a new window appears, Figure20.

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Figure 20: Create Peripheral, Slave Interface Window

This window is used to configure the slave on the PLB bus. As we have chosen to use the new peripheral in slave there is no choice. Click “Next” and a new window appears, Figure21.

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Figure 21: Create Peripheral, User S/W Register

Next, choose the number of 32 bit registers which can be read from and written to by the MicroBlaze system through the PLB bus. We have chosen only one register. When you have chosen the number or registers, click “Next” and a new window appears, Figure 22.

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Figure 22: Create Peripheral, IP Interconnect (IPIC) Windows

Now, you should choose the signal which will be used to communicate between the User logic part and the PLB bus. We left “Bus2IP_Add”, “Bus2IP_CS” and “Bus2IP_RNW” unselected. When you have made your choice, click “Next” and a new window appears, Figure 23.

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Figure 23: Create Peripheral, (OPTIONAL) Peripheral Simulation Support

Here, it is possible to generate a BFM simulation platform. We have chosen to leave this option black. Click “Next” and new window appears, Figure 24.

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Figure 24: Create Peripheral, (OPTIONAL) Peripheral Implementation Support Window

This window permits the choice of implementation options. We choose to select “Generate ISE and XPS project files to help you implement the peripheral using XPS flow” and “Generate template driver files to help you implement software interface”. Click “Next” and a new window appears, Figure 25.

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Figure 25: Create Peripheral, Congratulation Window

This window shows the location of the files to be saved and the files generated. Click “Finish”, the software creates the new peripheral and the file associate with. When the software has finished working this window disappears.

The internal peripheral has been created. There are two options:

1) Create an external connection between this new peripheral and the external pin of the FPGA. Go to Adding an external connection.

2) If you do not want to use an external connection, continue to Include New Peripheral in the system.

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Adding an External ConnectionWe modify the two VHDL file of the new peripheral: “name_new_peripheral” and “user_logic”. They can be found in location: “name_project\XPS_Project\pcores\name_new_peripheral\hdl\vhdl”, Figure 26.

Figure 26: Path to two new peripheral VHD files

Modify the “user_logic.vhd” FileOpen the “user_logic.vhd” with XPS software. This file is the user logic part of our new peripheral. In this file, you are declaring our external signal. We write also the function which generates our external signal.

Figure 27 shows where you declare the new external signals, line 100.

Figure 27: Declare the new external signal in the “user_logic.vhd”

We add three signals:

- cmd_robot_mot : out std_logic_vector(0 to 9);- cmd_robot_led : out std_logic;

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- cmd_led_board_drive_robot : out std_logic;

Figure 28: Declaration of the new external signal in the “user_logic.vhd”

Next, write the function which generates these external signals. The location to write the functions can be seen, Figure 29 line 150.

Figure 29: Declare the function with external signals in “user_logic.vhd”

We have chosen to write these allocations:

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- cmd_robot_mot(0 to 9) <= slv_reg0(0 to 9);- cmd_robot_led <= slv_reg0(10);- cmd_led_board_drive_robot <= slv_reg0(11);

You can see in figure 30 where you write these allocations, line 150.

Figure 30: External signal allocation in “user_logic.vhd”

When you have finished, save this file.

We have generated a new external signal. Now you have to map these signals to the pin in the top level. This top level is “name_new_peripheral.vhd”. So continue to Modify the “name_new_peripheral.vhd”.

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Modify the “name_new_peripheral.vhd“ Open the “name_new_peripheral.vhd” with XPS software, in this case “ip_remote_robot.vhd”. This file is the top level of your peripheral. Declare your external signal below the entity and port, as shown in figure 31.

Figure 31: Declare new external signal in the “name_new_peripheral.vhd”

Write the declaration of your external signal. We choose to add three signals:

- cmd_robot_mot : out std_logic_vector(0 to 9);- cmd_robot_led : out std_logic;- cmd_led_board_drive_robot : out std_logic;

Below, you can see how we have declared these new signals, Figure 32 line 165.

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Figure 32: Adding New External Connection in Declaration

It is now necessary to add the new signal in the port map.

Figure 33: Add the New Signal Port Map

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We chose to add in port map:

- cmd_robot_mot => cmd_robot_mot,- cmd_robot_led => cmd_robot_led,- cmd_led_board_drive_robot => cmd_led_board_drive_robot,

The added signals can be seen in figure 34, line 397.

Figure 34: New Port Map in the “name_peripheral.vhd”

When you have added the declaration of the external signal and added the mapping, save this file and close it.

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Modify the “name_new_peripheral.mpd”We have included a signal that connects with the FPGA exterior in the new peripheral. To include this modification in the XPS System, it is necessary to add these signals in the “name_new_peripheral.mpd” file. The file path is in the following location shown in figure 35, “name_project\XPS_Project\pcores\name_new_peripheral\data”.

Figure 35: Path of the .mpd file

Open this file “name_new_peripheral.mpd” with XPS software, i.e “ip_remot_robot_v2_1_0.mpd”.

We include the following lines of codes:

- PORT cmd_robot_mot = "", DIR = O, VEC = [0:9],- PORT cmd_robot_led = "", DIR = O,- PORT cmd_led_board_drive_robot = "", DIR = O,

For signals that you may have that are not included in this description, follow this format. These signals are a port. DIR = O is showing that they are outputs. Declare also if the signal is a bus, or a single signal.

The modifications can be seen in figure 36, line 38.

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Figure 36: Added Modifications to “name_new_peripheral.mpd”

When you have written this modification save and close this file. You have included this modification in the XPS system and you have added this new peripheral in the system. Next read Include New Peripheral in the system.

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Include New Peripheral in the SystemYou have created a new peripheral and you have created an external connection. Now, we have added the new peripheral in the system.

In the XPS software, click on “Rescan User Repositories” on “Project -> Rescan User Repositories”, shown in Figure37.

Figure 37: Rescan User Repositories

Now in the “IP Catalog tabs”, you can see the IP that you have created, as shown in figure 38.

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Figure 38: Newly created IP

Next double click on the created IP “IP_create” and slide on the “Bus Interface” tabs. This action includes the new peripheral into the system. A new window appears.

Figure 39: Add IP Instance to Design Window

Click “Yes” and a new window appears, Figure40.

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Figure 40: XPS Core Config Window

This window is a summary of the peripheral that you will add. You can see the schematic of the peripheral. Our peripheral has 1 SPLB input for communicating with the MicroBlaze and its three external outputs. Click “OK”, this window closes and you can see that the new peripheral is included in the system, Figure 41.

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Figure 41: Check if the peripheral is included

We can see that the new peripheral isn’t connecting at the PLB bus. To connect; click on the drop-down menu near “SPLB” and choose the “mb_plb” connection, Figure 42.

Figure 42: Connect New Peripheral at the PLB Bus

Click on the Address Tab at the top. The new peripheral has no address. To generate this address, click on the “Generate Addresses” icon in the top right hand corner, Figure 43.

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Figure 43: Address tabs with Generated Addresses

Next, look in the “Ports” tabs and in the new peripheral you can see that the three external signals are not connected.

Note: If the ‘Net’ tab isn’t visible along with the ‘Direction’, ‘Range’ etc, right-click on one of the tabs and select ‘Net’, it should now appear, Figure 44.

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Figure 44: XPS Port tabs, External Signals Not Connected

To connect this signal, click on the drop-down menu near the red pen and select the “Make External”, Figure 45.

Figure 45: Connection of the External Signal

Now the external signal is connected at the exterior pin. But it is necessary to modify the User Constraints File (.ucf file) to allocate a pin of the FPGA at these signals. Double-click on the “UCF File: data\system_nexys3.ucf” in the Project tabs, as shown in figure 46.

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Figure 46: Open system .ucf file

This action opens the UCF file in the XPS so we can add the pin corresponding to the external signal. Find the name of the external connection pin in the “Port” tabs.

Figure 47: Name of pin

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Add in the following modifications to the UCF file:

Net ip_remote_robot_0_cmd_robot_mot_pin<0> LOC=T12 | IOSTANDARD=LVCMOS33;

Net ip_remote_robot_0_cmd_robot_mot_pin<1> LOC=V12 | IOSTANDARD=LVCMOS33;

Net ip_remote_robot_0_cmd_robot_mot_pin<2> LOC=N10 | IOSTANDARD=LVCMOS33;

Net ip_remote_robot_0_cmd_robot_mot_pin<3> LOC=P11 | IOSTANDARD=LVCMOS33;

Net ip_remote_robot_0_cmd_robot_mot_pin<4> LOC=M10 | IOSTANDARD=LVCMOS33;

Net ip_remote_robot_0_cmd_robot_mot_pin<5> LOC=N9 | IOSTANDARD=LVCMOS33;

Net ip_remote_robot_0_cmd_robot_mot_pin<6> LOC=U11 | IOSTANDARD=LVCMOS33;

Net ip_remote_robot_0_cmd_robot_mot_pin<7> LOC=V11 | IOSTANDARD=LVCMOS33;

Net ip_remote_robot_0_cmd_robot_mot_pin<8> LOC=K2 | IOSTANDARD=LVCMOS33;

Net ip_remote_robot_0_cmd_robot_mot_pin<9> LOC=K1 | IOSTANDARD=LVCMOS33;

Net ip_remote_robot_0_cmd_robot_led_pin LOC=L4 | IOSTANDARD=LVCMOS33;

Net ip_remote_robot_0_cmd_led_board_drive_robot_pin LOC=L3 | IOSTANDARD=LVCMOS33;

.

Figure 48: Modified .ucf File

Save and exit the .ucf file.

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Build a New SDK Project Next, create a new SDK Project for programming the new system. In the XPS software, click on “Generate BitStream” icon or find it in “Hardware -> Generate BitStream”. This may take several minutes. During this time, the software creates a different VHDL file.

Note: Antivirus software may need to be disabled during the BitStream generation process as the software may interpret the generated files as threats and lock them in the antivirus 'vault'.

Figure 49: XPS BitStream is Generated

When the BitStream is generated, the Design Summary show in figure 49 is displayed. Click on “Export Design” icon then select ‘Export and launch’ or find this function in “Project -> Export Hardware Design to SDK”. The SDK is now open ed.

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Figure 50: Export to SDK / Launch SDK

Click on “Export & Launch SDK”. Wait several minutes while the SDK software is opening.

Figure 51: Workspace launcher SDK window

Click browse and select the “SDK_Project” folder that was created at the beginning and click “OK”. The SDK creates a new workspace in the “SDK_Project” folder. A new window appears after this.

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Figure 52: SDK window after the exportation

If this window appears close this tab (use the close at the top of left). A new window appears.

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Figure 53: XPS Design exported to SDK

In the left column of this window you can see one folder and three files. These files and folder are created from the exportation.

Next, we create a new board support package. This step creates the .c and .h files and a driver file necessary for programming MicroBlaze. Click on “File -> New -> Other”, and a new window appears.

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Figure 54: New file window in SDK. Chose Board Support Package

Click on the “Xilinx” option, select “Board Support Package” and click on “Next”. A new window appears.

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Figure 55: New Board Support Package Project window

Change the name if desired. In the “Hardware Platform” option, the Hardware that you have exported by XPS is normally the only choice. Click “Finish”.

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Figure 56: Board Support Package Settings window

Click “OK” and the window disappears and waits a moment. The SDK software creates a different file.

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Figure 57: SDK after the Board Support Package generation

“Project Explorer” shown in figure 57 shows the files generated. The “Peripheral Drivers” gives information and examples of using the drivers created, if you wish to read about them.

Now, you create a new C project for writing the program implemented in MicroBlaze. Click on “File -> New -> Other” and a new window appears, figure 58.

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Figure 58: New menu to create a new C project

Choose the “Application Project” and click “Next”, a new window appears, figure 59.

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Figure 59: New Project Application Project window

Choose a project name, we chose “remote_robot”. In “Hardware Platform” select the platform that was imported by the XPS. Then, choose “standalone” in “OS Platform”. A standalone OS will execute only the main function, and is all that is required by MicroBlaze.

Select C language, and choose to “use existing” in “Board Support Package”. Click “Next”, a new window appears, figure 60.

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Figure 60: New Project Templates window

Choose “Empty Application”, and the SDK will create a blank C Project. Click “Finish”, this window disappears.

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Figure 61: SDK software after the generation of a C project

The created C project and its files can be seen in figure 61 in the “Project Explorer”. Right-click within the project files and select “New -> Source File”, to create the C file to be executed by MicroBlaze, figure 62.

Figure 62 Path to Create a New C Source File

A new window appears, figure 63.

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Figure 63: New Source File Window

The name “main.c” must be given to this file, as MicroBlaze only executes the “main.c” file. Click “Finish”, the window disappears and the “main.c” file is opened, figure 64.

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Figure 64: Blank main.c File

The file must return something, setting a “return 0” before beginning your program will ensure you do not forget to do this, as shown in figure 65.

int main ()

{

return 0;

}

Figure 65: main.c file returning 0

Now, you can write the program executed by MicroBlaze. The following example programs can be found in the Appendix:

1) Hello_World2) Led_Flash 3) Remote_Robot

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Note: It was discovered that the HyperTerminal could be used to interpret the incoming Ascii characters being sent from the FPGA to the Com port. This enabled debugging of the application and the development of the tested applications.

For windows running versions later that XP the Hyperterminal has been removed. An alternative Hyperterminal can be downloaded at this link:

http://www.kmtronic.com/hyperterminal-for-windows-7.html

When you save the “main.c” in SDK, this file is compiled and it generates an .elf file, for example if the name of the C project is “remote_robot” the name of the .elf is “remote_robot.elf”. The .elf file is found in the Debug folder, the path of which is shown in figure 66.

Figure 666: Path of the .elf file

When the C code of your MicroBlaze has been written, the next step is to generate a BitStream to implement in the FPGA. For generating this BitStream you have two possibilities:

1) Create Project Using the SDK (click on this icon: ) - Used for Hello_World and LED_Flash examples.Note: For this the Xilinx Software Adept will have to be installed, for further information on this consult the Document:

2) Create a PlanAhead project – Used for Remote_robot example.

Generating BitStream with PlanAhead is recommended. Go to Create a PlanAhead Project.

Create a PlanAhead ProjectWe have created an XPS system, written a C program and now want to generate a BitStream with PlanAhead. First create the following three folders as seen in Fig 67: ‘CommonFiles’, ‘ISEProject’, ‘sourceVHDL’ in your repository. Now open PlanAhead, create a new project, write a name and select the folder shown in figure 67.

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Figure 67: Save path for PlanAhead project

Don’t select “Create project subdirectory”. Click “Next”. Choose “RTL Project”, click “Next”.

Make sure ‘VHDL’ is chosen as the project language, as seen in Fig, 68

Figure 68: Choose VHDL

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Select the Spartan 6 used by NEXYS 3 board (sc6slx16csg324-3) and click “Next” and click “Finish”, the new project is generated, as seen in figure 69.

Figure 69: Choose part

It is important to add sources in the following order described below:

1 “name_project_stub.vhd”

2 Import your “system.xmp”

3 Import “name_system.ucf”

4 Import your “.elf”

Add the top level of the system. Click on “Add Sources” and select “Add or Create Design sources”, and click “Next”. Click on “Add Files” and choose this file “name_project_stub.vhd” (for us, “system_nexys3_stub.vhd”). The path is “XPS_Project\hdl\system_nexys3.vhd”, as seen in figure 70.

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Figure70: Add stub.vhd file

Click “Ok”, and then click “Finish”. A file from the XPS system is now imported. Click on “Add Source” and choose “Add or Create Embedded Sources”. Click “Next”, and then click on “Add Sub-Design” and select the system .xmp file created by XPS at the beginning. It is in the XPS_Project folder as seen in figure 71. Click “OK”, and then click “Finish”.

Figure71: Add an XPS system in PlanAhead

Next, import the .ucf constraint file. Click on “Add Sources”, choose “Add or Create Constraints”, and click “Next”. Click on “Add Files…” and find this file “name_system.ucf”. The path for the .ucf file is “XPS_Project\implementation\name_system.ucf” and shown in figure 72. Click “OK” and then click “Finish”. (Note, this may be found in the ‘data’ folder instead of ‘implementation).

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Figure 72: Add .ucf file

Next, add the .elf file. This file is generated by SDK software when saving the “main.c” file. Click on “Add Sources”, select “Add or Create Design Sources”, click “Next” and then click on “Add File”. Normally the “name_C_project.elf” file is found in “SDK_Project\name_C_project\Debug”, as seen in figure 73. Click “OK” and the click “Finish”.

Figure 73: Add .elf file

Next, associate the .elf file with the XPS system. Right-click on the system and choose “Associate ELF Files…” as seen in figure 74.

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Figure74: Open the “associate elf files..” menu

Click on the highlighted browse button as shown in figure 75.

Figure 75: Browse Menu for Associate .elf files

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A new window will appear, select the .elf file that you imported. This can be seen in figure 76. Click “OK”. Now click on the ‘mp_bootloop.elf’ of the Simulation Source, a pop-up window will appear, if the ‘remote_robot.elf’ file is not visible, click on ‘Add Elf Files…’ and select the same elf file as used previously and associate, now click “OK” again.

Figure 7668: Choose Imported .elf File

Next right-click on the source window( where the hierarchy of files is contained) and right-click and set ‘No Update, Manual Compile Order’ as seen in Figure 77.

Figure 77: Select ‘No Update, Manual Compile Order’

Then set your ‘stub’ file as top (right-click – ‘Set as Top’).

Now, generate a BitStream by clicking on the “Generate BitStream” button.

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Note: When generating bitstream you may need to disable your antivirus software as it may

Implementation in the BoardNext, implement the new MicroBlaze sytem with its program in the FPGA. Use the Digilent software “Adept” to implement these .bit file. Connect the programing cable and switch on the board. Open Adept.

If you have generated your .bit with plan ahead click on browse and choose this download.bit file: “PlanAhead\ISEProject\remote_robot\remote_robot.runs\impl_1\download.bit”. This other file: “PlanAhead\ISEProject\remote_robot\remote_robot.runs\impl_1\system_nexys3_stub.bit”only implements the MicroBlaze system. When you have chosen, click on program and your board is programming

Different linksFor several information on the MicroBlaze system go to: http://www.xilinx.com/ise/embedded/edk6_2docs/platform_studio_ug.pdf

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/edk_ctt.pdf

http://www.youtube.com/watch?v=rv_BYDPlwHo

http://www.youtube.com/watch?v=JarNp1nJhCw

For your help for creating or adding new peripheral component view these videos:

http://www.youtube.com/watch?v=STGiqlBRVms

http://www.youtube.com/watch?v=Veut_iOtTv0

http://www.youtube.com/watch?v=MbVwNGGzuxE

http://www.youtube.com/watch?v=MC1amstP_8A

http://www.youtube.com/watch?v=WYOQpqlEY94

http://www.youtube.com/watch?v=DkjVXeqRKjE

If you want another tutorial see:

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http://www.xilinx.com/ise/embedded/edk6_2docs/platform_studio_ug.pdf

It is the Xilinx tutorial. This tutorial explain how create a new MicroBlaze. But this tutorial used an old version of ISE (XPS and EDK). I think that the ISE version used in this tutorial, XPS and SDK it is one software.

The digilient note is available if you download “Nexys2 Board Support files for use with Xilinx EDK. Supports EDK 13 and up.” Nexys2 Board Support files for use with Xilinx EDK. Supports EDK 13 and up. Or “Nexys3 Board support files for EDK BSB wizard. Supports EDK 13.2-14.4 for both AXI and PLB buses” http://www.digilentinc.com/Data/Products/NEXYS3/Nexys3_BSB_Support_v_2_7.zip. This note explain how load the Digilent board library and the different adjustment possible with these boards.

http://www.smdp2vlsi.gov.in/smdp2vlsi/downloads/mb_tutorial.pdf

It another tutorial for create a news XPS project using the MicroBlaze. This tutorial used and old version of ISE. In this version, XPS and SDK it is one software.

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ListingsFigure 1: Repository Example........................................................................................................................4

Figure 2: XPS Start-Up Menu..........................................................................................................................5

Fig. 3: Create New XPS Project Window........................................................................................................6

Fig. 4: Configuration of Create New XPS Project window..............................................................................7

Fig. 5: Base System Builder Welcome Window..............................................................................................8

Fig. 6: Base System Builder Board Select Window.........................................................................................9

Fig. 7: Base System Builder System Window................................................................................................10

Fig. 8: Base System Builder Processor Window............................................................................................11

Fig. 9: Base System Builder Peripheral Window...........................................................................................12

Fig. 10: Configuration of Base System Builder Peripheral Window..............................................................13

Fig. 11: Base System Builder Cache Window................................................................................................14

Figure 12: Base System Builder Summary Window......................................................................................15

Fig. 13: XPS management MicroBlaze project..............................................................................................16

Fig. 14: Create and Import Peripheral Welcome Window............................................................................17

Fig. 15: Create and Import Peripheral, Peripheral Flow Window.................................................................18

Fig. 16: Create Peripheral, Repository or Project Window...........................................................................19

Fig. 17: Create Peripheral, Name and Version Window...............................................................................20

Fig. 18: Create Peripheral, Bus Interface Window.......................................................................................21

Fig. 19: Create Peripheral, IPIF (IP Interface) Services..................................................................................22

Fig. 20: Create Peripheral, Slave Interface Window.....................................................................................23

Fig. 21: Create Peripheral, User S/W Register..............................................................................................24

Fig. 22: Create Peripheral, IP Interconnect (IPIC) Windows.........................................................................25

Fig. 23: Create Peripheral, (OPTIONAL) Peripheral Simulation Support.......................................................26

Fig. 24: Create Peripheral, (OPTIONAL) Peripheral Implementation Support Window................................27

Fig. 25: Create Peripheral, Congratulation Window.....................................................................................28

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Fig. 26: Path to two new peripheral VHD files.............................................................................................29

Fig. 27: Declare the new external signal in the “user_logic.vhd”.................................................................29

Fig. 28: Declaration of the new external signal in the “user_logic.vhd”.......................................................30

Fig. 29: Declare the function with external signals in “user_logic.vhd”.......................................................30

Fig. 30: External signal allocation in “user_logic.vhd”..................................................................................31

Fig. 31: Declare new external signal in the “name_new_peripheral.vhd”...................................................32

Fig. 32: Adding New External Connection in Declaration.............................................................................33

Fig. 33: Add the New Signal Port Map..........................................................................................................33

Fig. 34: New Port Map in the “name_peripheral.vhd”.................................................................................34

Fig. 35: Path of the .mpd file........................................................................................................................35

Fig. 36: Added Modificationd to “name_new_peripheral.mpd”..................................................................36

Fig. 37: Rescan User Repositories................................................................................................................37

Fig. 38: Newly created IP..............................................................................................................................38

Fig. 39: Add IP Instance to Design Window..................................................................................................38

Fig. 40: XPS Core Config Window.................................................................................................................39

Fig. 41: Check if the peripheral is included..................................................................................................40

Fig. 42: Connect New Peripheral at the PLB Bus..........................................................................................40

Fig. 43: Address tabs with Generated Addresses.........................................................................................41

Fig. 44: XPS Port tabs, External Signals Not Connected................................................................................42

Fig. 45: Connection of the External Signal....................................................................................................42

Fig. 46: Open system .ucf file.......................................................................................................................43

Fig. 47: Name of pin.....................................................................................................................................43

Fig. 48: Modified .ucf File.............................................................................................................................44

Fig. 49: XPS BitStream is Generated.............................................................................................................45

Fig. 50: Export to SDK / Launch SDK.............................................................................................................46

Fig. 51: Workspace launcher SDK window...................................................................................................46

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Fig. 52: SDK window after the exportation..................................................................................................47

Fig. 53: XPS Design exported to SDK............................................................................................................48

Fig. 54: New file window in SDK. Chose Board Support Package.................................................................49

Fig. 55: New Board Support Package Project window.................................................................................50

Fig. 56: Board Support Package Settings window........................................................................................51

Fig. 57: SDK after the Board Support Package generation...........................................................................52

Fig. 58: New menu to create a new C project..............................................................................................53

Fig. 59: New Project Application Project window........................................................................................54

Fig. 60: New Project Templates window......................................................................................................55

Fig. 61: SDK software after the generation of a C project............................................................................56

Fig. 62 Path to Create a New C Source File..................................................................................................56

Fig. 63: New Source File Window.................................................................................................................57

Fig. 64: Blank main.c File..............................................................................................................................58

Fig. 65: main.c file returning 0.....................................................................................................................58

Fig. 66: Path of the .elf file...........................................................................................................................59

Fig. 67: Save path for PlanAhead project.....................................................................................................59

Fig. 68: Add stub.vhd file..............................................................................................................................60

Fig. 69: Add an XPS system in PlanAhead.....................................................................................................60

Fig. 70: Add .ucf file......................................................................................................................................61

Fig. 71: Add .elf file......................................................................................................................................61

Fig. 72: Open the “associate elf files..” menu..............................................................................................62

Fig. 73: Browse Menu for Associate .elf files................................................................................................62

Fig. 74: Choose Imported .elf File.................................................................................................................63

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Appendix

Hello_WorldAn application was developed in the SDK to output text onto the Uart. The example Hello World can be seen in listing 1 below.

Listing 1

LED_FlashThis application utilises several internal peripherals. A polling system is used to monitor the state of the switches. Once the switch is changed the value at the switch address is changed. This in turn causes the read in value to change. Note as the read in value is converted to an int, it is in the form of the power of 2 (1,2,4,8,16 etc), this causes the corresponding LED address to be accessed and light up. The 7 segment display is also displays the switch value. This is automatically decoded to be represented in Hexadecimal (1,2,3,4..D,E,F).

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/* * helloworld.c: simple test application * * Mark Hughes * 10/11/13 */

#include <stdio.h>#include "platform.h"int main(){

xil_printf("Hello World"); //Outputs text to Uart

return 0;}

Listing 2

Remote_ robotThe following listing details the example code for controlling the robotic arm.

/* main.c * * Created on: Mar 28, 2014 * Author: Florent Dordon

Modified by Mark Hughes */#include <stdio.h>#include "xgpio.h"#include "xparameters.h"#include "xil_io.h"#include "mb_interface.h" //Contains the functions for registering the interrupt controller with the MicroBlaze MP

#define ID_SW XPAR_DIP_SWITCHES_8BITS_BASEADDR#define ID_BP XPAR_PUSH_BUTTONS_4BITS_BASEADDR#define ID_LED XPAR_LEDS_8BITS_BASEADDR

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#include <stdio.h>#include "xgpio.h"#include "xparameters.h"#include "xil_io.h" //Input/Output interface for external pins and Uart#include "xintc.h" //Interrupt Controller API functions#include "mb_interface.h" //Contains the functions for registering the interrupt controller with the microblaze MP

// Define the memory address of the following peripherals#define ID_LED 0x81400000#define ID_SEG 0xcd600000#define ID_SW XPAR_DIP_SWITCHES_8BITS_BASEADDR

int main(){

xil_printf("FPGA Running\n");int sw;

while(1){sw = Xil_In32(ID_SW); //Reads in the state of switches and assigns

it to an int ‘sw’

Xil_Out32(ID_LED,sw); //Outputs the int ‘sw’ to the LEDsXil_Out32(ID_SEG,sw); //Outputs the int ‘sw’ to the 7 seg display

Xil_printf("\nSw Value: %d\n",sw); //Prints the value of the switch after

each loop iteration.

}return 0;

}

#define ID_ROBOT 0xCE800000+0xC //XPAR_IP_DRIVE_ROBOT_0_BASEADDR+offset register 1

#define M5 10 //mask right+left push at the same time#define RIGHT 8 //mask right is push#define LEFT 2 //mask left is push#define CMD_BIT_M5 0xFF3FFFFF //mask that isolates(sets to 0) the 2 bits of command mot 5#define CMD_RIGHT 0x00400000 //configuration for M5 right#define CMD_LEFT 0X00800000 //configuration for M5 left#define STOP_M5 0x00000000 //configuration for M5 STOP

#define M4 5 //mask M4#define UP_M4 1 //mask M4 Up#define DOWN_M4 4 //mask M4 Down#define CMD_BIT_M4 0xFCFFFFFF //mask that isolates(sets to 0) the 2 bits of command mot 4#define CMD_M4_UP 0x01000000 //configuration for M4 Up#define CMD_M4_DOWN 0X02000000 //configuration for M4 Down#define STOP_M4 0x00000000 //configuration for M4 Stop

#define M3 3 //mask command M3 (SW0 and SW1)#define UP_M3 1 //mask M3 Up (SW0 = 1)#define DOWN_M3 2 //mask M3 down (SW1 = 1)#define CMD_BIT_M3 0xF3FFFFFF //mask that isolates (sets to 0) the 2 bits of commande mot 3#define CMD_M3_UP 0x04000000 //configuration for M3 Up#define CMD_M3_DOWN 0X08000000 //configuration for M3 Down#define STOP_M3 0x00000000 //configuration for M3 Stop

#define M2 12 //mask command M2 (SW2 and SW3)#define UP_M2 4 //mask M2 Up (SW2 = 1)#define DOWN_M2 8 //mask M2 down (SW3 =1)#define CMD_BIT_M2 0xCFFFFFFF //mask that isolates(sets to 0) the 2 bits of command mot 2#define CMD_M2_UP 0x10000000 //configuration for M2 Up#define CMD_M2_DOWN 0X20000000 //configuration for M2 Down#define STOP_M2 0x00000000 //configuration for M2 Stop

#define M1 0b110000 //mask commande M1 (SW4 and SW5)#define TAKE_M1 0b010000 //mask M1 take (SW4 = 1)#define RELEASE_M1 0b100000 //mask M1 release (SW5 = 1)#define CMD_BIT_M1 0x3FFFFFFF //mask that isolates (sets to 0) the 2 bits of command mot 1#define CMD_TAKE 0x40000000 //configuration for M1 take#define CMD_RELEASE 0X80000000 //configuration for M1 release#define STOP_M1 0x00000000 //configuration for M1 STOP

#define LED_ROBOT 0b1000000 //mask command LED_ROBOT (SW6)#define BIT_LED_ROBOT 0xFFDFFFFF#define LED_ROBOT_ON 0x00200000#define LED_ROBOT_OFF 0x00000000

#define CMD_STOP_ALL 0X000FFFFF

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#define STOP_ALL 0x00000000

int main(){xil_printf("\n\rWelcome Remote Robotic Arm\n\r");int btn;int sw;long int command;int sel_M5;int sel_M4;int sel_M3;int sel_M2;int sel_M1;int sel_LED_ROBOT;long int var_M1;long int var_M2;long int var_M3;long int var_M4;long int var_M5;long int var_led_robot;long int stopall;

while(1){

btn=Xil_In32(ID_BP);sw =Xil_In32(ID_SW);Xil_Out32(ID_LED,sw);//xil_printf("%d",btn);

/* * Command motor 5 (Grasper Motor) * If Button Left pressed, grasps/takes * If Button Left pressed, releases/opens * If Buttons not pressed, robot stops. */sel_M5=(btn&M5);xil_printf("M5=%d ",sel_M5);if (sel_M5!=M5){//Button Left

if ((sel_M5&RIGHT)==RIGHT){

var_M5=command&CMD_BIT_M5;command=var_M5|CMD_RIGHT;xil_printf("M1_TAKE ");

}//Button Rightif ((sel_M5&LEFT)==LEFT){

var_M5=command&CMD_BIT_M5;command=var_M5|CMD_LEFT;xil_printf("M1_RELEASE ");

}}else{

var_M5=command&CMD_BIT_M5;

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command=var_M5|STOP_M5;xil_printf("M5_stop ");

}/* * Command motor 4 (Wrist Motor) * If Button down pressed, wrist moves up * If Button up pressed, wrist moves down * If Buttons not pressed, robot stops. */sel_M4=(btn&M4);xil_printf("M4=%d ",sel_M4);if(sel_M4!=M4){//Button down

if ((sel_M4&DOWN_M4)==DOWN_M4){

var_M4=command&CMD_BIT_M4;command=var_M4|CMD_M4_DOWN;xil_printf("M4_DOWN ");

}//Button Upif ((sel_M4&UP_M4)==UP_M4){

var_M4=command&CMD_BIT_M4;command=var_M4|CMD_M4_UP;xil_printf("M4_UP ");

}}else{

var_M4=command&CMD_BIT_M4;command=var_M4|STOP_M4;xil_printf("M4_stop ");

}/* * Command motor 3 (Elbow Motor) * If Switch 0 on, elbow moves up, * If Switch 1 on, elbow moves down, * If Switches off, robot stops. */sel_M3=(sw&M3);xil_printf("M3=%d ",sel_M3);if(sel_M3!=M3){//Switch 1

if ((sel_M3&DOWN_M3)==DOWN_M3){

var_M3=command&CMD_BIT_M3;command=var_M3|CMD_M3_DOWN;xil_printf("M3_DOWN ");

}//Switch 0if ((sel_M3&UP_M3)==UP_M3){

var_M3=command&CMD_BIT_M3;command=var_M3|CMD_M3_UP;xil_printf("M3_UP ");

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}}else{

var_M3=command&CMD_BIT_M3;command=var_M3|STOP_M3;xil_printf("M3_stop ");

}/* * Command motor 2 (Shoulder Motor) * If Switch 2 on, shoulder moves up, * If Switch 3 on, shoulder moves down, * If Switches off, robot stops. */sel_M2=(sw&M2);xil_printf("M2=%d ",sel_M2);if(sel_M2!=M2){//Switch 3

if ((sel_M2&DOWN_M2)==DOWN_M2){

var_M2=command&CMD_BIT_M2;command=var_M2|CMD_M2_DOWN;xil_printf("M2_DOWN ");

}//Switch 2if ((sel_M2&UP_M2)==UP_M2){

var_M2=command&CMD_BIT_M2;command=var_M2|CMD_M2_UP;xil_printf("M2_UP ");

}}else{

var_M2=command&CMD_BIT_M2;command=var_M2|STOP_M2;xil_printf("M2_stop ");

}/* * Command motor 1 (Base/Waist Motor) * If Switch 4 on, waist turns left, * If Switch 5 on, waist turns right, * If Switches off, robot stops. */sel_M1=(sw&M1);xil_printf("M1=%d ",sel_M1);if(sel_M1!=M1){//Switch 4

if ((sel_M1&TAKE_M1)==TAKE_M1){

var_M1=command&CMD_BIT_M1;command=var_M1|CMD_TAKE;xil_printf("Right ");

}//Switch 5

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if ((sel_M1&RELEASE_M1)==RELEASE_M1){

var_M1=command&CMD_BIT_M1;command=var_M1|CMD_RELEASE;xil_printf("Left ");

}}else{

var_M1=command&CMD_BIT_M1;command=var_M1|STOP_M1;xil_printf("M1_stop ");

}/* * Command LED ROBOT * Switch 6 open, LED ROBOT ON * Switch 6 close, LED ROBOT OFF */sel_LED_ROBOT=(sw&LED_ROBOT);xil_printf("LED ROBOT=%d ",sel_LED_ROBOT);//Switch 6if(sel_LED_ROBOT!=LED_ROBOT){

var_led_robot=command&BIT_LED_ROBOT;command=var_led_robot|LED_ROBOT_OFF;xil_printf("led robot off ");

}else{

var_led_robot=command&BIT_LED_ROBOT;command=var_led_robot|LED_ROBOT_ON;xil_printf("led robot on");

}/* * If no choice all system is stop */if((btn|sw)==0){

stopall=command&CMD_STOP_ALL;command=stopall|STOP_ALL;xil_printf("ALL_STOP");

}else{

xil_printf(" ");}xil_printf("\r");/* * Send command on the ROBOT */Xil_Out32(ID_ROBOT,command);//Xil_Out32(ID_ROBOT,0x80000000);

}return 0;

}

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