Speaker : Utku Özcan ASIC Designer, R&D, Netaş, Turkey

Speaker:Utku Özcan

ASIC Designer, R&D, Netaş, Turkey

Designers:Utku Özcan,ASIC Designer

İsmail Hakkı Topçu, Hardware DesignerÖmer Aydın, Senior System Engineer{ozcan, topcu, aydin}@netas.com.tr

A Novel Parametric ATM Adaptation Layer 1Bridging Between PCM and ATM

Utku Özcan3/11/1999

ICSPAT’99

A Novel Parametric AAL1 Bridging Between PCM and ATM

ATM (Asynchronous Transfer Mode):A most recent network technology

- voice, image and data transfer on the same network- support of users with different features- support high transfer rates between end users

ATM network

ATM (Asynchronous Transfer Mode)


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User information is carried in 53 byte packetscalled ATM cells on an ATM network

- user information acquired in 53 byte packets On the Transmitter - packets reassembled and sent to users On the Receiver

ATM (Asynchronous Transfer Mode)


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ATM Cell

ATM cell payload (47 bytes) AAL1 Header(1 byte)

ATM Header(5 bytes)

Network element

Network element


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End users described by QoS (Quality of Service) On ATM

Users tell the network what kind of transfer will existNetwork will be programmed for best performance

according to this set of information

QoS 1

QoS 2

Preparation of ATM to the users


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ATM Network General Architecture

Physical Layer(PHY)

ATM Layer(ATM)

AAL Layer(AAL)

Physical Layer(PHY)

ATM Layer(ATM)

AAL Layer(AAL)

AAL userAAL user

An ATM network is implemented mostly as hardwareAAL users are implemented mostly as software


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Basic QoS typesCBR (Constant Bit Rate)VBR (Variable Bit Rate)

Some of QoS data carried in ATM Header

GFC VPI

VPI VCI

VCI

VCI PTI CLP

HEC

AAL1 Header

ATM cell payload byte 1

...

...



0347

QoS List

ATM QoS types


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AALATM Adaptation Layer

It serves as an interface between the users and the ATM network

5 different types of AAL are defined in ITU-T Standarts

Most common AAL1 typesAAL1: used in CBR type QoS (e.g. POTS)AAL5: used in VBR type QoS (e.g. Internet)

AAL1 AAL5

ATM Adaptation Layer


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AAL1ATM Adaptation Layer 1

- a connection based layer protocol- support to conventional phone networks

- numerous researches on AAL1

- realtime voice or image transmission- ISDN network on ATM network

ATM Adaptation Layer 1 (AAL1)


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ISDN facility on ATM

Physical Layer(PHY)

ATM Layer(ATM)

AAL Layer(AAL)

ISDN Terminal

Physical Layer(PHY)

ATM Layer(ATM)

AAL Layer(AAL)

ISDN Terminal

Support of 64 kbps voice traffic: ISDN over ATMResult: ISDN uses ATM advantages


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ISDN Rate Adaption and AAL1

ISDN supports users with 64 kbps rateToday, most users have a bandwidth of lower than 64 kbps

Rate adaption necessity:ITU-T X.30/V.110 standards

All state-of-the-art AAL1 applications support new systemsSupport of old systems: X.30/V.110 feature in AAL1

Conventional AAL1 ?


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NETAAL1: Netaş’ AAL1 Solution

NETAAL1 Netaş AAL1 Solution- support to every kind of user

- ISDN compatibility- user variety

taking advantage of ATM

Our AAL1


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General Architecture of AAL1

AAL1 user data

ConvergenceSublayer

Segmentation &Reassembly

sublayer

AAL1 PDU (48 bytes)

AAL1 user data

AAL1 PDU(48 bytes)

ATM Layer ATM Layer

AAL1 Header Calculator

... CSIoutput

SC Output

47 bytes

1 bit 3 bits

1 byte

...

AAL1 Header Correction-Detection

CSIAnalysis

SC Analysis

1 bit 3 bits

1 byte47

bytes

Transmitterside

Receiverside


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Main Functions of AAL1

Convergence Sublayer, CSTransmitter Side:

- acquires user data in 47 byte packets- assigns a Sequence Count, SC for every 47 byte packet

- prepares Convergence Sublayer Indication (CSI)Receiver Side:

- sends 47 byte packets to the user- analyzes the sequence of 47 byte packets

- analyzes timing information (CSI)

Segmentation and Reassembly sublayer, SARTransmitter Side:

generates AAL1 packet from SC, CSI and 47 byte packets and sends itReceiver Side:

- divides AAL1 packet into SC, CSI and 47byte packets


ICSPAT’99


NETAAL1 General Configuration

4 x 2.048 Mbps PCM Bus 4 x 2.048 Mbps PCM Bus

10 Mbps ATMBus 10 Mbps ATM Bus

TransmitPointerRAM

TransmitPayload

RAM

ReceivePointerRAM

ReceivePayload

RAM

NETAAL1

CPU


ICSPAT’99


Transmit side of NETAAL1

Transmit PCM Bus

Transmit Parametric Algorithm

Transmit Static

Parameter Table

CPU

Transmit Dynamic

Parameter Table

Transmit Pointer RAM

Transmit Payload

RAM

address

data

address

data

Transmit Payload

Flag RAM

Transmit SAR

Scheduler Unit

AAL1 Header

Generator

Transmit ATM Bus Interface

TransmitATM Bus

CS SAR


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Transmit NETAAL1 CS

Nth channeltimeslot

PCM Frame (125 μs.)

Nth channeltimeslot


......

...

Mth X.30/V.110 Frame M+1th X.30/V.110 Frame

TransmitPointer Table

byte bitFlag

byte

bitAAL1Header

ATMHeader

Payload Locationfor the Nth channel

on the Transmit Side(in Payload RAM)

30th bit ofX.30/V.110 frame

Pointer Groupfor M+1th

X.30/V.110frame

(80 Pointers)

time


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Transmit NETAAL1 SAR

PayloadFlagRAM

Payload Ready

Transmit SARScheduler Unit

address

data

SC RAM

PayloadFlag of

Nth channel

Transmit Payload

RAM

AAL1 Header

Generator

ATM BusInterface

ATM Bus

N = N + 1

Nth Channel Payload Ready?

Prepare AAL1 Header of Nth

Channel

Send Payload of Nth Channel

to ATM Bus Interface

SC = SC + 1


ICSPAT’99


Receive Side of NETAAL1

Receive ATM Bus Interface

Receive Look Up

Table

Receive SNP/SN Analyzer

Receive ATM Bus

Receive Payload

Flag RAM

Receive Payload

RAM

Receive Parametric Algorithm

Receive Pointer Table

Receive Static

Parameter Table

CPU

Receive Dynamic

Parameter Table

Receive PCM Bus

data

data

address

address

SAR CS


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Receive NETAAL1 SAR

ATM BusInterface

ATM Bus

VPI VCI

ReceiveLook Up

Table

Nth address

AAL1 HeaderSNP ErrorDetection-Correction

AAL1 HeaderSN

Analyzer

ATM CellFilter

ReceivePayload RAM

ReceivePayload

Flag RAM

Payload Ready

Payload Flag of Nth

Channel


ICSPAT’99


Receive NETAAL1 CS

Nth channeltimeslot


Nth channeltimeslot


......

...

Mth X.30/V.110 Frame M+1th X.30/V.110 Frame

ReceivePointer Table

byte bitFlag

byte

bitAAL1Header

ATMHeader

Payload Locationfor the Nth channelon the Receive Side(in Payload RAM)

30th bit ofX.30/V.110 frame

Pointer Groupfor M+1th

X.30/V.110frame

(80 Pointers)

time


ICSPAT’99


Design Technology

NETAAL1 implemented as a digital integrated circuitdesigned with Verilog Hardware Description Language

(Verilog HDL)100.000 lines of Verilog and C code in 5 months

always @(posedge clock)

begin

out_reg <= in_reg;

end

in_reg

clock

out_reg

Flip-Flop Model

FF


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Minimal CPU time statistics of postroute simulations for 4 cell transmission of the Transmit AAL1

Static Timing Analysis is mandatory for this

complexity

Design Environment Statistics


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Parametric synthesis results of Transmit NETAAL1


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Placement&Routing statistics of Transmit NETAAL1: Sept 1st - 30th, 1999


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Parametric synthesis results of Receive NETAAL1


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Placement&Routing statistics of Receive NETAAL1: Sept 1st - 10th, 1999


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NETAAL1 has been implemented withTop-Down Design Flow

DesignEntry

Synthesis P&R

always @(posedge clock)

out_reg <= in_reg;

Verify Verify Verify

comparison

Automatedverification

environment

chip

Design Technology

out_regin_reg

clock


ICSPAT’99


Design Technology

TransmitNETAAL1

ReceiveNETAAL1

CPU Simulation

Model

PCM Bus Simulation

Model

ATM Bus Simulation

Model

RAM Simulation

Models

RAM Simulation

Models

open_aal1_connection (<chip>, <pcm>, <ts>, <vpi>, <vci>);

Internal monitors &

cell file dumpers

Internal monitors &

cell file dumpers

Testvector generators

C Interfaces to external

tools

Verilog and C based Automated Verification Environment

Macro Behavioral

Model Generators

Simulation mode check


ICSPAT’99


Transmit NETAAL1implemented in XC40150XV

Receive NETAAL1implemented in XC40150XV

NETAAL1 implemented inField Programmable Gate Arrays (FPGA) of Xilinx

transistor count ca. 1.000.000

Design Technology

Speaker : Utku Özcan ASIC Designer, R&D, Netaş, Turkey

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Transcript of Speaker : Utku Özcan ASIC Designer, R&D, Netaş, Turkey