Sima Dezs

Tbbmagos/sokmagos processzorok-22013 OktberVersion 1.2

ttekints1. Tbbmagos processzorok megjelensnek szksgszersge 2. Homogn tbbmagos processzorok 3. Heterogn tbbmagos processzorok 2.1 Hagyomnyos tbbmagos processzorok 3.1 Mester/szolga elv tbbmagos processzorok 3.2 Csatolt tbbmagos processzorok 4. Kitekints 2.2 Sokmagos processzorok

3. Heterogn tbbmagos processzorok

3. Heterogn tbbmagos processzorok (1)3.1 bra Tbbmagos processzorok fbb osztlyaiDesktopsHeterogenous multicoresHomogenous multicores Multicore processorsManycore processorsServerswith >8 coresConventionalMC processorsMaster/slavearchitecturesAdd-onarchitectures2 n 8 coresGeneral purpose computingPrototypes/ experimental systemsMM/3D/HPCproduction stageHPCnear future

3.1 Heterogn tbbmagos mester/szolga elv TP-ok A Cell processzor

3.1 Heterogn mester/szolga elv TP-ok - A Cell (1)Cell BE Elzmnyek:2000 nyara:Az architektra alapjainak meghatrozsa02/2006: Cell Blade QS2008/ 2007 Cell Blade QS2105/ 2008 Cell Blade QS22 Sony, IBM s Toshiba kzs termke Cl: Jtkok/multimdia, HPC alkalmazsokPlaystation 3 (PS3)QS2x Blade Szerver csald(2 Cell BE/blade)

EIB: Element Interface Bus 3.1.1 bra: A Cell BE blokk diagramja [1]SPE: Synergistic Procesing ElementSPU: Synergistic Processor UnitSXU: Synergistic Execution UnitLS: Local Store of 256 KBSMF: Synergistic Mem. Flow UnitPPE: Power Processing ElementPPU: Power Processing UnitPXU: POWER Execution UnitMIC: Memory Interface Contr.BIC: Bus Interface Contr.XDR: Rambus DRAM3.1 Heterogn mester/szolga elv TP-ok - A Cell (2)

3.1.2 bra: A Cell BE lapka (221mm2, 234 mtrs) [1]3.1 Heterogn mester/szolga elv TP-ok - A Cell (3)

3.1.3 bra: A Cell BE lapka EIB [1]3.1 Heterogn mester/szolga elv TP-ok - A Cell (4)

3.1.4 bra: Az EIB mkdsi elve [1]3.1 Heterogn mester/szolga elv TP-ok - A Cell (5)

3.1.5 bra: Konkurens tvitelek az EIB-en [1]3.1 Heterogn mester/szolga elv TP-ok - A Cell (6)

Plda egy komplex alkalmazs futtatsa (digitlis TV dekdolsa) a Cell processzoron [2]3.1 Heterogn mester/szolga elv TP-ok - A Cell (7)

Teljestmny @ 3.2 GHz:QS21 Cscs SP FP: 409,6 GFlops (3.2 GHz x 2x8 SPE x 2x4 SP FP/cycle) Cell BE - NIK2007: Faculty Award (Cell 3 app./Teaching)2008: IBM NIK Kutatsi Egyttmkdsi Szerzds: Teljestmnyvizsglatok IBM Bblingen Lab IBM Austin Lab3.1 Heterogn mester/szolga elv TP-ok - A Cell (8)A Cell teljestmnye s a NIK rszvtele a Cell teljestmny-vizsglataiban

The Roadrunner6/2008 : International Supercomputing Conference, DresdenA vilg 500 leggyorsabb szmtgpe listjn (Top500): 1. Roadrunner1 Petaflops (1015) fenntartott teljestmny (Linpack)3.1 Heterogn mester/szolga elv TP-ok - A Cell (9)

3.1.6 bra:A vilg leggyorsabb szmtgpe: IBM Roadrunner (Los Alamos 2008) [3]3.1 Heterogn mester/szolga elv TP-ok - A Cell (10)

3.1.7 bra: A Roadrunner fbb jellemzi [1]3.1 Heterogn mester/szolga elv TP-ok - A Cell (11)

3.2 Heterogn csatolt tbbmagos processzorok

3.2.1 bra: Tbbmagos processzorok fbb jellemziDesktopsHeterogenous multicoresHomogenous multicores Multicore processorsManycore processorsServerswith >8 coresConventionalMC processorsMaster/slavearchitecturesAdd-onarchitectures2 n 8 coresGeneral purpose computingPrototypes/ experimental systemsMM/3D/HPCproduction stageHPCnear future3.2 Heterogn csatolt tbbmagos processzorok (1)

kernel0()kernel1()HostDeviceCsatolt elv vgrehajts elve GPGPU-k esetn (a legegyszerbb (ktegelt) szervezst felttelezve) [4]3.2 Heterogn csatolt tbbmagos processzorok (2)(Adatprh. progr.)

Heterogn csatolt tbbmagos processzorok: feldolgozs gyorstk (accelerators) A mkdsi elv szempontjbl elzmny: heterogn csatolt trsprocesszoros rendszerekPldk: korai szemlyi szmtgpek lebegpontos trsprocesszorokkal Intel 286 + 287 386 + 387 Az Intel 486-nak mr volt sajt on-chip lebegpontos egysge (FPU) (az SX s SL modelek kivtelvel)Megjegyzs a mkdsi elvhez3.2 Heterogn csatolt tbbmagos processzorok (3)

Heterogn csatolt tbbmagos processzorok legfontosabb implementciiHeterogn csatolt tbbmagos processzorok Integrlt grafikaOkostelefonok/tblagpek3.2 Heterogn csatolt tbbmagos processzorok (4)

3.2.1 Az Integrlt grafika megjelense

3.2.1 Az Integrlt grafika megjelense (1)ttrs angol nyelv slide-ok hasznlatra

Implementation of integrated graphicsImplementations about1999 - 2009In the north bridgeOn the processor dieIn a multi-chip processor package on a separate die Both the CPU and the GPU are on separate diesand are mounted into a single packageIntels Havendale (DT) andAuburndale (M) (scheduled for 1H/2009 but cancelled)Arrandale (DT, 1/2010) andClarkdale (M, 1/2010) Implementation of integrated graphicsIntels Sandy Bridge (1/2011) andIvy Bridge (4/2012)AMDs Swift (scheduled for 2009but canceled)AMDs Bobcat-based APUs (M, 1/2011)Llano APUs (DT, 6/2011)Trinity APUs (DT, Q4/2012)3.2.1 Az Integrlt grafika megjelense (2)

Implementation of integrated graphicsImplementations about1999 - 2009In the north bridgeOn the processor dieIn a multi-chip processor package on a separate die Both the CPU and the GPU are on separate diesand are mounted into a single packageIntels Havendale (DT) andAuburndale (M) (scheduled for 1H/2009 but cancelled)Arrandale (DT, 1/2010) andClarkdale (M, 1/2010) Implementation of integrated graphicsIntels Sandy Bridge (1/2011) andIvy Bridge (4/2012)AMDs Swift (scheduled for 2009but canceled)AMDs Bobcat-based APUs (M, 1/2011)Llano APUs (DT, 6/2011)Trinity APUs (DT, Q4/2012)3.2.1 Az Integrlt grafika megjelense (3)

Example 1: Intels Havendale (DT) and Auburndale (M) multi-chip CPU/GPU processor plans [5] Revealed in 9/2007. Scheduled for 1H/2009 but cancelled about 1/2009. Both parts were based on the 2. gen. Nehalem (Lynnfield) architecture (45 nm), as shown below.Same LGA 1160 platformSchedule: 2H 08 First Samples1H 09 ProductionTDP < 95 W3.2.1 Az Integrlt grafika megjelense (4)

Example 2: Intels Westmere-EP based multi-chip CPU/GPU processors (2010)-1 [6]Clarkdale (desktop)Arrandale (mobile)3.2.1 Az Integrlt grafika megjelense (5)

Positioning of Clarkdale (DT) and Arrandale (M) in Intels roadmap [7]3.2.1 Az Integrlt grafika megjelense (6)

Single PCH for Intels Westmere-EP based multi-chip CPU/GPU processors (2010) [7] PCH(Peripheral Control Hub)3.2.1 Az Integrlt grafika megjelense (7)

Removing integrated graphics (IGFX) from the north bridge to the processor [7](Dedicated graphicsvia graphics card)3.2.1 Az Integrlt grafika megjelense (8)(Dedicated graphicsvia graphics card)

Removing integrated graphics (IGFX) from the north bridge to the processor [7](Dedicated graphicsvia graphics card)3.2.1 Az Integrlt grafika megjelense (8a)(Dedicated graphicsvia graphics card)

Removing integrated graphics (IGFX) from the north bridge to the processor [7](Dedicated graphicsvia graphics card)3.2.1 Az Integrlt grafika megjelense (8b)(Dedicated graphicsvia graphics card)

Implementation of integrated graphicsImplementations around1999 - 2009In the north bridgeOn the processor dieIntels Sandy Bridge (1/2011) andIvy Bridge (4/2012)AMDs Swift (scheduled for 2009)AMDs Bobcat-based APUs (M, 1/2011) andLlano APUs (DT, 6/2011)Trinity APUs (DT, Q4/2012)In a multi-chip processor package on a separate dieBoth the CPU and the GPUare on separate diesand are mounted into a single packageImplementation of commercial graphics on the processor die Intels Havendale (DT) andAuburndale (M) (scheduled for 1H/2009 but cancelled)Arrandale (DT, 1/2010) andClarkdale (M, 1/2010) 3.2.1 Az Integrlt grafika megjelense (9)

3.2.2 Intels Sandy Bridge

Key microarchitecture features of the Sandy Bridge vs the Nehalem 3.2.2 Intels Sandy Bridge [8]3.2.2 Intels Sandy Bridge (1)

Die plot of the 4C Sandy Bridge processor [9] Sandy Bridge 4C32 nm995 mtrs/216 mm2 MB L2/C8 MB L33.2.2 Intels Sandy Bridge (2)

Core i3-21xx, 2C, 2/2011 Core i5-23xx/24xx/25xx, 4C, 1/2011Core i7-26xx, 4C, 1/2011 Intel 6 series PCH11Except P67 that does not provide a display controller in the PCHBlock diagram of Intels Sandy Bridge with 6 Series PCH [10]3.2.2 Intels Sandy Bridge (3)

3.2.3 Intels Ivy Bridge

Key microarchitecture features of the Ivy Bridge vs the Sandy Bridge 3.2.3 Intels Ivy Bridge [11]3.2.3 Intels Ivy Bridge (1)

Ivy Bridge-DTSandy Bridge-DT22 nm 1480 mtrs160 mm232 nm995 mtrs216 mm2Contrasting the die plots of Ivy Bridge vs. Sandy Bridge (at the same feature size)-1 [12]3.2.3 Intels Ivy Bridge (2)

NoteIn the Ivy Bridge Intel devoted much more emphasis to graphics processing than in the Sandy Bridge to compete with AMDs graphics superiority.Contrasting the die plots of Ivy Bridge vs Sandy Bridge (at the same feature size)-2 [12]3.2.3 Intels Ivy Bridge (3)

3.2.4 AMDs Swift Fusion APU plan

3.2.4 AMDs Swift Fusion APU planPreliminariesIn 10/2006 AMD acquired the graphics firm ATI and at the same day they announced thatAMD plans to create a new class of x86 processors that integrate the central processing unit (CPU) and graphics processing unit (GPU) at the silicon level, codenamed Fusion [13].RemarkAlthough in the above statement AMD designated the silicon level integration of the CPU and GPU as the Fusion initiative, in some other publications they call both the package level and the silicon level integration of the CPU and GPU as the Fusion technology, as shown in the next figure [14] 3.2.4 AMDs Swift Fusion APU plan (1)

Extended interpretation of the term Fusion technology in some AMD publications [14] Despite this disambiguation, subsequently AMD understood the term Fusion usually as the silicon level integration of the CPU and the GPU.3.2.4 AMDs Swift Fusion APU plan (2)

In 12/2007 at their Financial Analyst Day AMD gave birth to a new term by designating their processors implementing the Fusion concept as APUs (Accelerated Processing Units). At the same time AMD announced their first APU family called the Swift family [15] as well. 3.2.4 AMDs Swift Fusion APU plan (3)

In 11/2008 again at their Financial Analyst Day AMD postponed the introduction of Fusion-based APU processors until the company transitions to the 32 nm technology [16] [17].3.2.4 AMDs Swift Fusion APU plan (4)No Swift APU!

This is a similar move as done by Intel with their 45 nm Havendale (DT) and Auburndale (M) in-package integrated multi-chip CPU+GPU projects. As leaked from industry sources in 1/2009 Intel canceled their 45 nm multi-chip processor plans in favor of 32-nm multi-chip processors to be introduced in Q1/2010 [18].Remark3.2.4 AMDs Swift Fusion APU plan (5)

3.2.5 AMDs K12 (Llano)-based APU lines

3.2.5 AMDs K12 (Llano)-based APU lines (1)3.2.5 AMDs Llano-based APU lines [19] Introduced: 6/2011. The Llano line belongs to the Fusion APU (Accelerated Processing Unit) series as it includes beyond a number of CPUs also a GPU to accelerate vision computing (graphics and media). Processors of the Llano lines have up to 4 CPU cores and a GPU. Nevertheless, AMD sells Llano based desktop lines as well with disabled GPUs. These lines are branded as Athlon II X4/X2 or Sempron lines. 32 nm technology, 228 mm2, 1450 mtrs.

Die plot of the Llano processor [20]3.2.5 AMDs K12 (Llano)-based APU lines (2)

Example: AMDs Llano-based A-series mobile lines [21]3.2.5 AMDs K12 (Llano)-based APU lines (3)

Conceptual difference between AMDs Fusion APUs and Intels Sandy Bridge CPUs [22]3.2.5 AMDs K12 (Llano)-based APU lines (4)

AMDs Llano APU processor with the A75 FCH [23] Lynx platformFCH: Fusion Control Hub3.2.5 AMDs K12 (Llano)-based APU lines (5)

3.2.6 AMDs Piledriver-based Trinity desktop APU line

3.2.6 AMDs Piledriver-based Trinity desktop APU line Announced in 6/2012Launched: 10/2012The Trinity APU is based on the Piledriver Compute Module, which is a redesign of the ill fated Bulldozer Compute Module.3.2.6 AMDs Piledriver-based Trinity desktop APU line (1)32 nm feature size, 226 mm2, 1.303 billion transistors (almost the same figures as for Lliano)

The Piledriver Compute Module of Trinity [24] 3.2.6 AMDs Piledriver-based Trinity desktop APU line (2)

AMDs Trinity die [29] 2 Piledriver modules (4 cores) GPU32 nm226 mm21.303 billion transistors 3.2.6 AMDs Piledriver-based Trinity desktop APU line (3)

Comparing die areas devoted to cores and graphics in AMDs Llano and Trinity []http://www.tomshardware.com/reviews/a10-4600m-trinity-piledriver,3202-4.html3.2.6 AMDs Piledriver-based Trinity desktop APU line (4)Quad coresDual modules (quad cores)32 nm226 mm21.303 billion transistors 32 nm228 mm21.450 billion transistors

The Comal platform that incorporates the (Piledriver-based) Trinity APU and the A70M PCH [26]3.2.6 AMDs Piledriver-based Trinity desktop APU line (6)

3.2.7 Okostelefonok, tblagpek

3.2.7 Okostelefonok, tblagpek

Ld. ksbb kln fejezetknt.

4. Kitekints

4. Kitekints (1)Kitekints Heterogenous multicoresMaster/slavearchitecturesAdd-onarchitectures4.1 bra: Hetererogn tbbmagos processzorok vrhat fejldseTbb CPUTbb gyorst

Referencik

[1]: Wright C., Henning P., Bergen B., Roadrunner Tutorial, An Introduction to Roadrunner, and the Cell Processor, Febr. 7 2008, http://www.lanl.gov/orgs/hpc/roadrunner/pdfs/Roadrunner-tutorial-session-1-web1.pdfReferences (1)[3]: Ricker T., World's fastest: IBM's Roadrunner supercomputer breaks petaflop barrier using Cell and Opteron processors, Engadget, June 9 2008, http://www.engadget.com/2008/ 06/09/worlds-fastest-ibms-roadrunner-supercomputer-breaks-petaflop/[4]: NVIDIA CUDA Compute Unified Device Architecture, Programming Guide, Version 1.1, Nov. 29 2007, http://moss.csc.ncsu.edu/~mueller/cluster/nvidia/1.1/NVIDIA_CUDA_ Programming_Guide_1.1.pdf[5]: RS Intel 2009 Desktop Platform Overview, Sept. 2007, http://pic.xfastest.com/z/INTEL%202009%20%20Overview/2009Overview.ppt[2]: Blachford N., Cell Architecture Explained, v.02, 2005, http://www.blachford.info/computer/Cell/Cell2_v2.html[6]: Smith S.L., Intel Roadmap Overview, IDF 2009, Sept. 22 2009, http://download.intel.com/pressroom/kits/events/idffall_2009/pdfs/IDF_SSmith_Briefing.pdf[7]: Smith S.L., 32nm Westmere Family of Processors, 2009, http://download.intel.com/pressroom/kits/32nm/westmere/32nm_WSM_Press.pdf[8]: Kahn O., Piazza T., Valentine B.: Technology Insight: Intel Next Generation Microarchitecture Codename Sandy Bridge, IDF 2010, extreme.pcgameshardware.de/.../281270d1288260884- bonusmaterial-pc- games-hardware-12-2010-sf10_spcs001_100.pdf

[9]: Intel Sandy Bridge Review, Bit-tech, Jan. 3 2011, http://www.bit-tech.net/hardware/cpus/2011/01/03/intel-sandy-bridge-review/1References (2)[11]: George V., Piazza T., Jiang H., Technology Insight: Intel Next Generation Microarchitecture, Codename Ivy Bridge, IDF 2011, SPCS005[12]: Athow D., Picture : Ivy Bridge vs Sandy Bridge GPU Die Sizes Compare, ITProPortal, April 24 2012, http://www.itproportal.com/2012/04/24/picture-ivy-bridge-vs-sandy- bridge-gpu-die-sizes-compared/[13]: AMD Completes ATI Acquisition and Creates Processing Powerhouse, Oct. 25 2006, http://www.amd.com/us/press-releases/Pages/Press_Release_113741.aspx[10]: 2nd Generation Intel Core Processor Family Desktop, Datasheet, Vol.1, Jan. 2011, http://pdfs.icecat.biz/pdf/28565951-9811.pdf[14]: AMD Torrenza and Fusion together, Metal Ghost, March 22 2007, http://www.metalghost.ro/index.php?option=com_content&view=article&id=233:amd- torrenza-and-fusion-together[15]: Rivas M., AMD 2007 Financial Analyst Day Presentation, Dec. 13 2007[16]: AMD Financial Analyst Day2008, Nov. 13 2008, http://gbcw.wordpress.com/2008/11/13/amd-financial-analyst-day-2008/[17]: Hruska J., AMD Fusion now pushed back to 2011, Ars Technica, Nov. 14 2008, http://arstechnica.com/uncategorized/2008/11/amd-fusion-now-pushed-back-to-2011/

[18]: Intel cans 45nm Auburndale and Havendale FusionCPUs!, Jan. 31 2009, http://theovalich.wordpress.com/2009/01/31/exclusive-intels-cans-45nm-auburndale- and-havendale-fusion-cpus/References (3)[20]: Foley D., AMDs LLANO Fusion APU, Hot Chips 23, Aug. 19 2011, http://www.hotchips.org/archives/hc23/HC23-papers/HC23.19.9-Desktop-CPUs/ HC23.19.930-Llano-Fusion-Foley-AMD.pdf[21]: AMD A-Series APU, EMEA Press Call, June 7 2011, http://img.zwame.pt/nemesis11/Amd_A_series/AMD.pdf[22]: Kirsch N., AMD Llano A-Series APU Sabine Notebook Platform Review, Legit Reviews, June 13 2011, http://www.legitreviews.com/article/1636/1/[19]: Wikipedia, Turion, http://en.wikipedia.org/wiki/Griffin_(processor)#Turion_X2_Ultra[23]: Chiappetta M., AMD A8-3850 Llano APU and Lynx Platform Preview, Hot Hardware, June 30 2011, http://hothardware.com/Reviews/AMD-A83850-Llano-APU-and-Lynx- Platform-Preview/?page=2[24]: Walrath J., AMD, Vishera, and Beyond: New Design Philosophy Dictates a Faster Pace, PC Perspective, July 5 2012, http://www.pcper.com/reviews/Editorial/AMD-Vishera-and- Beyond-New-Design-Philosophy-Dictates-Faster-Pace/How-Does-Vishera[25]: Wasson S., AMD's A10-4600M 'Trinity' APU reviewed, Tech Report, May 16 2012, http://techreport.com/review/22932/amd-a10-4600m-trinity-apu-reviewed

[26]: Paul D., Meet the new AMD APUs Series A-2nd generation Trinity, TechNews, May 15 2012, http://technewspedia.com/meet-the-new-amd-apus-series-a-2-nd-generation-trinity/References (4)[27]: OMAP 5 Mobile Applications Platform, Product Bulletin, Texas Instruments, 2011, http://www.ti.com/pdfs/wtbu/SWCT010.pdf[28]: Hibben M., Texas Instruments and the Big Chip Maker Anachronism, Nov. 16 2012, http://beta.fool.com/markhibben/2012/11/16/texas-instruments-and-big-chip-maker- anachronism/16680/[29]: Shimpi A.L., AMD A10-5800K & A8-5600K Review: Trinity on the Desktop, Part 1, AnandTech, Sept. 27 2012, http://www.anandtech.com/show/6332/amd-trinity-a10- 5800k-a8-5600k-review-part-1

Ksznm a figyelmet!

http://www.hardwarecanucks.com/forum/hardware-canucks-reviews/54260-amd-trinity-going-mobile-new-apu-4.htmlTrinitys Unified North Bridge []3.2.6 AMDs Piledriver-based Trinity desktop APU line (6)

http://hothardware.com/Reviews/AMD-Trinity-A104600M-Processor-Review/?page=3RMB: Radeon Memory BusGNB: Graphics North Bridge

http://www.hardwarecanucks.com/forum/hardware-canucks-reviews/54260-amd-trinity-going-mobile-new-apu-4.htmlTrinity Unified North Bridge

http://www.hardwarecanucks.com/forum/hardware-canucks-reviews/54260-amd-trinity-going-mobile-new-apu-4.html

The links between each section of the APU follow in the same footsteps as the previous generation but AMD has refined certain interconnects with the goal of speeding up information transfers. The AMD Fusion Compute Link is still considered to be a medium bandwidth connection which manages the complex interaction between the onboard GPU, the CPUs cache and the system memory. Unlike in the past, AMD has finally refined this interconnect, giving the GPU direct access to a coherent memory space while the CPU can now directly access the GPUs dedicated framebuffer if needed. This is one of the primary reasons why Trinitys theoretical data throughput has jumped from 572 GFLOPS to 736 GFLOPS. The Radeon Memory Bus on the other hand is the all-important link between the onboard graphics coprocessor and the primary on-chip memory controller. Rather than acting like a traffic cop (a la Fusion Compute Link) which tries to direct the flow of information, this memory bus is all about the GPU having unhindered high bandwidth access to the systems memory controllers. In the previous generations of AMD IGPs, before Llano came around, the Northbridges graphics processor had to jump through a series of hoops before gaining access to onboard memory which is partially why 128MB of SidePort memory was sometimes added. However, the APUs single chip, all in one solution allows for the elimination of many potential bottlenecks. http://www.hardwarecanucks.com/forum/hardware-canucks-reviews/54260-amd-trinity-going-mobile-new-apu-4.html

This unit adds virtual address access discrete graphics, allowing an external GPU to directly access the same virtual address space as the CPU through page tables. As you can imagine, this is a key part of the programming model for AMDs Heterogeneous Systems Architecture (HSA). http://www.tomshardware.com/reviews/a10-4600m-trinity-piledriver,3202-4.htmlTrinity

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