SH-MobileG1: A Single-Chip Application and Dual-mode ......1 SH-MobileG1: A Single-Chip Application...
Transcript of SH-MobileG1: A Single-Chip Application and Dual-mode ......1 SH-MobileG1: A Single-Chip Application...
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SHSH--MobileG1: MobileG1: A SingleA Single--Chip Application and Chip Application and
DualDual--mode Baseband Processormode Baseband Processor
Masayuki Ito1, Takahiro Irita
1, Eiji Yamamoto
1,
Kunihiko Nishiyama1, Takao Koike
1, Yoshihiko Tsuchihashi
1,
Hiroyuki Asano1, Hiroshi Yagi
1, Saneaki Tamaki
1,
Ken Tatezawa1, Toshihiro Hattori
1, Shinichi Yoshioka
1,
Koji Ohno2 *
.
1 Renesas Technology2 NTT DoCoMo
*: Currently with Renesas Technology
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OutlineOverview
SH-MobileG1 Architecture
- 3 CPU Configuration
- Communication Architecture
- Interrupt Control
- System Control
- Power Control and Leakage Current
Summary
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3G Multi-Media Cellular Phone System
HPAHigh Power Amplifier
RFICRadio Frequency IC
BasebandProcessor
ApplicationProcessor
Multi-MediaAccelerator
HPAHigh Power Amplifier
RFICRadio Frequency IC
One ChipSH-MobileG1
PreviousSystem
New SystemUsing G1
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Realtime OS (ITRON, etc.)
BB-CPU (ARM)
W-CDMA IPGSM/GPRS IP
Application-System domain
Baseband domain
SuperHyway Bus SuperHyway Bus
AP-RT CPU (SH) APSYS CPU(ARM)
Multi-MediaAccelalators
System Peripherals
BridgeBridge
SDRAMSDRAM SDRAMSDRAM
General Purpose OS(Symbian, Linux, etc.)
VideoVideoM/WM/W
CameraCameraM/WM/W
GSM/WCDMAGSM/WCDMAProtocol StackProtocol Stack
AudioAudioM/WM/W
File File SystemSystem JAVAJAVA DeviceDevice
DriverDriver
CameraCameraApplicationApplication
MailMailApplicationApplication
Video PhoneVideo PhoneApplicationApplication
BrowserBrowserApplicationApplication
TelephoneTelephoneApplicationApplication
APIAPI
Realtime OS (ITRON, etc.)
Application-Realtimedomain
A Sample of System Architecture using G1
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Motivation for One Chip Integration
GSM
W-CDMA
BB-CPU
APL-RTCPU
AP-SYSCPU
BB-Misc
AP-Misc
MediaRAM
3D G MPEG
Camera
SoundCPG
LCDC
JPEG
DDR
SRAM
- Chip-set cost will be down
- Mount area will be decreased by sharing
common peripherals
- Performance will be up by wide data
throughput
- Dynamic power will be saved by low-load
inter-domain signals
- Static power will be saved by leakage
current shut-off for unused domain
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Chip Overview
181M TRs,
13.5M Gate
20.2 Mbit mem
# of TRs, gate, memory
11.15mm x 11.15mm
Die size
1.2V(internal), 1.8/2.5/3.3V(I/O)
Supply voltage
90nm LP
8M(7Cu+1Al)
CMOS dual-Vth
Process
GSM
W-CDMA
BB-CPU
APL-RTCPU
AP-SYSCPU
BB-Misc
AP-Misc
MediaRAM
3D G MPEG
Camera
SoundCPG
LCDC
JPEG
DDR
SRAM
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G1 Module Diagram
BSC SBSC
LCDC
VIO
MFI
DMAC3DG
INTCRT
CPGAP
Camera
LCD
Med
ia B
us
JPU
VPU
HP
Bu
s (R
T)
APBB
AH
B B
us
AP-RT Block
DMAC
MFI
INTCSYS
HP
Bu
s (S
YS
)
Peripherals(SYS)
APB Bus
MMU
I-Cache
CPU
AP-SYS Block
D-Cache
MMU
I-Cache
CPU
BB Core Block
D-Cache
BB Main Bus
CPGBB
BBSC
WCDMA Block
GSM Block
MODEMDSP
MMU
I-Cache
CPU
D-Cache
URAM
DSP
XYRAM
INTCBB
SYSC WUC
Peripherals(RT)
DMAC
ABBPeripherals
S2SSuperHyway (SYS) SuperHyway (RT)
INTRAM
MODEMDSP
Peripherals
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AP-Realtime Domain Configuration
SHX2 runs on RT-OS - 2-way superscalar up to 312MHz
- 32KB-I$ and 32KB-D$
- 512KB onchipRAM
Media IPs - VPU encodes MPEG4 and H.264
- VIO handles up to 5M pixel
camera.
- 3D graphic accelerator
LCDC
VIO
Med
ia B
us
JPU
VPU
AP-RT Block (SHX2)
MMU
I-Cache
CPU
D-Cache
URAM
DSP
XYRAM
SBSC
MFI
DMAC3DG
INTCRT
HP
Bu
s (R
T)
Peripherals(RT)
SuperHyway (RT)S2S
S2S:SBSC:LCDC:VIO:
VPU:
JPU:3DG:INTC: MFI:
SHwy-SHwy bridgeSDR/DDR-SDRAM ControllerLCD ControllerCamera I/F with Image-
Processing EngineVideo Processing Unit
(MPEG-4 Accelerator)JPEG Codec Unit3D Graphics AcceleratorInterrupt ControllerMulti-Functional Interface
SDRAM(AP)
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AP-System Domain Configuration
BSC
CPGAP
APBB
DMAC
MFI
INTCSYS
HP
Bu
s (S
YS
)
Peripherals(SYS)
S2SSuperHyway (SYS)
ARM926EJ-S runs on
general-purpose OS- Up to 208MHz
- 32KB-I$ and 16KB-D$
Peripherals - Sound handling
- SDcard, IIC
- Flash Control
- USB
- BB communication serial
MMU
I-Cache
CPU
AP-SYS Block
D-Cache
S2S:APBB:BSC::CPG: INTC: MFI:
SHwy-SHwy bridgeAP-BB bridgeSRAM/FLASH ControllerClock Pulse GeneratorInterrupt ControllerMulti-Functional Interface
SRAM/FLASH
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Baseband Domain Configuration
APBB
AH
B B
us
APB Bus
MMU
I-Cache
CPU
BB Core Block
D-Cache
BB Main Bus
CPGBB
BBSCWCDMA Block
GSM Block
MODEMDSP
INTCBB
DMAC
Peripherals
ARM926EJ-S runs on RT-OS- Up to 104MHz
- 16KB-I$ and 4KB-D$ with TCM
W-CDMA and GSM/GPRS- DSP accelerates the modem
protocol handling
- One can be cut-off where only
the other is available
- Only small logic is awake for
tracing the timing of each radio
RAM MODEMDSP
Peripherals
APBB:BBSC:CPG:INTC:
AP-BB bridgeBaseband Bus ControllerClock Pulse GeneratorInterrupt Controller
SDRAM(BB)
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Communication Architecture
SH-MobileG1 (1 LSI with 3 CPUs)
AP- RTCPU
AP- SYSCPU
BasebandCPU
APBB
Serial
S2S
MFI
BSC
SerialPrevious System with 3 LSIs
- G1 keeps the communication paths (MFI and Serials)
used in the previous system for software reuse
Memory
AP- SYS LSI Baseband LSI
AP- RT LSI
Serial
BBSC BSC
MFI
MFI
Serial
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Communication Architecture (Cont’d)
AP Address MapBB Address Map
Map any region ofAP address byregister settings
Map any region ofBB address byregister settings
- AP-SYS and AP-RT share SDRAM and memory map
- AP and BB have different SDRAM and memory map
- APBB bridge supports access window scheme to access
the resource in the other memory map
AP Access WindowUsing AP-BB bridge
BB SDRAM
BB Periphral Regs
Flash
BB Access WindowUsing AP-BB bridgeRT Periphral Regs
Flash
SYS Periphral Regs
AP SDRAM
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Interrupt Control
AP- RTCPU
AP- SYSCPU
BasebandCPU
INTC(SYS)
INTC(BB)
INTC(RT)
Peripherals(SYS)
Peripherals(BB)
Peripherals(RT)
MFI MFI
- Each CPU has its INT controller
- MFI can generate inter-domain interruptions
- Some external pins generate interrupts for each CPU
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System Control
CPGAPCPGBB
S P W B S P W B S P W B
SemaphoreFree:00RT:01SYS:10BB:11
SYSC (Common)
Boot Control(Master CPU,Boot Address for each CPU)
SYSCBB SYSCSYS SYSCRT
Power Control
Boot Address
Boot Address
AP- SYSCPU
Boot Address
AP- RTCPU
PLLs PLLs
Reset Control
Reset Control
Reset Clock
Reset Clock
Reset Clock
S:SemaphoreRegister
P:Power Down Register
W:Wake-up Register
B: Boot ControlRegister Boot
Mode
RESET
WakeUp
BasebandCPU
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System Control (Cont’d)
GSM
W-CDMA
BB-CPU
APL-RTCPU
AP-SYSCPU
BB-Misc
AP-Misc
MediaRAM
MPEG
Camera
SoundCPG
LCDC
JPEG
DDR
SRAM
Boot Control- One master CPU defined by pin settings boots first and
specifies the other CPUs’ boot addresses
- Various boot modes are supported for system
configurability and debuggability(1) BB Master External Memory Boot(2) BB Master Internal ROM Boot(3) BB-Alone Mode (for Test)(4) AP-SYS Master External Memory Boot (5) AP-SYS Master Internal ROM Boot(6) AP-RT Master Boot(7) AP-Alone Mode (for Test)
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System Control (Cont’d)
GSM
W-CDMA
BB-CPU
APL-RTCPU
AP-SYSCPU
BB-Misc
AP-Misc
MediaRAM
3D G MPEG
Camera
SoundCPG
LCDC
JPEG
DDR
SRAM
Power Control- Each CPU can read and write SYSC registers from each
domain, which are reflected into the common SYSC
- Power up/down can be controlled by each CPU that gets
the semaphore
Clock Control- AP and BB have separate Clock Pulse Generator
- Many variations of clock configuration and gear changes
are supported for dynamic power reduction
- Clock for some IPs remains the fixed frequency
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Power Domain
20 hierarchical domains for partial power-off
C4 (Repeaters, CK buffers, BKUP FFs)
C5 (System controller, PAD controller)
LCDC Reg Mem Control. RAM, DMAVRAM
Application part Baseband part
PLL for Application part PLL for Baseband part
Mobile Video Interface
Mem control. Serial I/Os
SYS-CPU RT-CPU
BB-CPU WCDMA GSM
DFT WCDMA GSM
WCDMA GSM
A4U1 A4U2 A4
AC
A3
A2
A1RA1A
BA4
BC
BG3
BG2
BG1
BW3
BW2
BW1
BA3
BA2
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Power Domain (Cont’d)
GSM
APL-RTCPU SRAM
C4
Chip Floorplan Power Domains
C5
GSM
W-CDMA
BB-
CPUAPL-RT
CPU
AP-SYS
CPU
BB-
Misc
AP-Misc
Media
RAM
3DGMPEG
Camera
Sound
JPEG
A2
A1A
A4
ACBC
BA2
BW2
BW
3B
W1
BA4
BA3
BG1 BG2BG3
A3
A4U1
A4U
2A1R
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Implementation Results of Power Domains
# of Power domains
# of Islands for C4(Repeaters,CK buffers, BKUP FFs)
# of Repeaters in C4 domain
# of Clock buffers in C4 domain
# of Backup FFs in C4 domain
# of mIOs (isolation cell)
Total area of power switch
20 domains
19 islands
3100 cells
1600 cells
2300 cells
20000 cells
4.2 mm2
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Leakage Current in Usage Scenes
A1R
A4U2A3
A4U1
A1A
A2A4
C5AC
BW2
BA3
BW1
BG1 BG2BG3
BC
BA4BW3
C4
BA2
(1) Video telephony
Measured Leakage Current
(@ Room Temp, 1.2V)
Control
W-CDMA
GSM
System-domain
Realtime-domain
Baseband
part
Application
part
Power on
Power off
ON
ON
ON / OFF
ON
ON
849 µA
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Leakage Current in Usage Scenes
(2)Telephony (W-CDMA)
Measured Leakage Current
(@ Room Temp, 1.2V)
Control
W-CDMA
GSM
System-domain
Realtime-domain
Baseband
part
Application
part
Power on
Power off
ON
ON
ON / OFF
ON
OFF
407 µA
A1R
A4U2A3
A4U1
A1A
A2A4
C5AC
BW2
BA3
BW1
BG1 BG2BG3
BC
BA4BW3
C4
BA2
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Leakage Current in Usage Scenes
(3)Waiting for Calling
Measured Leakage Current
(@ Room Temp, 1.2V)
Control
W-CDMA
GSM
System-domain
Realtime-domain
Baseband
part
Application
part
Power on
Power off
ON
OFF *
OFF
OFF
OFF
299 µA
A1R
A4U2A3
A4U1
A1A
A2A4
C5AC
BW2
BA3
BW1
BG1 BG2BG3
BC
BA4BW3
C4
BA2
*: Intermittent Operation
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Leakage Current in Usage Scenes
(4) Power off ( I/O fixed)
Measured Leakage Current
(@ Room Temp, 1.2V)
Control
W-CDMA
GSM
System-domain
Realtime-domain
Baseband
part
Application
part
Power on
Power off
OFF
OFF
OFF
OFF
OFF
7 µA
A1R
A4U2A3
A4U1
A1A
A2A4
C5AC
BW2
BA3
BW1
BG1 BG2BG3
BC
BA4BW3
C4
BA2
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Summary
We have developed SH-MobileG1
- Application and dual-baseband single-chip
processor for 3G multimedia cellular phone
system
- Key features of its architecture have been
presented
- One chip integration contributes not only to
dynamic but also to leakage current reduction
by careful partial power-off control