SerDes Presentation
-
Upload
mohit-singh -
Category
Documents
-
view
228 -
download
1
Transcript of SerDes Presentation
-
8/17/2019 SerDes Presentation
1/23
Presented By:-
Mohit Singh Choudhary
M.Tech. Communication and Signal Processing
Discipline of Electrical Engineering
IIT Indore
IIT-Indore | EE 799 | M.Tech. Project Stage 1
Guided By:-
Dr. Santosh Kum
Assistant Profes
Discipline of Ele
IIT Indore
CML-SerDes
-
8/17/2019 SerDes Presentation
2/23
IIT-Indore |
Contents
Introduction
Motivation
Literature Review
Implementation
Application
Future Work
References
-
8/17/2019 SerDes Presentation
3/23
Motivation
Parallel Interconnections• Large I/O Pins
• More Power consumed
•
Problem in meeting timing requirement• On Chip-area is more
Sender Receiver
IIT-Indore |
David Robert Stauffer, 2008. High Speed Serdes Devices and Applications. 2009 Edition. Springer
3
-
8/17/2019 SerDes Presentation
4/23
Motivation
Large Distance Transmission• Infeasible to transmit parallel data to a large distance.
IIT-Indore |
David Robert Stauffer, 2008. High Speed Serdes Devices and Applications. 2009 Edition. Springer
4
-
8/17/2019 SerDes Presentation
5/23
Introduction
IIT-Indore |
SerDes ( Serializer and Deserializer)• Multiplexing bit data to bit of interconnect and at receiver demultiplexing
interconnect to bit data(< ).
Serializer Deserializer /
David Robert Stauffer, 2008. High Speed Serdes Devices and Applications. 2009 Edition. Springer
5
-
8/17/2019 SerDes Presentation
6/23
Introduction
IIT-Indore |
SerDes
Types of SerDes on the basis of design techniques.
Introduction
6
-
8/17/2019 SerDes Presentation
7/23
Introduction
IIT-Indore |
/2 /4
Serialization• Serializer uses mux to convert parallel data into serial output.
Safwat, Sally; Hussein, E.E.; Ghoneima, M.; Ismail, Y., "A 12Gbps all digital low power SerDes transceiver for on-chip netwo
(ISCAS), 2011 IEEE International Symposium, pp.1419-1422, 15-18 May 2011
Introduction
7
-
8/17/2019 SerDes Presentation
8/23
Introduction
IIT-Indore |
Deserialization• Deserializer uses DFF to deserialize input bits.
DFF DFF DFF DFF DFF DFF DF
Introduction
8
-
8/17/2019 SerDes Presentation
9/23
Introduction
IIT-Indore |
CML (Current Mode Logic)• Current mode logic provides true differential operation, low noise level and no
immunity with low dynamic power dissipation.
− = ≤ ,
1.2
1.2
0
0.7
Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes,
(SOCC), 2014 27th IEEE International , pp.5-10, 2-5 Sept. 2014
Introduction
9
-
8/17/2019 SerDes Presentation
10/23
Literature Review
IIT-Indore |
1. Safwat, Sally; Hussein, E.E.; Ghoneima, M.; Ismail, Y., "A 12Gbps all digital low power SerDes transceiver for on-chip net
and Systems (ISCAS), 2011 IEEE International Symposium, pp.1419-1422, 15-18 May 2011.
2. Hussein, Ezz El-Din; Safwat, Sally; Ghoneima, M.; Ismail, Y., "A 16Gbps low power self-t imed SerDes transceiver for mult
in Circuits and Systems (ISCAS), 2012 IEEE International Symposium, pp.1660-1663, 20-23 May 2012
/2 /4
DETFF
DETFF
DETFF
DETFF
DETFF
DETFF
DETFF
VDD/2
"1"
VDD
0
10
-
8/17/2019 SerDes Presentation
11/23
Literature Review
IIT-Indore |
Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes,
(SOCC), 2014 27th IEEE International , pp.5-10, 2-5 Sept. 2014
a). Serializer b). Deserializer
Literature Review
11
-
8/17/2019 SerDes Presentation
12/23
Literature Review
IIT-Indore |
Tondo, D.F.; Lopez, R.R., "A low-power, high-speed CMOS/CML 16:1 serializer," in Micro-Nanoelectronics, Technology and A
Argentine School of Micro-Nanoelectronics, Technology and Application, pp.81-86, 1-2 Oct. 2009
Serializer Architecture
Literature Review
12
l i
-
8/17/2019 SerDes Presentation
13/23
Implementation
IIT-Indore |
Serializer• We have implemented serializer using CML.
• Input CMOS data is converted into CML.
• Then CML mux is used to serialize data.
• CML serialized output is converted back into CMOS for transmission.
CMOS to CML MUX CML to C
Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes,
(SOCC), 2014 27th IEEE International , pp.5-10, 2-5 Sept. 201413
I l i
I l i
-
8/17/2019 SerDes Presentation
14/23
Implementation
IIT-Indore |
Serializer• Serializer is implemented in 65nm UMC CMOS technology.
Implementation
14
I l t ti
I l t ti
-
8/17/2019 SerDes Presentation
15/23
Implementation
IIT-Indore |
Serializer• Serialization we got at 16.64Gbps speed.
Implementation
15
I l t ti
I l t ti
-
8/17/2019 SerDes Presentation
16/23
Implementation
IIT-Indore |
Deserializer• At the receiver deserialization is done using two parallel chain of DFF.
• Half clock is used and bits are shifted at both edges
/2
DFF DFF DFF DFF
DFF DFF DFF DFF
Implementation
16
I l t ti
I l t ti
-
8/17/2019 SerDes Presentation
17/23
Implementation
IIT-Indore |
Deserializer• Deserializer we have implemented with the help of CML DFF which is build us
latch.
CML Latch
Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes,
(SOCC), 2014 27th IEEE International , pp.5-10, 2-5 Sept. 2014
Implementation
17
I l t ti
I l t ti
-
8/17/2019 SerDes Presentation
18/23
Implementation
IIT-Indore |
Deserializer• Deserializer is implemented in 65nm UMC CMOS technology.
Implementation
18
Implementation
Implementation
-
8/17/2019 SerDes Presentation
19/23
Implementation
IIT-Indore |
Results
Implementation
19
() (℃) −
1.08 125 11.49 / 15.36 /
1.2 27 12.67 / 16.64 /
ff 1.32 −45 13.75 / 16.96 /
ℎ ℎ () ()
− [4] 65 16 18.1 − [2] 65 12.67 14.3
CMOS − CML[5] 45/65 10 50/106
ℎ 65 16.64 9.29
PVT Corners of various SerDes techniques
Comparison of various SerDes techniques
Submitted: Mohit Singh Choudhary, Mahesh Kumawat, Pramod Kumar Bharti and Dr. S. K. Vishvakarna, “Power Optimized
CML SerDes Transceiver Design with Process Corner Variation” IET Electronics Letter
Application
-
8/17/2019 SerDes Presentation
20/23
Application
IIT-Indore |
Application• Telecom wireless communication
• In video transmission (FlatLink)
• Transceiver Devices
• Telecom Switching Applications
• 8b/10b SerDes are used in Ethernet, Fiber optics, InfiniBand
Dave Lewis, “SerDes Architectures and Application”, National Semiconductor Corporation
20
Future work
-
8/17/2019 SerDes Presentation
21/23
Future work
IIT-Indore |
Dynamic CML• Reduced swing logic style that reduces both gate and interconnect power diss
• DyCML circuits combines the advantages of CML with those of dynamic logic f
achieve high performance at a low-voltage with low-power dissipation.
Asynchronous Circuits• Asynchronous circuits since does not require clock thus saves lot of power con
oscillators and CDR.
Encoding• Serial data can be encoded to 3-level, 8b/10b etc so that speed can be increas
1 . Allam, M.W.; Elmasry, M.I., "Dynamic current mode logic (DyCML): a new low-power high-performance logic style," in S
Journal of , vol.36, no.3, pp.550-558, Mar 2001.
2. Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip asynchronous Wave-pipelined CML SerD
Conference (SOCC), 2014 27th IEEE International , pp.5-10, 2-5 Sept. 2014.
3. Hussein, Ezz El-Din; Safwat, Sally; Ghoneima, M.; Ismail, Y., "A 16Gbps low power self-timed SerDes transceiver for mul
in Circuits and Systems (ISCAS), 2012 IEEE International Symposium, pp.1660-1663, 20-23 May 2012.
21
References
-
8/17/2019 SerDes Presentation
22/23
References
IIT-Indore |
References[1]. David Robert Stauffer, 2008. High Speed Serdes Devices and Applications. 200
Springer
[2]. Jaiswal, A.; Walk, D.; Yuan Fang; Hofmann, K., "Low-power high-speed on-chip
asynchronous Wave-pipelined CML SerDes," in System-on-Chip Conference (SOCC27th IEEE International , pp.5-10, 2-5 Sept. 2014
[3]. Safwat, Sally; Hussein, E.E.; Ghoneima, M.; Ismail, Y., "A 12Gbps all digital low
SerDes transceiver for on-chip networking," in Circuits and Systems (ISCAS), 2011
International Symposium on , pp.1419-1422, 15-18 May 2011
[4]. Hussein, Ezz El-Din; Safwat, Sally; Ghoneima, M.; Ismail, Y., "A 16Gbps low po
timed SerDes transceiver for multi-core communication," in Circuits and Systems
2012 IEEE International Symposium on, pp.1660-1663, 20-23 May 2012[5]. Tondo, D.F.; Lopez, R.R., "A low-power, high-speed CMOS/CML 16:1 serializer,
Nanoelectronics, Technology and Applications, 2009. EAMTA 2009. Argentine Sch
of Micro-Nanoelectronics, Technology and Application, pp.81-86, 1-2 Oct. 2009
22
-
8/17/2019 SerDes Presentation
23/23
Thanks