Sequential Logic

1

Sequential Sequential LogicLogic

Lecture #7Lecture #7

모바일컴퓨팅특강 2

강의순서강의순서 Latch FlipFlop

Active-high Clock & asynchronous Clear Active-low Clock & asynchronous Clear Active-high Clock & asynchronous Preset Active-high Clock & asynchronous Clear & Preset

Shift Register Counter

4 bits Universal Counter : 74161 Modulo 16 Up counter Modulo 16 Down counter Modulo 16 Up Down counter 0-14 hold Up counter


SR LatchSR Latch

Most simple “storage element”.

Qnext = (R + Q’current)’

Q’next = (S + Qcurrent)’

In1 In2 Out0 0 10 1 01 0 01 1 0

NOR

S R Q

0 0 No change0 1 0 (reset)1 0 1 (set)

Function Table

Storing


SR latches are sequentialSR latches are sequential

For inputs SR = 00, the next value of Q depends on the current value of Q.

So the same inputs can yield different outputs.

This is different from the combinational logics.

I nputs Current NextS R Q Q’ Q Q’

0 0 0 1 0 10 0 1 0 1 0

0 1 0 1 0 10 1 1 0 0 11 0 0 1 1 01 0 1 0 1 0

S R Q

0 0 No change0 1 0 (reset)1 0 1 (set)


Timing Diagram for S-R Timing Diagram for S-R LatchLatch

S

R

Q

Q’Set Reset


SR latch simulationSR latch simulation


What about SR = 11?What about SR = 11?

Both Qnext and Q’next will become 0.

If we then make S = 0 and R = 0 together,

Qnext = (0 + 0)’ = 1Q’next = (0 + 0)’ = 1

But these new values go back into the NOR gates, and in the next step we get:

Qnext = (0 + 1)’ = 0Q’next = (0 + 1)’ = 0

The logic enters an infinite loop, where Q and Q’ cycle between 0 and 1 forever. (Unstable)

This is actually the worst case, so we have to avoid setting SR=11.

Qnext = (R + Q’current)’Q’next = (S + Qcurrent)’

0

0

0

0

0

0

1

1


An SR latch with a control An SR latch with a control inputinput(Gated SR latch)(Gated SR latch)

The dotted blue box is the S’R’ latch from the previous slide. The additional NAND gates are simply used to generate the corr

ect inputs for the S’R’ latch. The control input acts just like an enable.

C S R S’ R’ Q

0 x x 1 1 No change1 0 0 1 1 No change1 0 1 1 0 0 (reset)1 1 0 0 1 1 (set)1 1 1 0 0 Avoid!


D latch (Gated D latch)D latch (Gated D latch)

D latch is based on an S’R’ latch. The additional gates generate the S’ and R’ signals, based on inputs D (“data”) and C (“control”).

When C = 0, S’ and R’ are both 1, so the state Q does not change.

When C = 1, the latch output Q will equal the input D. Single input for both set and reset

Also, this latch has no “bad” input combinations to avoid. Any of the four possible assignments to C and D are valid.

C D Q

0 x No change1 0 01 1 1


Timing diagram for D Timing diagram for D LatchLatch

Q follows D while EN is HIGH.


D latch with BDFD latch with BDF


D latch simulation with D latch simulation with PrimitivePrimitive Insert the

symbol latch


Simulation result with Simulation result with PrimitivePrimitive


D latch simulation with D latch simulation with VHDL fileVHDL file


The D flip-flop : Edge The D flip-flop : Edge triggeringtriggering

• The D flip-flop is said to be “edge triggered” since the output Q only changes on the rising edge (positive edge) of the clock signal

DLatch

D1

C

Q1

Q’

DLatch

D2

C

Q2

Q2’

D

C

Q


Timing Diagram for a D flip-Timing Diagram for a D flip-flopflop

C

D

Q

Q1

shift

shift

Positive Edge Triggering


Direct inputsDirect inputs

Most flip-flops provide direct, or asynchronous, inputs that immediately sets or clears the state.

The below is a D flip-flop with active-low direct inputs.S’ R’ C D Q

0 0 x x Avoid!0 1 x x 1 (set)1 0 x x 0 (reset)

1 1 0 x No change1 1 1 0 0 (reset)1 1 1 1 1 (set)

Direct inputs to set or reset the flip-flop

S’R’ = 11 for “normal” operation of the D flip-flop


D FF with BDFD FF with BDF

Insert the symbol dff

Edge-trigger symbol


D FF with VHDL fileD FF with VHDL file


FlipFlop FlipFlop with active-high Clock &with active-high Clock & asynchronous Clear asynchronous Clear

library ieee;use ieee.std_logic_1164.all;entity dff_1 is port( d, clk, nclr : in std_logic; q : out std_logic );end dff_1 ;architecture a of dff_1 isbegin

process(nclr,clk)begin if( nclr='0') then

q <='0'; elsif(clk'event and clk='1') then

q <= d; end if;end process;

end a;


FlipFlop FlipFlop with active- low Clock &with active- low Clock & asynchronous Clear asynchronous Clear

library ieee;use ieee.std_logic_1164.all;entity dff_fall_1 is port( d, clk, nclr : in std_logic; q : out std_logic );end dff_fall_1 ;architecture a of dff_fall_1 isbegin

process(nclr,clk)begin if( nclr='0') then

q <='0'; elsif(clk'event and clk=‘0') then


end a;


FlipFlop FlipFlop with active-high Clock &with active-high Clock & asynchronous Preset asynchronous Preset

library ieee;use ieee.std_logic_1164.all;entity dff_ preset_1 is port( d, clk, npre : in std_logic; q : out std_logic );end dff_ preset_1 ;architecture a of dff_ preset_1 isbegin

process(npre,clk)begin if( npre='0') then

q <=‘1'; elsif(clk'event and clk=‘1') then


end a;


FlipFlop FlipFlop with active-high Clock &with active-high Clock & asynchronous Clear & Preset asynchronous Clear & Presetlibrary ieee; use ieee.std_logic_1164.all;entity dff_ presetclr_1 is port( d, clk, npre,nclr : in std_logic; q : out std_logic );end dff_ presetclr_1 ;architecture a of dff_ presetclr_1 isbegin

process(npre, nclr, clk)begin if( npre='0') then

q <=‘1'; elsif( nclr='0') then

q <=‘0'; elsif(clk'event and clk=‘1') then


end a;


Shift RegisterShift Registerlibrary ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity shiftreg is port( d, clk,nclr : in std_logic; qa,qb : out std_logic );end shiftreg;

architecture a of shiftreg issignal tqa,tqb : std_logic;

beginprocess(nclr,clk)begin if( nclr='0') then

tqa <='0'; tqb <='0';

elsif(clk'event and clk='1') thentqa <= d; tqb <= tqa;

end if;end process;qa<=tqa; qb<=tqb;

end a;


library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity cnt161_4bits is port( d3,d2,d1,d0 : in std_logic; nld,ent,enp : in std_logic; clk,nclr : in std_logic; q3,q2,q1,q0 : out std_logic; rco : out std_logic);end cnt161_4bits;architecture a of cnt161_4bits is

signal q : std_logic_vector( 3 downto 0);begin

process(nclr,clk)variable d : std_logic_vector(3 downto 0);begin

d := d3&d2&d1&d0;if( nclr='0') then q <="0000";elsif(clk'event and clk='1') then

if(nld='0') then q <= d;elsif(ent='1' and enp='1') then

q <= q+'1';end if;

end if;end process;q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); rco <= ent and q(3) and q(2) and q(1) and q(0);

end a;

74161 은 실제로 가장 널리 사용되는 4 비트

카운터임

74161 은 실제로 가장 널리 사용되는 4 비트

카운터임

4 bits Universal Counter: 741614 bits Universal Counter: 74161


library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity mod16cnt is

port( clk,nclr : in std_logic;

q3,q2,q1,q0 : out std_logic);

end mod16cnt;

architecture a of mod16cnt is

signal q : std_logic_vector( 3 downto 0);

begin

process(nclr,clk)

begin

if( nclr='0') then q <="0000";

elsif(clk'event and clk='1') then

q <= q+'1';

end if;

end process;

q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);

end a;

Modulo 16 Up CounterModulo 16 Up Counter


library ieee;

use ieee.std_logic_1164.all;


entity mod16dncnt is



end mod16dncnt;

architecture a of mod16dncnt is


begin

process(nclr,clk)

begin

if( nclr='0') then q <="0000";


q <= q-'1';

end if;

end process;

q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);

end a;

Modulo 16 Down CounterModulo 16 Down Counter


Modulo 16 Up Down Modulo 16 Up Down countercounter

library ieee; use ieee.std_logic_1164.all;


entity UpDncnt4 is


UpDn : in std_logic;


end UpDncnt4;

architecture a of UpDncnt4 is


begin

process(nclr,clk)

begin

if( nclr='0') then q <="0000";


if( UpDn='1') then q <= q+'1';

else q <= q-'1';

end if;

end if;

end process;

q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);

end a;

1 이면 증가

1 이면 증가

0 이면 감소

0 이면 감소


library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mod15cnt is port( clk,nclr : in std_logic; q3,q2,q1,q0 : out std_logic);end mod15cnt;architecture a of mod15cnt is

signal q : std_logic_vector( 3 downto 0);begin

process(nclr,clk)begin

if( nclr='0') thenq <="0000";

elsif(clk'event and clk='1') thenif( q="1110") then

q<="0000";else q <= q+'1';end if;

end if;end process;q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);

end a;

14에서 0

으로 증가

14에서 0

으로 증가

Modulo 15 Up CounterModulo 15 Up Counter


library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mod15holdcnt is port( clk,nclr : in std_logic; q3,q2,q1,q0 : out std_logic);end mod15holdcnt;architecture a of mod15holdcnt is


beginprocess(nclr,clk)begin

if( nclr='0') then q <="0000";elsif(clk'event and clk='1') then

if( q=14) then q<=q;else q <= q+'1';end if;

end if;end process;q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);

end a;

14에서 정지

14에서 정지

0-14 hold Up Counter0-14 hold Up Counter


1bit Async load down counter1bit Async load down counter


4bit Async load down counter


1bit Async Sync load down counter


8bit Async sync load down counter


State Machine - State Machine - 강의순서강의순서

Mealy Machine

Moore Machine


State Machine - State Machine - Mealy Mealy MachineMachine

Mealy Machine 현재의 상태 (Current State) 와 현재의 입력 (Inputs) 에

의해 출력이 결정

Combination

Logic F/FInputs

Outputs

Current State

Combination

Logic

Next State


State Machine - State Machine - Moore Moore MachineMachine Moore Machine

현재의 상태 (Current State) 에 의해 출력 (Outputs) 이 결정

Combination

Logic F/FInputs

Outputs

Current State

Combination

Logic

Next State


Mealy Machine – Mealy Machine – VHDL VHDL ExampleExample

S0

S1

0/00

1/00

0/01 1/10

WindowAct / RiseShot, FallShot

입력 / 출력 1, 출력 2

해석

1. WindowAct 신호가 0 에서 1 로 변하는 순간에 RiseShot 을 1 로 만들고 ,

2. WindowAct 신호가 1 에서 0 로 변하는 순간에 FallShot 을 1 로 만들어야함 ..

해석

1. WindowAct 신호가 0 에서 1 로 변하는 순간에 RiseShot 을 1 로 만들고 ,

2. WindowAct 신호가 1 에서 0 로 변하는 순간에 FallShot 을 1 로 만들어야함 ..


Mealy Machine–Mealy Machine–Process 2Process 2 개 개 사용사용

Library ieee; Use ieee.std_logic_1164.all;

ENTITY RiseFallShot IS

PORT( clk : IN STD_LOGIC;

reset : IN STD_LOGIC;

WindowAct : IN STD_LOGIC;

RiseShot, FallShot : OUT STD_LOGIC);

END RiseFallShot;

ARCHITECTURE a OF RiseFallShot ISTYPE STATE_TYPE IS (s0, s1);SIGNAL state: STATE_TYPE;

BEGINPROCESS (clk, reset)BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS

WHEN s0 => IF WindowAct='1' THEN state <= s1; ELSE state <= s0; END IF;

WHEN others => IF WindowAct='0' THEN state <= s0; ELSE state <= s1; END IF;END CASE;

END IF;END PROCESS;

Combination

Logic F/FInputs

Outputs

Current State

Combination

Logic

Next State

같은 부분같은 부분

Entity 문에 입출력이 표시 .Entity 문에 입출력이 표시 .



PROCESS(state, WindowAct)

BEGIN

if( state= s0 and WindowAct='1') then

RiseShot <='1';

else

RiseShot <='0';

end if;

if( state= s1 and WindowAct='0') then

FallShot <='1';

else

FallShot <='0';

end if;

END PROCESS;

END a;

Combination

Logic F/F

Outputs

Current State

Combination

Logic

Next State

Inputs



Mealy Machine–Mealy Machine–Process 3Process 3 개 개 사용사용library ieee;Use ieee.std_logic_1164.all;ENTITY RiseFallShot_v2 IS

PORT(clk : IN STD_LOGIC;reset : IN STD_LOGIC;WindowAct : IN STD_LOGIC;RiseShot, FallShot : OUT STD_LOGIC);

END RiseFallShot_v2;

ARCHITECTURE a OF RiseFallShot_v2 ISTYPE STATE_TYPE IS (s0, s1);SIGNAL State, NextState: STATE_TYPE;

BEGINPROCESS (State, WindowAct)BEGIN

CASE State ISWHEN s0 =>

IF WindowAct='1' THENNextState <= s1;

ELSENextState <= s0;

END IF;WHEN others =>



END IF;END CASE;

END PROCESS;

Combination

Logic F/FInputs

Outputs

Current State

Combination

Logic

Next State





PROCESS(reset,clk)BEGIN

IF reset = '0' THENState <= s0;

ELSIF clk'EVENT AND clk = '1' THENState <= NextState;

END IF;END PROCESS;

PROCESS(State,WindowAct) BEGIN if( State= s0 and WindowAct='1') then RiseShot <='1'; else RiseShot <='0'; end if; if( State= s1 and WindowAct='0') then FallShot <='1'; else FallShot <='0'; end if; END PROCESS;

END a;

Combination

Logic F/FInputs

Outputs

Current State

Combination

Logic

Next State




Moore Machine – Moore Machine – VHDL VHDL ExampleExample

S0000

S1010

0

01

1

S2101

1

상태출력

입력 : WindowAct

출력 : y(2:0)

해석

1. WindowAct 신호가 0 에서는 상태의 변화가 없으며 , 1 인 구간에서는 상태의 변화가 S0->S1->S2->S0 로 순환한다 .

2. 출력신호 y(2:0) 은 상태가 S0 인 경우 “ 000” 을 S1 인 경우에는 “ 010” 을 S2인 경우에는 “ 101” 을 출력한다 .

해석

1. WindowAct 신호가 0 에서는 상태의 변화가 없으며 , 1 인 구간에서는 상태의 변화가 S0->S1->S2->S0 로 순환한다 .

2. 출력신호 y(2:0) 은 상태가 S0 인 경우 “ 000” 을 S1 인 경우에는 “ 010” 을 S2인 경우에는 “ 101” 을 출력한다 .


Moore Machine–Moore Machine–Process 2Process 2 개 개 사용사용

Library ieee; Use ieee.std_logic_1164.all;ENTITY MooreMachine ISPORT( clk : IN STD_LOGIC;

reset : IN STD_LOGIC;WindowAct : IN STD_LOGIC;y : OUT STD_LOGIC_vector(2 downto 0));

END MooreMachine;

ARCHITECTURE a OF MooreMachine ISTYPE STATE_TYPE IS (s0, s1,s2);SIGNAL state: STATE_TYPE;

BEGINPROCESS (clk, reset)BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS

WHEN s0 => IF WindowAct='1' THEN

state <= s1;ELSE

state <= s0; END IF;

WHEN s1 => IF WindowAct='1' THEN

state <= s2;ELSE


WHEN others => IF WindowAct='1' THEN

state <= s0;ELSE


END CASE; END IF;END PROCESS;

Entity 문에 입출력이 표시 .Entity 문에

입출력이 표시 .

Combination

Logic F/FInputs

Outputs

Current State

Combination

Logic

Next State

같은부분

같은부분



PROCESS(state)BEGIN

CASE state ISWHEN s0 =>

y <= "000";WHEN s1 =>

y <= "010";WHEN others =>

y <= "101"; END CASE;END PROCESS;END a;

Combination

Logic F/FInputs

Outputs

Current State

Combination

Logic

Next State



Moore Machine–Moore Machine–Process 3Process 3 개 개 사용사용Library ieee;Use ieee.std_logic_1164.all;ENTITY MooreMachine_v3 ISPORT( clk : IN STD_LOGIC;

reset : IN STD_LOGIC;WindowAct : IN STD_LOGIC;y : OUT STD_LOGIC_vector(2 downto 0));

END MooreMachine_v3;

ARCHITECTURE a OF MooreMachine_v3 ISTYPE STATE_TYPE IS (s0, s1,s2);SIGNAL state, NextState: STATE_TYPE;

BEGINPROCESS ( State, WindowAct)BEGIN

CASE State ISWHEN s0 =>



END IF;WHEN s1 =>



END IF;WHEN others =>



END IF;END CASE;

END PROCESS;


Combination

Logic F/FInputs

Outputs

Current State

Combination

Logic

Next State




PROCESS (clk, reset)BEGIN IF reset = '0' THEN state <= s0; ELSIF clk'EVENT AND clk = '1' THEN

state <= NextState; END IF;END PROCESS;

PROCESS(state)BEGIN

CASE state IS WHEN s0 =>

y <= "000"; WHEN s1 =>

y <= "010"; WHEN others =>

y <= "101"; END CASE;

END PROCESS;END a;

Combination

Logic F/FInputs

Outputs

Current State

Combination

Logic

Next State

같은부분

같은부분

같은 부분

같은 부분


참고문헌참고문헌

1. PERRY, VHDL 4/E : PROGRAMMING BY EXAMPLE .

2. FLOYD, DIGITAL FUNDAMENTALS WITH VHDL .

3. ARMSTRONG,GRAY, VHDL DESIGN REPRESENTATION & SYNTHESIS.

4. SKHILL, VHDL FOR PROGRAMMABLE LOGIC .5. PELLERIN, VHDL MADE EASY.6. LEE, VHDL CODING & LOGIC SYNTHESIS

WITH SYNOPSYS.

Sequential Logic

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