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安捷倫科技高頻元件量測研討會

時間: 2006年 2月23日地點: 高雄金典酒店

1

安捷倫高頻元件量測研討會

2/23/2006Page 1

Packaging Development Trend of Integrated Analysis

Sung-Mao Wu

安捷倫科技高頻元件量測研討會2/23/2006

OutlineDevelopment Trend for PKG

-- PKG Technology Trend-- Why SiP and POP/PIP

Challenges to PKG Integrity Design-- Design Challenges on Simulation, Measurement and Design-- Case I : Effective DK-- Case II : Impedance Control verify by TDR-- Case III: TDR FA Application-- Case IV : Substrate Ball Pad Design-- Case V : PDS Analysis

Integrated Design-- Components of Optimization PKG Design-- Advanced PKG Analysis Flow-- Plan and Actions for PKG Design

2


Bio tech / New form chip

IC/module/System DesignHigh speed/high frequency

High thermal / Stress solution

Fab/fablessCopper wafer

Low K material

12” wafer

Naro meter tech

Front/Back end solutionEnvironment friendly

Compact Size

Low power consumption

Integrated SystemLow cost

Short Time to Market

Worldwide strategy

SemiconductorIndustry

Interesting SemiconductorWorld


Page 4

Packaging Technology Trend

Single Chip Package

Stacked Package

Flip Chip

Stacked Die

1995 2000 2005 2010

QFP

Multiple Chip Package

BGA

MCM

FC+WB

System in Package

Laminate 2 & 4 Layer

Build-Up SubstrateMulti-Layer

PCB

Chip

Functional Substrate(Active & Passive Chip)

PiP

PoP

Wire Bond Wire Bond + FC Bond New Interconnection?

3


Page 5

Why SIP ?

Single Chip Solution

SoC IC

Build-up Substrate

Sub-System Module

Board Assembly

Passives Micro-component

Memory IC

SIPCompare to Board Assembly:Compare to Board Assembly:

Performance EnhancementPerformance EnhancementThinner, Smaller, and LighterThinner, Smaller, and LighterLow CostLow Cost

Compare to SOCCompare to SOCLow Cost Low Cost Time to MarketTime to MarketFlexibleFlexible

SIP SIP PlatformPlatform

Die Stacking Platform

Package Stacking Platform

Flash SDRAMASIC

Flash SDRAM

ASIC

ASIC

Flash SDRAM


Page 6

1.4mm

1.2mm

0.8mm

1.0mm

0.5mm

2 die 3 die 4 die 5 die 7 die

Die Stacking Package Trend• Smaller & Lighter Package Size

• High Density Device in Package

4


Page 7

PoP and PiP

Available 2006 2007

Package/ Die Count

Package Thickness

Package Structure

Package/ Die Count

Package Thickness

Package Structure

2 PKG/ 3 Chip 2 PKG/ 3 Chip 2 PKG/ 4 Chip 3 PKG/ 7 Chip

1.6 mm Max 1.4 mm Max 1.2 mm Max 2.0 mm Max

ASIC

Flash SDRAM

ASIC

Flash SDRAM

Flash SDRAM

ASIC

Flash SDRAM

ASIC

1.4 mm Max 1.2 mm Max 1.0 mm Max

2 PKG/ 3 Chip 2 PKG/ 3 Chip 2 PKG/ 3 Chip

W/B Type

F/C Type

PoP

PiP


Page 8

IC Feature Size (um) 0.25 0.18 0.13 0.09 0.065

• Wire Bond pad Pitch (um)

(Single-In-Line)

• Wire Bond Pad Pitch (um)

(2 Row Staggered)

• Wire Bond Pad Pitch (um)

(Tri-Tier)

•Wire Bond pad pitch (um )

( Quad-Tier )

60 50 45 40 35

80/40 70/35 60/30 50/25 40/20

90/45 80/40 70/35 60/30 50/25

100/50 90/45 80/40 70/35 60/30

Leading-Edge Fine-Pitch Capabilities

In-Line: 45 um; Staggered: 60 um; Tri-Tier: 70 um ; Quad-Tier: 80um

Low k & Copper wafer capabilities available.

Fine Pitch Wire Bonding

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Page 9

Focus Packages - Bumping, WLCSP, FCBGA, SIP, SCSP and modified LF package

Small & Light - Thin ThicknessThin Thickness in Wafer, Substrate, Package- Fine PitchFine Pitch in Wire Bonding, Flip Chip Bond and

Solder Ball- High DensityHigh Density by Stacked Die, Package, Multi-

Substrate Layer,Substrate Stacked, Staggered Viaand Small Trace Via Hole Size

Good Thermal and Electrical Performance

- High Speed and Low Thermal ResistanceHigh Speed and Low Thermal Resistance- Cu / LowCu / Low--K waferK wafer, Nano-technology

Green - Green SolutionGreen Solution

Low Cost & Fast Time-to-market - 1212’’’’ Wafer CapacityWafer Capacity- Total Turnkey Solution - Matrix design, Multi-die, package Design - LAB Design SupportLAB Design Support

Trends of Packaging Technologies


Page 10




Integrated Design-- Components of Optimization PKG Design-- Advanced PKG Analysis Flow-- Plan and Actions for PKG Design

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Page 11

Challenges to PKG Integrated DesignAnalysis Challenges

Multi-port parameters analysis and broadband calibration skillDouble-side calibration and probing technologySignal-integrity, SSN/SSO and IP drop Mixed-signal analysisSubstrate On-line testing, like via, bump and ball……

Design Challenges to SiPPKG selection for different thermal/electrical requestSubstrate Design integrated thermal/electrical solution.

-- Embedded Die/passive, IPD, decoupling cap……PKG IP development.Design Guideline and constraint


Page 12

Analysis Case I : effective dielectric constant

Er = 3.2

Er = 6.0

What is the effective Er of this mixture material ?

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Page 13

VNA

Probe station

Sample

Long trace

Short traceshort trace

DUT: (Microstrip/Strip TL)same cross-section with different length

Analysis Case I : Measurement and ADS setup


Page 14

m4freq=Er_preg=3.828

2.358GHz

0.160.320.480.640.800.961.121.281.441.601.761.922.082.242.402.562.722.883.043.203.363.523.683.844.004.164.324.484.644.804.965.125.285.445.605.765.926.086.246.406.566.726.887.047.207.367.527.687.84

0.00

8.00

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

-1.0

4.5

freq, GHz

Er_p

reg

m4

m5freq=loss_tan1=0.011

4.985GHz

1 2 3 4 5 6 7 8 90 10

0.1

0.2

0.3

0.4

0.0

0.5

freq, GHz

loss

_tan

1

m5

2 4 6 8 10 12 14 16 18 20 22 240 26

-100

0

100

-200

200

freq, GHz

phas

e(S

(2,1

))ph

ase(

S(6

,5))

Effective dielectric constant

Loss tangent

Good Correlation between simulation and measurementOnce we have the accurate the dielectric constant of mixture material of substrate, we can achieve good electrical substrate design.

Sim/mea comparison

Analysis Case I : extraction result

Mea

Sim

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Page 15

Analysis Case II : Impedance Control Verify by TDR/TDR System

Design Condition:Substrate Type : 2 Layer

Impedance Control : Differential

Simulation Structure : Micro-Strip Line

Trace Width (W): 0.39mm

Trace Thickness (T): 22 um

Dielectric Thickness (T1): 200um

Separation (s): 0.15mm

Dielectric Layerε= 4.0

Signal Trace in 1st Layer

GND Plane in 2nd Layer

W

T

T1

S

TDR Measurement Result


Page 16

Trace width(um) separation(um) Zodd(ohm) Zeven(ohm) Single ended(ohm)Q2D 388.95(from drawing) 150(from drawing) 41.2 58.8 50.9

Q2D 429um 116um 38.1267 55.6689 47.5768/435um

TDR 429um 116um 42.4~42.8 61.7 52.3~53

Impedance comparison

Impedance Control -- Manufacture Result and comparison

SEM-single ended trace width measurement

SEM-differential trace width/space measurement

Design / Measurement Comparison

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Page 17

Chip capacitance

Open waveform

bare substrate

2202 T4failure good unit 2

good unit 1

Analysis Case III FA Application TDR of bare, good, and failure sampleTDR of bare, good, and failure sample

Slight difference on the chip capacitance charge curve –A possible reason of this phenomenon is the IMC makes the interface resistance between wire and bond pad growing, which causes the charge current different.

IMC


Page 18

Analysis Case IV : Ball pad effect analysis

Ball_Pad1

Ball_Pad3

Ball_Pad2

2 4 6 8 10 12 14 16 180 20

-20

-15

-10

-5

-25

0

freq, GHz

dB(B

all_

Pad1

_UP_

1112

..S(2

,1dB

(Bal

l_Pa

d2_U

P_11

12..S

(2,1

dB(B

all_

Pad3

_UP_

1112

..S(2

,1

Measurement Result Measurement Result Void PWR/GNG plane above the ball land on Layer3

No Void

Void layer3

Void layer2＆3

Void the plane above ball pad area at PWR/GND will reduce the capacitance,

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Page 19

Analysis Case V : PDS Analysis -- Measurement setup

Top view Bottom view

27mm

27mm


Page 20

Analysis Case V : Measurement and Simulation Result (Test Board only) Port 1

S21_dBS21_dB

Port 2

Field propagation @750MHz

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Page 21

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5Frequency (GHz)

-55

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5S 2

1 (d

B)

Bare PCBpackage onlyBGA and PCB

Effect of package

Noise coupling between PKG&PCb?

Analysis Case V : comparison with bare PCB, Package and BGA+PCB


Page 22




Integrated Design-- Components of Optimization PKG Design -- Advanced PKG Analysis Flow-- Plan and Actions for PKG Design

12


Page 23

Design Rule/Specfor substrate layout

Characterization Labcapability on Electrical,Thermal, Stress and Material

Components of Optimization Package Design

Pkg options:structure,cost,thermal,board level...

Substrate:laminate,build-up,ceramic,RLC embed

Wire &Bumping

Leadframe:L/F for SOP/QFP etc,L/F for BCC/QFN etc.

•Knowing ElectricalCharacteristics

deep inside•Provide package solutions

from advanced pkgtechnology


Page 24

Integrity Design Flow for Advanced PKG

Quasi-State EM Simulator•Whole PKG modeling extracting

High Frequency/Speed Simulator•3D Field solver•FTDT simulator•2.5D Momentum•PDS Simulator

Frequency Domain•VNA/PNA with PLTS/ADS

8722ES (40GHz, 2-port)8364B (50GHz, 4-port)

•Impedance Analyzer•Spectrum analyzer

Measurement Plane•Probe Station

Single-side 2-portDouble-Side Multi-port

•High Performance Probe (50GHz)•High Performance cable (50GHZ)

Time Domain•Time Domain Reflectometer

with TDA/•High Speed Pattern Generator

POST-Analysis Capability & Integrated plane•Broadband modeling•Signal Integrity (SI)•PDS analysis•EMI/EMC analysis•data flow control plane•PKG IP Development

System Integrity Analysis and Design Guide for

Advance Package

Software HardwareSubstrate Design / Pre-simulation•Design Guideline and Constraint

Simulation

Transfer interface

Design Constraint & PKG IP

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Page 25

Plan and Actions for PKG Design

Substrate Design Integrity Electrical Performance-Design Integrity Electrical performance flow -Design Rule and Constraint setting for SiP PKG Application,like RF Module, optical and wireless PKG

Active/Passive Device analysis capability-Embedded passive (RF-MEMS, Substrate embedded RLC) analysis and IP-development

-Sub-system measurement capability setting for advanced PKG

Co-Design and Co-development with key partners-Co-working with key partners for more close and detail study in Wireless, Optical or RF module


Page 26

ContactsContactsSamuel_Wu, Leader of Electrical LabE-mail: [email protected]: 886-7-3617131 ext. 15290/85290Fax: 886-7-3613094

Mark_Li, Project Engineer of Electrical LabE-mail: [email protected]: 886-7-3617131 ext. 15291/85291Fax: 886-7-3613094

ASE, Inc (Kaohsiung)26, Chin 3rd Rd., 811, Nantze Export Processing ZoneKaohsiung, TAIWAN

Website: www.aseglobal.com

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Page 27

THE END

Thank You For Your Listening

1


Feb.23, 2006Page 1

PNA Based Solutions

- Pulsed RF S-Parameter Measurements- Multiport Test Solutions- Physical Layer Test Systems

Agilent Technologies Ltd.

Ming-Fan, Tsai Project Manager

Feb, 23, 2006


Feb.23, 2006Page 2

Pulsed-RF S-Parameter Applications Using The Agilent PNA Series Network Analyzer

2

Page 3


Feb.23, 2006

Agenda• Why Measure in Pulsed Mode and the DUTs We Test

– Wafer Test– Power Amplifiers– Antenna RCS– T/R Modules

• Review of Pulsed Measurements• Wideband synchronous• Narrowband asynchronous

• Evolution of Pulsed VNAs from Agilent• 8510, 85108, 85120, CTS Platform to PNA

• Test Sets Available

Page 4


Feb.23, 2006

Why Test Under Pulsed Conditions?

• Device may behave differently between CW and pulsed stimuli• Bias changes during pulse might affect RF performance• Overshoot, ringing, droop may result from pulsed stimulus• Measuring behavior within pulse is often critical to characterizing

system operation (radars for example)• CW test signals would destroy DUT

• High-power amplifiers not designed for continuous operation• On-wafer devices often lack adequate heat sinking• Pulsed test-power levels can be same as actual operation

3

Page 5


Feb.23, 2006

On-Wafer Amplifier Test and Modeling

•Most applications are at microwave frequencies

•Devices lack adequate heatsinking for CW testing, so pulsed-RF used as a test technique to extract S-parameters

•Arbitrary, stable temperature (isothermal state) set by adjusting duty cycle

•Duty cycles are typically < 1%

•Often requires synchronization of pulsed bias and pulsed RF stimulus

Page 6


Feb.23, 2006

Wireless Communications Systems

• TDMA-based systems often use burst mode transmission

• Saves battery power

• Minimizes probability of intercept

• Power amplifiers often tested with pulsed bias

• Most of wireless communications applications ≤ 6 GHz

4

Page 7


Feb.23, 2006

Pulsed Antenna Test

• About 30% of antenna test involves pulsed-RF stimulus

• Test individual antennas, complete systems, or RCS

• RCS (Radar Cross Section) measurements often require gating to avoid overloading receiver

Page 8


Feb.23, 2006

Component-Level Characterization

• Accurate characterization of components such as amplifiers, mixers,filters, and antennas is critical for effective system simulation

• Pulsed-RF stimulus crucial for many components in A/D applicationssuch as AESA Phased arrays and the individual T/R Modules that are used in such systems

Transmit / Receive Module Receive Module

5

Page 9


Feb.23, 2006

Radar and Electronic-Warfare

•Biggest market for pulsed-RF testing

•Traditional applications ≤ 20 GHz

•Many now include Multi-Mode Ka-Band

•Devices include

• amplifiers• T/R modules• up/down converters

Pave-Paws AN/APG-81 JSF

AN/APG-79 F16C Block 60

Page 10


Feb.23, 2006






6

Page 11


Feb.23, 2006

VNA Pulsed-RF Measurements

Average Pulse

Magnitude and phase data averaged over duration of pulse

Point-in-Pulse

Data acquired only during specified gate width and position within pulse

VNA data display

Frequency domain

Frequency domain

Time domainPulse Profile

Data acquired at uniformly spaced time positions across pulse (requires a repetitive pulse stream) Magnitude

Phase

data point

Note: there may not be a one-to-one correlation between data points and the actual number of pulses that occur during the measurement

CWdB

deg

Swept carrier

Page 12


Feb.23, 2006

Pulsed-RF Data Acquisition (Time Domain View)

t

carrier freq

Trace point 1

Trace point 2

Trace point 3

Trace point 4

Trace point 5

Trace point 6

. . .

Freq 1Freq 2

Freq 3Freq 4

Freq 5Freq 6 . . .

Point-in-Pulse

Pulse Profile

t

gate delay

Trace point 1

Trace point 2

Trace point 3

Trace point 4

Trace point 5

Trace point 6

. . .

Delay 1Delay 2

Delay 3Delay 4

Delay 5Delay 6 . . .

Note: the number of pulses per data point varies with

PRF and IF bandwidth

Pulsed-RF

Gate

7

Page 13


Feb.23, 2006

Pulse-to-Pulse (Single Shot) Measurements

• Carrier remains fixed in frequency

• Measurement point in pulse remains fixed with respect to pulse trigger (requires wideband detection technique)

• One data point for each successive pulse, no pulses skipped

• Display magnitude and/or phase versus time

VNA data display Time domain

P1 P2 P3 P4 P5 P6 …

CW pulses

One data point for each successive pulse, no pulses skipped

Page 14


Feb.23, 2006

Pulsed S-parameter Measurement ModesWideband/synchronous acquisition

• Majority of pulse energy is contained within receiver bandwidth• Incoming pulses and analyzer sampling are synchronous

(requires a pulse trigger, either internal (8510) or external (PNA)• Pulse is “on” for duration of data acquisition• No loss in dynamic range for small duty cycles (long PRI's),

but there is a lower limit to pulse width

Receiver BW

Pulse trigger Time domainFrequency domain

8

Page 15


Feb.23, 2006

10 MHz Ref

Typical Hardware Setup For Wideband DetectionPoint-in-Pulse and Pulse-to-Pulse

Output 1

Src OutRef In

Cplr Thru

DUT

Output 2

To TRIG IN (rear panel)

External pulse generator (e.g., 81110A/81111A)

Z5623A H81 2-20 GHz RF modulator

PNA (20, 40, 50, or 67 GHz) with:• 014 Configurable test set• UNL Source attenuators• 080 Frequency offset mode

Note: pulse generator controls timing

Additional PNA setup:• step sweep• frequency offset on (0 Hz)• Auto IF gain = off

Page 16


Feb.23, 2006

Alternate Hardware Setup For Wideband Detection

Output 1

Src OutRef In

Cplr Thru

DUT

Output 2

TRIG OUT (rear panel) to pulse gen EXT INPUT

External pulse generator(e.g., 81110A/81111A)


PNA (20, 40, 50, or 67 GHz) with:• 014 Configurable test set• UNL Source attenuators• 080 Frequency offset mode

Additional PNA setup:• step sweep• frequency offset on (0 Hz)• Auto IF gain = offNote: PNA controls timing

10 MHz Ref

9

Page 17


Feb.23, 2006

Minimum Pulse Widths for Point-in-Pulse Measurements Using Wideband Detection

No2 us600 kHzPNA-L models(2-port, 6, 13.5 GHz; 4-port, 20 GHz)

Yes10 us250 kHzPNA-L models(2-port, 20, 40, 50 GHz)

Yes50 us40 kHzPNA models(20, 40, 50, 67 GHz)

IF auto-gain mode*

Minimum pulse width

Maximum IF bandwidth

* Note: for point-in-pulse measurements, the IF auto-gain mode should be turned off (i.e., set IF gains manually)

Page 18


Feb.23, 2006

P1 P2 P3 P4 P5 P6 …

CW pulses

Fastest PRI/PRF for Pulse-Pulse Measurements Using Wideband Detection

25 kHz40 us600 kHzPNA-L models(2-port, 6, 13.5 GHz; 4-port, 20 GHz)

12.5 kHz80 us250 kHzPNA-L models(2-port, 20, 40, 50 GHz)

5.9 kHz170 us40 kHzPNA models(20, 40, 50, 67 GHz)

Maximum PRF

Minimum PRI

Maximum IF bandwidth

Conditions: point sweep; external trigger, CW sweep; IF autogain=off

PRI

10

Page 19


Feb.23, 2006

Pulsed S-parameter Measurement Modes

Narrowband/asynchronous acquisition• Extract central spectral component only; measurement appears CW• Data acquisition is not synchronized with incoming pulses (pulse trigger not required)• Sometimes called “high PRF” since normally, PRF >> IF bandwidth• “Spectral nulling" technique achieves wider bandwidths and faster measurements• No lower limit to pulse width, but dynamic range is function of duty cycle

IF filter

IF filter

Time domain

Frequency domainD/R degradation = 20*log[duty cycle]

Page 20


Feb.23, 2006

-3 -2 -1 0 1 2 3

x 104

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Filtered Output Using Spectral Nulling

Pulsed spectrum Output

X

-3 -2 -1 0 1 2 3

x 104

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Digital filter (with nulls aligned with PRF)

• With “custom” filters, number of filter sections (M) can be chosen to align filter nulls with pulsed spectral components

• With spectral nulling, reject unwanted spectral components with much higher IF bandwidths compared to using standard IF filters

• Result: faster measurement speeds!

11

Page 21


Feb.23, 2006

Typical Hardware Setup(Narrowband)

Output 1

10 MHz Ref

Src OutRef In

Cplr Thru

DUT

Output 2

Pulse 2 drive to PULSE IN B (for point-in-pulse measurements)

External pulse generator(e.g., 81110A/81111A)


PNA (20, 40, 50, or 67 GHz) with:• 014 Configurable test set• UNL Source attenuators• 080 Frequency offset mode• 081 Reference switch• H11 IF access• H08 Pulsed-RF measurement capability• 016 Receiver attenuators (optional)

PNA

Option H08 VB application/DLL

GPIB

Page 22


Feb.23, 2006






12

Page 23


Feb.23, 2006

85108A

First True pulsed Network Analyser

Still the most widely used system for TR Module R&D and manufacturing test (>100 off world-wide still in use)

Wholly COTS solution

Affordable

Low cost of ownership

Low risk

Point-on-pulse

Pulse profile, repetitive

Page 24


Feb.23, 2006

Pulsed PNA is the New Generation 85108A

COTS stand alone hardware can perform:

– Point-on-pulse– Pulse-to-Pulse– Pulse profile

Timing generator can trigger custom user hardware e.g.

TR Module controller

Very much faster measurement speed

13

Page 25


Feb.23, 2006

Comparing the 8510 and PNA8510 (85108A)• Dominant mode is wideband detection

• Detection is done BEFORE analog-to-digital conversion

• Analog synchronous detector produces baseband I/Q output(detector bandwidth = 1.5 MHz)

• Pulse profiling achieved by varying sample point of baseband pulses

• Trade off speed and dynamic range with averaging

PNA• Dominant mode is narrowband detection

• All processing (filtering and detection) is done digitally

• Widest bandwidth = 35 kHz

• Pulse profiling achieved with analog switches that gate IF (or RF) signals

• Trade off speed and dynamic range with variable IF bandwidths and averaging

PNA-L• Dominant mode is wideband detection• All processing (filtering and detection) is done digitally

• Widest bandwidth = 600 kHz

• Trade off speed and dynamic range with variable IF bandwidths and averaging

Page 26


Feb.23, 2006

Agilent TR Module Test Systems

85120A S10 Family 84000A Family

14

Page 27


Feb.23, 2006

Agilent TR Module Test Systemscontinued

CTS-I Family CTS-II Family

Page 28


Feb.23, 2006

Pulse Summary

AveragePoint-in-pulsePulse profile

AveragePoint-in-pulse Pulse profilePulse-to-pulse

Measurements

H11/H08***None requiredPNA Options

PW > 20 ns (limited by IF gate)PW > 50 us/10 us/2 us**PNA

Limited* (High PRF Mode)PW > 1 us8510

Dynamic range loss with small duty cycles

No pulse-to-pulse

Lower pulse width limit

Elevated noise floorDisadvantages

Narrow pulse widthsConstant dynamic rangeAdvantages

Narrowband/AsynchronousWideband/Synchronous

* No nulling, no point-in-pulse** PNA/PNA-L 2-port 20, 40, 50 GHz/PNA-L 2-port 6, 13.5, 4-port 20 GHz*** Option H08 is usually used in conjunction with Option H11. Without H11, the user can perform average pulse, or point-in-pulse

measurements using external RF gates.

15

Page 29


Feb.23, 2006







Feb.23, 2006

Z5623A Hxx RF Modulators• Z5623A H81 (2-20 GHz)

• Expected to be most common configuration ($43K)• Contains pin switch, amplifier, directional coupler• Use jumpers to bypass internal amp or use high-power external amp

• Other quoted test sets:• Z5623A H83 1-20 GHz Bidirectional (two pin switches) $80K• Z5623A H84 20-40 GHz Bidirectional (two pin switches) $105K• Z5623A H85 20-40 GHz Unidirectional, no amplifier $35K• Z5623A H86 2-40 GHz Unidirectional, dual band (incl. band switch) $65K

• Customization via Agilent’s “Special Handling” group:• Different frequency ranges • No amplifier or higher power amplifiers• High power components

Z5623A H81

16


Feb.23, 2006

PNA Pulsed-RF Configuration Example 1

• User-supplied external modulator• Average pulse measurements

TTL

10MHz Ref

Cplr Thru

Src Out

+25 -25Com

DC(-)DC(+)

RF out

RF inPower Supply

Pulse out

Advantage: simplest – use any standard PNA with 014GPIB

81110A family pulse generator

Page 32


Feb.23, 2006

One output channel drives RF modulator

Src Out

Ref In

Three output channels drive internal receiver gates A, B, and R1 for point-in-pulse and pulse-profile measurements

10 MHz Ref

GPIB

Trigger

DUT

Z5623A H81 pulsed-RF test set

PNA

81110A family pulse generators


Advantages: • easily make point-in-pulse and

pulse profile measurements• more sophisticated RF

modulator boosts port power

• Modulator test set, internal receiver gates• Point-in-pulse, pulse profile of S21 and S11

17

Page 33


Feb.23, 2006

PNA Pulsed-RF Configuration Example 3:Full Forward/Reverse S-Parameter Configuration

Three output channels drive internal receiver gates A, B, and R1/R2 for point-in-pulse and pulse-profile measurements

One output channel drives RF modulator

10 MHz Ref

GPIB

Trigger

DUT

PNA


Page 34


Feb.23, 2006

PNA Pulsed-RF Configuration Example 3:Full Forward/Reverse S-Parameter Configuration a different view

18

Page 35


Feb.23, 2006

Z5623A H83 – H84 Test Set Control Macro

Page 36


Feb.23, 2006

Z5623A H83 RF Modulator 1-20 GHz

12

3 4

10/20/30

60 dB

12

3 4

12

3 4

1 2

34

10/20/30

60 dB

1 2

34

1 2

34SW1

SW2 SW3

ATN1 ATN2

CPLR1 CPLR2

16 dB 16 dB

SW4

SW5SW6

SW8SW 7

SourceIN

RCVRR1 IN

RCVRR2 IN

CPLRTHRU

CPLRTHRU

SourceIN

PulseOut

PulseOut

CPLRIN

AMPOUT

SourceOUT

AMPIN

Pulse 2IN

Pulse 1IN

CPLRIN

SourceOUT

AMPIN

AMPOUT

AMP 1TERM

AMP 1TERM

AMP 2TERM

AMP 2TERM

FilterIN

FilterIN

0

RCVR R1 OUT AMP IN

AMP OUTCPLR THRU

SOURCE IN

SOURCE OUT

CPLR IN

FILTER IN

PULSE OUT

PULSE 1IN

RCVR R2 OUTAMP IN

AMP OUT CPLR THRU

SOURCE IN

SOURCE OUT

CPLR IN

FILTER IN

PULSE OUT

PULSE 2IN

LINE

1

Z5623AH83 PULSE TEST SET, 1 GHz to 20 GHz

TTL 0,5 VDC, 10K OHM

PORT STATUS "GPIB ONLY"

AVOID STATIC DISCHARGE

CAUTION: SEE MANUAL FOR MAXiMUM POWER RATINGS CAUTION: SEE MANUAL FOR MAXiMUM POWER RATINGS

0

19

Page 37


Feb.23, 2006


Pulse1 out

10 MHz Ref

Src Out

• Modulator test set, external receiver gate • Point-in-pulse, pulse profile

Ref In

+25 -25Com

Power SupplyTTL

DC(-)

DC(+)

Pulse2 out

GPIB

External switch in receiver B loop for external gating

Advantage: gate widths < 20 ns81110A family pulse generator

Z5623A H81 pulsed-RF test set

Page 38


Feb.23, 2006


Pulse1 out

+25 -25Com

Power Supply

• User-supplied pulsed bias to amplifier, internal IF gate• Point-in-pulse, pulse profile

Pulse2 drive to internal receiver gates (for point-in-pulse)

CW Pulsed-RF

Advantage: pulsed bias to amplifier (with CW input)

10 MHz Ref

GPIB

81110A family pulse generator

20

Page 39


Feb.23, 2006


Cplr Thru

Src Out

RF out

RF in

• Customer-supplied pulsed bias and pulsed RF, internal IF gate• Point-in-pulse, pulse profile

Pulse1 out

Power Supply

+25 -25Com

Trigger

Pulse3 drive to internal receiver gate B (for point-in-pulse)

Pulse2 outTTL

DC(-) DC(+)

Advantage: both pulsed bias and pulsed-RF stimulus

10 MHz Ref

GPIB


Page 40


Feb.23, 2006

Summary

• Testing with pulsed-RF is very important for radar, EW, and wireless comms systems

• Narrowband detection:• Spectral nulling technique improves measurement speed

• For radar and wireless comms applications, offers superior dynamic range/speed

• No lower limit to pulse widths

• Although the PNA uses different hardware and detection techniques than the 8510, measurement results are essentially the same!

• PNA also offers numerous platform benefits:• Measurement flexibility (32 channels, 64 traces, 16 windows, 16,001 points)

• Connectivity (LAN, USB, …)

• Automation (open Windows®, COM, SCPI …)

• Ease of use (built-in HELP, Cal Wizard, ECal …)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

7.74

7.99

8.24

8.49

8.74

8.99

9.24

9.49

9.74

9.99

10.2

4

10.4

9

10.7

4

10.9

9

11.2

4

11.4

9

11.7

4

11.9

9

12.2

4

12.4

9

12.7

4

Frequency (GHz)

S21

(dB

)

PNA8510

21

Page 41


Feb.23, 2006

Resources• www.agilent.com/find/pulsedrf


Feb.23, 2006Page 42

Multiport - PNA based solutions

22

Page 43


Feb.23, 2006

Agenda

• Target Applications

• PNA Multiport Test Solutions

• Specials vs. Standard product

• Customer data required for new multiport specials

• Further Information

Page 44


Feb.23, 2006

Target Applications

• Front End Module (FEM)• Cellular FEM (see next slide)• WLAN FEM (Base Band not included, 2.4G & 5G dual band)• Filter array (see next slide)

– Multiple filter in single package– Duplexer/Coupler array (see next slide)– Multiple Duplexer/Coupler in single package

• High Frequency Multiport devices– Triplexer, power splitter, multiport coupler etc.– RF module, RF switch IC

• High power device testing

23

Page 45


Feb.23, 2006

Cellular FEM #1 (Dual band, 1xEV,GPS)

Diversity Rx

Page 46


Feb.23, 2006

Cellular FEM #2 (Quad band, UMTS,GSM)

24

Page 47


Feb.23, 2006

WLAN FEM（2.4G・５G dual band）

2.4 GHz Rx

5 GHz Rx

2.4 GHz Tx

5 GHz Tx

Diversity SW

Diplexer

PA

BPF

LNA

2.4 GHz / 5 GHz WLAN FEM

Page 48


Feb.23, 2006

Multiport & High Power Testing Devices

• Typical High Frequency devices– Switches, Couplers, Power Splitter/Divider and etc..– Filter/Coupler array

• Multiport and high power– PA Cellular/WLAN FEM with PA– RF switch IC ( Switch filters)

25

Page 49


Feb.23, 2006

Key Measurement Requirements

Cellular FEM without PA• IL, RL for each path up 12.75GHz• Isolation

– Frequency > 3x Carrier– Signal level 0dBm or –10dBm

• Switch distortion– Frequency up to 12.75GHz in R&D– Signal Level up +36dBm

UMTS850 UMTS1900

GSM Tx

Page 50


Feb.23, 2006

Key Measurement Requirements

WLAN FEM with PA– Gain, 1dB Compression, Pout,PAE– RL– Isolation– Harmonics distortion

• Frequency Cellular > 3x Carrier Frequency• Frequency（WLAN）: 17.4GHz• Power : 25dBm(WLAN)

36dBm(GSM/Mobile)

2.4 GHz Rx

5 GHz Rx

2.4 GHz Tx

5 GHz Tx

Diversity SW

DiplexerPA

BPF

LNA

26

Page 51


Feb.23, 2006

Agenda






Page 52


Feb.23, 2006

New PNA Rev 6.0 Firmware (Available December 2005)

Sets GP-IB address, or Test Set IO address

Set control lines (if test set has them)on a per channel basis

Set physical ports in ANY order

Select Testset Control File base on test set

New Functionality:• External test set control• “Any 2-port” capability

27

Page 53


Feb.23, 2006

PNA/PNA-L Option 550

• New firmware option 550 for the PNA/PNA-L adds full 4-port capability and differential measurements to a two port network analyzer

• CPL Dec 1, 2005

• $7k RFP

ApplicationsReceiversBalancedSParameterMeasure

Page 54


Feb.23, 2006

Hybrid

Variety Summary

Signal Conditioning

Switching

Special Multiport Test VarietiesSpecial Multiport Test Varieties

Extension

SCMM

28

Page 55


Feb.23, 2006

Test Sets Overview

Platform Description Benefits87050A-Hxx/Kxx Switching test sets. Lower cost

No coupler inside test set

N4419/20/21B/H67 Extension test sets 4-port differential to 67GhzCoupler on each port

Z5623A-Hxx/Kxx Depend on the particular option Meets customer specific req’ts

Mixing of Switching and Extension

test sets

Page 56


Feb.23, 2006

Agilent’s Promoted Multiport Products & Specials

29

Page 57


Feb.23, 2006

Agilent PNA > 4-port Products offeringFreq. Coverage: PNA Based Unit & Ext. Test set Total Test Ports300 KHz – 20 GHz N5230A opt. 245 & Z5623AK64 6300 KHz – 20 GHz N5230A opt. 245 & Z5623AK66 14300 KHz – 20 GHz N5230A opt. 245 & Z5623AKxx 20.010 – 40GHz E8363/4B or E8361A & 87050A-K62* 6

* 2-port cal only

Page 58


Feb.23, 2006

Multiport Specials – Variety

• Extension Test Sets– Extension test sets provide signal paths from the network analyzer access

ports to the test set. All test ports to the DUT are Coupler or Bridge base. Provides greater sensitivity.

30

Page 59


Feb.23, 2006


• Hybrid Test Sets– Hybrid test sets are a combination of the switching and extension types.

Test ports can be either switched or coupler bridge based.

Page 60


Feb.23, 2006


• Switching Test Sets– Switching test sets provide signal paths from the network analyzer test ports

to the DUT.

J15

A3 DriverDaughter

BoardA2 Controller

Interface MotherBoard

A1PowerSupply

Port 3

Port 1

Port 2

Reflection(Type-N)

C

A4 LCDController

Board

w22 w23

Transmission(Type-N)

J10-

J15,

J50-

J57

GPI

BJ1

w5

w4

w2

w3

w6w7

w8w9

w14w15

w16

w17

w21w20

w19

w18w13

w12w11

w10

w1 w1 w1 w1 w1 w1 w1 w1

J13

J12

J11

J10

J14

J10-J1587050-60055

J50-J57

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

C C C C C C C

Port 6

Port 4

Port 5

Port 8

Port 7

(Type-N)

Sw15

Sw13 Sw12 Sw11 Sw10

Sw14

Sw50 Sw51 Sw52 Sw53 Sw54 Sw55 Sw56 Sw57

2

3

6532 65326532

2

3

Z5623A Option H48

1

6532

Z5623-60013

J74-J79

2 3 4 5 6 7 8 9

Open / CollectorLines

87050-60053

J54

J53

J52

A3 DriverDaughter

BoardA2 Controller

Interface MotherBoard

A1 PowerSupply

R3R1 R2Reflection

12

C6C1

C

A4 LCDController

Board

Transmission

C

J50-

J55

GPI

BJ1

C2 C3 C4 C5

A T1 T2/3

12S50

2S55

C

S51

C

S5412

1 2S52

20052 20053

12S53

20054

20051

20057

2005620055

20061 20062

20058

20059

20060

C C

C

J50

J55

J51

Z5623-60013

Z5623-60012

J74-J79

2 3 4 5 6 7 8 9

Open / CollectorLines

1

(Type-N)

Z5623A Option H46

1

31

Page 61


Feb.23, 2006


• SCMM– Single connection multiple measurement test sets allow the user to make

different types of measurements with out having to disconnect there DUT form the test set.

Power Supply

Display LCD Board

Controller Interface Mother BoardDriver Daughter Board

1 2 3 4 5 6 7 8 9 10 11 12Test Ports

Aux1 Aux2

Agilent 8720D Option K22Multi-Function Switch Matrix

B i/p 4-1A i/p 1-4

SW 50 SW 61

SW 12 SW 11

SW 13SW 10 SW 15 SW 14 SW 16 SW 17

1 1 1 1 1 1 1 1 1 1 1 1 222222222222

1 25 6 4 3 1 25 6 4 3 1 25 6 4 3 1 25 6 4 3

4 15 3 2 6 1 2 4 36 5

6 32 5 5 36 2

Page 62


Feb.23, 2006


• Signal Conditioning– Test sets that require couplers, attenuators, amplifiers, filters and mixers that may or

may not directly connect to the DUT.

R2

R1

P1

A

B

RF IF

LO

RF

IF

LO

P2

M1

Z5623A Opt H61

DUT MIXERisolator

Normal Mode

Source OUT PNA

Coupler IN

B OUT

B IN

Source INPNA

CouplerOUT

B IN

B OUT

LO DUTPORT

Source

LO INPORT

Up/DownFilter/Mixer

IN

IN

OUT

OUTFilter/Mixer

LO EXTOUT

IN

32

Page 63


Feb.23, 2006

Agenda






Page 64


Feb.23, 2006

Multiport Specials – Why Specials?

• Offer solutions for applications which can not be addressed with existing or standard products

• Increase sales of CTD standard products• Leverage standard platforms & OF capabilities to develop product extensions• Fastest development-shipment time for new opportunities & competitive

battles• Helps to identify market needs and trends of specific applications

33

Page 65


Feb.23, 2006

Multiport Specials –Specials vs. Standard product

Multiport Special – Custom– Does not follow the NPI PLC process– Fast development to shipment– Typical supplemental performance– Provide just enough performance• Functional Certificate• Return to Factory support

Standard Product– Follows the NPI PLC process– Specifications with uncertainties. – Box and System level performance• Calibration Certificate• Return to Bench support• Verification test

Page 66


Feb.23, 2006

Multiport Specials –Test Set vs. System PerformanceMultiport Test Set

• Typical supplemental performance specifications of the test set.

• Measures the Insertion Loss, Port Match, and path Isolation between ports.

• Provide just enough performance• Functional Certificate

System Level (PNA and Test Set)• Raw or Corrected system performance is not

provided.• Customers must take into consideration the

performance of the PNA, Test Set, cabling, fixtures, and other peripherals to characterize their system level performance.

• Once established that system level performance meets the application requirements. The customer can now define the PNA Multiport Test Solution and calibrate the system.

• The customer can define a system verification method by using either a golden standard or by establishing an additional type of verification process.

34

Page 67


Feb.23, 2006

Agenda






Page 68


Feb.23, 2006

Multiport Qualification Form

Qualification Form for Multiport Device

Device Description and Specifications Describe the device and application (please attach block diagram of device) ________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________ Number of device ports: ______ Port impedance: ___ 50 ohms ___ 75 ohms Connector type(s):__ Type N __SMA __ 3.5 mm __ 2.4 mm __ 1.85mm __ other (if other, please explain) ___________________________________________________ Specify the frequency range of the device: _____________________________________ Specify the frequency range required for the device application: ____________________ Specify required test port power: _____________________________________________ Specify Insertion loss / gain of the device paths: _________________________________ ________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________ Specify Isolation of other device ports: ________________________________________ ________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________ Specify Port matches of the device: ___________________________________________ ________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________ Specify desired measurement uncertainty: _____________________________________ ________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________ Specify other measurement requirements: ______________________________________ ________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________ If desired test system is complex (e.g. includes other analyzers, additional sources, etc), include block diagram of overall test setup.

• Most >4-port applications unique

• Define customer needs upfront

• Reduces time to quote and minimizes error

FE/AE fill out with customer and email back to CTD/Say Phommakesone

Page 1 of 4

35

Page 69


Feb.23, 2006

Agenda






Page 70


Feb.23, 2006

Information Sources

Freq. Coverage: Ext. Test Set & #Ports300 KHz – 20 GHz Z5623AK64 2-port300 KHz – 20 GHz Z5623AK66 10-port.45 – 20/40/50 GHz N4419/20/21B 2-port.45 – 67.0 GHz N4421BH67 2-port

http://mktwww.soco.agilent.com/Product-Info/Network-Analyzers/PNA/multiport.htm

http://www.agilent.con/find/multiport

http://www.agilent.con/find/PNA

Agilent Test Solution for Multiport and Balanced Devices 5988-2461EN

Agilent PNA Series Configuration Guide 5988-7989EN

36

Page 71


Feb.23, 2006

Summary

• PNA multiport test solutions provide: – Direct test set control made easy with PNA Firmware Rev 6.0s – Flexible test port configuration that enables customer to perform variety kinds

of multiport device measurements– Advanced measurement capabilities, such as the APE, result in accurate

measurements

Page 72


Feb.23, 2006

presented by:

Ming-Fan, TsaiAgilent Technologies Ltd.

Complete Characterization of Backplane Differential

ChannelsFebruary 23, 2006

© Copyright 2003 Agilent Technologies, Inc.

37

Page 73


Feb.23, 2006

Overview

Backplanes

Measurement set up

Single-ended

Differential

Frequency & time domain

Eye diagrams

Model extraction

Page 74


Feb.23, 2006

All Next Generation High Speed Serial Links will use Differential Signaling

Serial ATA 1.25 Gbps

Hypertransport 1.6 Gbps

AGP8x 2.1 Gbps

Infiniband 2.5 Gbps

PCI Express 2.5 Gbps

Serial ATA II 2.5 Gbps

XAUI 3.125 Gbps

PCI Express II 5.0 Gbps

OC-192 9.953 Gbps

10 GbE 10 Gbps

OC-768 39.81 Gbps

38

Page 75


Feb.23, 2006

Important Physical Layer Properties of Differential Channels

Differential impedance profile (diff return loss)

Transmitted differential signal quality (diff insertion loss)

Conversion of differential to common signal

Where conversion of differential to common signal occurs

Eye diagrams (1 Gbps 10 Gbps)

Page 76


Feb.23, 2006

Measurement System for Complete Physical Layer Characterization

GigaTest Labs Probe Station

Agilent Physical Layer Test System

Device Under Test(backplane)

39

Page 77


Feb.23, 2006

Differential VNA/TDR Applied to All Passive, Linear Components and Interconnects

When an external precision signal is requiredApplies to any passive interconnect or component

BackplanesDiscretesPackagesConnectorsPCB structuresMaterial properties

Page 78


Feb.23, 2006

A Precision Instrument is Not Enough!

Component to characterize

Instrument Valuable information? ?

40

Page 79


Feb.23, 2006

Complete Characterization System Solution

DUT + microprobes

GigaTest Probe Station

Physical Layer Test System: VNA + PLTS software

Page 80


Feb.23, 2006

Microprobes Allow Precision Probing of Structures with Minimal Artifacts

Pitch ~ 50µ – 1000µ

Close up

41

Page 81


Feb.23, 2006

4 Port Differential VNA Techniques Applied to Tyco Electronics HM-Zd Legacy Backplane System

16 inches, 30 inches backplane

2 inches, daughter card

2 inches, daughter card

Total channel lengths: 26 inches, 40 inches

Page 82


Feb.23, 2006

4 Port Single-ended S-parameters

1

3

2

4(and their return paths!)

44434241

34333231

24232221

14131211

SSSSSSSSSSSSSSSS

Stimulus

Res

pons

e Interpreting single ended measurements:S11 : return loss, single endedS21= S12 : insertion loss, single endedS31= S13 : near end cross talkS41= S14 : far end cross talk

in

outin,out P

PS =

42

Page 83


Feb.23, 2006

DUTIncident wave

Reflected wave

Transmitted wave

S11

S21

Incident wave

Reflected wave

Transmitted wave

TDR

TDTt

t

DUT

TDR and VNA Techniques

Page 84


Feb.23, 2006

4 Port, Single-ended S-parameters: Tyco Backplane Example

Interpreting single ended measurements:S11 : return loss, single endedS21= S12 : insertion loss, single endedS31= S13 : near end cross talkS41= S14 : far end cross talk

43

Page 85


Feb.23, 2006

Single-ended Return Loss and Insertion Loss: 26 inch channel length

2 GHz/div

0 dB

Input Single-ended Return Loss S11

2 GHz/div

-10 dB

-20 dB

-30 dB

-40 dB

-50 dB

Input Single-ended Insertion Loss S21

Page 86


Feb.23, 2006

Microprobing on SMA Pads

Added ground pad

44

Page 87


Feb.23, 2006

Bandwidth Limit of SMA vs. Microprobes

Measured with SMA connector

Measured with microprobe

Conclusions:

1. Microprobes can be higher bandwidth (important > 14 GHz)

2. Identical performance < 10 GHz for these SMA connectors

20 GHz full scale

S11- return loss0 dB

-10 dB

-20 dB

-30 dB

-40 dB

-50 dB

Page 88


Feb.23, 2006

Design for Test (DFT):Optimized Pad Design for Micro-probing

Any signal via can be used as a probe point

Use a “copper fill” around the signal via with immediate connection to all adjacent ground vias

Every board should be designed with pads for optional microprobing- no impact on function

Ground vias shorted to the copper fill

45

Page 89


Feb.23, 2006

Microprobing vs. SMA Connectors

• Probe station required

• Probes can be damaged

• Can use on any signal lines

• No constraints on how many or where

• Can be used on functional board

• Important for active probing

Micro Probes

• Can’t use on functional boards- loads the line too much

• Limited density

• No additional fixturing to VNA required

• Easy to use

• Mechanically robust

SMA Connectors

WeaknessesStrengths

Page 90


Feb.23, 2006

Two Important Transformations Facilitate First Order Analysis

From single-ended S-parameters to differential S-parameters

From frequency domain to time domain

46

Page 91


Feb.23, 2006

4 Port Balanced Measurements:Frequency and Time Domain

Port 2Port 1Port 2Port 1

Common SignalDifferential Signal

Stimulus

22CC21CC22CD21CD

12CC11CC12CD11CD

22DC21DC22DD21DD

12DC11DC12DD11DD

SSSSSSSSSSSSSSSS

1

3

2

4

Single-ended

(and their return paths!)

44434241

34333231

24232221

14131211

SSSSSSSSSSSSSSSS

Stimulus

Res

pons

e

Diff pair port 1

Diff pair port 2


Differential

Page 92


Feb.23, 2006

The Meaning of the Quadrants

22CC21CC22CD21CD

12CC11CC12CD11CD

22DC21DC22DD21DD

12DC11DC12DD11DD

SSSSSSSSSSSSSSSS

Differential in, differential out:Behavior of differential signals

Common in, common out:Behavior of common signals

Differential in, common out:Behavior of mode conversion

Common in, differential out:Behavior of mode conversion



Stimulus

47

Page 93


Feb.23, 2006

22CC21CC22CD21CD

12CC11CC12CD11CD

22DC21DC22DD21DD

12DC11DC12DD11DD

SSSSSSSSSSSSSSSS



Stimulus

Diff pair port 1

Diff pair port 2


Signal quality of the common signal, time delay of common signalSCC21

Common impedance profileSCC11

Conversion of common signal to differential signal in transmission (susceptibility)

SDC21

Conversion of differential signal to common signal in transmission (emissions)

SCD21

Signal quality of differential signal, time delay of differential signalSDD21

differential impedance profileSDD11

Important Performance Terms

Page 94


Feb.23, 2006

Single-ended to Differential S-parameters

Single-ended S-parameters Differential S-parameters

Note: One measurement with Physical Layer Test System yields above information

48

Page 95


Feb.23, 2006

Differential Return Loss & Reflection Coefficient

Conclusions-Connectors create large impedance discontinuity-Daughter card differential impedance is 110 Ω-Backplane differential impedance is 102 Ω

0 dB--

-50 dB--

20 GHz full scale

Frequency Domain SDD11

1 nsec/divt = 0

Time Domain TDD11

100 Ω−80 Ω−

120 Ω−

Page 96


Feb.23, 2006

Single-ended and Differential TDR

t = 0

Single-ended TDR(NOT odd mode impedance)

50 Ω

1 nsec/div

inside connector

60 Ω

Via fields on either side of connector

Backplane trace

1 nsec/div

Differential TDR

100 Ω120 Ω

Coupling brings differential impedance down

49

Page 97


Feb.23, 2006

Important Design Feedback

Designing for 50 Ohm single ended line is not the same as a 100 Ohm differential line.

Characterizing with single ended TDR will not measure differential impedance.

Design the daughter cards with as much care as the backplane.

Most discontinuities from connectors are not from the connectors- they are from the via fields.

Optimizing connectors is all about optimizing the circuit board via field layout.

Design for test: add copper fills for microprobing

Page 98


Feb.23, 2006

Differential TDR from Both Ends

TDD11 TDD22

similar connector, reduced bandwidth

1 nsec/div 1 nsec/divmirrored

Port 1 Port 2

100 Ω

50

Page 99


Feb.23, 2006

Differential Transmitted Signal SDD21

Conclusions:

• Measurement system bandwidth > 40 GHz

• 26 inch traces have a 15 dB BW ~ 3.5 GHz

• 40 inch traces have a 15 dB BW ~ 2 GHz

10 GHz full scale

0 dB--

-100 dB--

26 inch backplane trace

40 inch backplane trace

-10 dB--

-20 dB--

Frequency Domain SDD21

Page 100


Feb.23, 2006

Differential Transmitted Signal: Time Domain TDD21

1 nsec/div

40 GHz bandwidth, ~20 psec input rise time

Total of 26 inches

Total of 40 inches

51

Page 101


Feb.23, 2006

Eye Diagrams: 26 inch Channel

1 Gbps, 200 psec/div 2.5 Gbps, 80 psec/div

5 Gbps, 40 psec/div 7.5 Gbps, 27 psec/div

Page 102


Feb.23, 2006

Non-ideal Differential Signaling: Mode Conversion

Anything that affects one line and not the other will convert differential signal into common signal

Drive is asymmetrical between channels • skew• output impedance and launched voltage Signal environment in interconnect is asymmetrical• different characteristic impedance in each leg• length is different• loading from connectors, jags, pads, ground planes

Real problem of common signal is EMI from unshielded twisted pair

52

Page 103


Feb.23, 2006

Differential Signal Input Common Signal Output

~7% of differential signal amplitude converted to common signal

May be a problem if it were on CAT5 twisted pair

TDD21

TCD21, 20x scale

1 nsec/div

26 inch channel length

Page 104


Feb.23, 2006

Where did the Conversion Happen?

TCD11 x10 scale increase

Via field on daughter card

Via field on mother board

asymmetry of backplane traces

Conclusion: most mode conversion happens in the

via fields!

TDD11

53

Page 105


Feb.23, 2006

Measurement and Model Extraction

AGILENT TECHNOLOGIESPNA SERIES

VECTOR NETWORK ANALYZERS

TIME DOMAIN SIMULATORS(HSPICE®, SPECTRAQUEST®, SMARTSPICE)

FREQUENCY-DOMAIN SIMULATORS(ADS, ETC)

AGILENT TECHNOLOGIES86100-SERIES

TIME DOMAIN REFLECTOMETERS

AGILENT TECHNOLOGIESN1900-SERIES

PHYSICAL LAYER TEST SYSTEM

TDA SYSTEMS ICONNECT MEASUREXTRACTOR

S-PA

RAM

ETER

S TOPO

LOGI

CAL

MOD

ELS

DEVICE UNDER TEST

S-PARAMETERS

DEVICE UNDER TEST

BEHA

VRIO

ALM

ODEL

S

TIM

E DO

MAI

N

TDR or VNA

Note: TDR is NEW measurement engine for PLTS v1.2

Note

See Note

Page 106


Feb.23, 2006

Modeling Example with PLTS & IConnect

54

Page 107


Feb.23, 2006

Conclusions

Differential pairs will proliferate

Differential characterization requires • microprobes • probe station• 4 port VNA• Analysis softwareAbsolutely everything you ever wanted to know about the performance of a differential pair is contained in the 4 port balanced S parameters-displayed in either the frequency or time domain

Page 108


Feb.23, 2006

Visit www.gigatest.com for..

• More than 100 application notes on high speed design• Schedule of signal integrity short courses• High-bandwidth measurement and modeling services• Complete signal integrity characterization systems

Technical Information Resources

• Visit www.agilent.com/find/plts for..• Physical Layer Test System data sheet & user’s guide• Signal integrity solutions brochure• XAUI backplane design case study• PCI Express tools brochure• N1900 series product flyer

Contact Gigatest Labs for more information....www.gigatest.com/about/ReqForInfo.jsp

55

Page 109


Feb.23, 2006

Keep up to date on:Services and Support Information Events and Announcement

- Firmware updates - New product announcement- Manuals - Technology information- Education and training courses - Application and product notes- Calibration - Seminars and Tradeshows- Additional services - eSeminars

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1


Feb.23, 2006Page 1

Enhanced TDR Channel Characterization Capabilities


Brian ChiSenior Project ManagerAgilent [email protected]

Feb, 23, 2006

Page 2


Feb.23, 2006

Z Impedance?

High Speed Digital Design

Impedance in Time Domain

2

Page 3


Feb.23, 2006

E

R

PROBE

0Ω

E/2

0

E

What do you expect to see at the probe before, during, and after you close the switch?

Time

Short Termination


Page 4


Feb.23, 2006

E

R

PROBE

∞Ω


E/2

0

E

Time

Open Termination


3

Page 5


Feb.23, 2006

E/2

0

E

E

R

PROBE

R


Time

Perfect Termination


Page 6


Feb.23, 2006

Zero Ω

∞ Ω

ZL=Z0 ΩE/2

0

E

Vi

Vr

Vr

(∆V)

ρρ

−+

=11

0ZZLImpedance Calculated from

Source Impedance and Reflection Coefficient.

i

r

VV

=ρ Reflection Coefficient:How much was reflected?

Time

Impedance Mismatch Terms


4

Page 7


Feb.23, 2006

E

R

PROBE

? ZL = ?

Z0 = 50 Ω Vi = 200 mV

Vr = 66.6 mV

200 mVolts

0 Volts200 mV

66.6 mVVi

Vr(ΔV)

What is the value of ΖL?

Time

Mismatch Exercise


Page 8


Feb.23, 2006

ZL

Ei Er

STEP GENERATOR

OSCILLOSCOPE

TRANSMISSION SYSTEM UNDER TEST

Ei

Er

T

Oscilloscope display when Er ≠ 0Typical Step: 200 mV, 25 kHz square wave

with 35 ps rise time

Step Reflection Testing

5

Page 9


Feb.23, 2006

Distance FormulaWhere

νp = velocity of propagation

T = transit time from monitoring point to the mismatch and back

2TD p ⋅=υ

ZL

Why is the transit timedivided by two?

Mismatches Location

Page 10


Feb.23, 2006

The shape of the reflected wave reveals the nature and magnitude of the mismatch

What is the nature of each of the loads shown at the right?

a) SHORTb) OPENc) IMPEDANCE > Z0d) IMPEDANCE < Z0

10

0 +=+−ZZZZ

L

L

10

0 −=+−ZZZZ

L

L

Z = ?

Z = ?

Simple Loads Reflection Analyzing

6

Page 11


Feb.23, 2006

The shape of the reflected wave reveals the nature and magnitude of the mismatch

What is the nature of each of the loads shown at the right?

a) SHORTb) OPENc) IMPEDANCE > Z0d) IMPEDANCE < Z0

100

0 +<+−

<ZZZZ

L

L

010

0 <+−

<−ZZZZ

L

L

Z = ?

Z = ?

Simple Loads Reflection Analyzing

Page 12


Feb.23, 2006

The shape of the reflected wave reveals the nature and magnitude of the reflection

Complex load impedances are also identified

Series R-LShunt R-L

LR

RL

Complex Loads Reflection Analyzing

7

Page 13


Feb.23, 2006

The shape of the reflected wave reveals the nature and magnitude of the reflection

Complex load impedances are also identified

Series R-CShunt R-C

R C

CR

Complex Loads Reflection Analyzing

Page 14


Feb.23, 2006

Analyzing Reflections of Complex Loads

8

Page 15


Feb.23, 2006

Analyzing Reflections of Complex Loads

Page 16


Feb.23, 2006

0 0 2incident reflected measured

DUTincident reflected incident measured

V V VZ Z ZV V V V

+= =

− • −

9

Page 17


Feb.23, 2006

Required Parameters by Standard – S parameters

8RapidIO

XX1.3USB 2.0XXX8Firewire

X4.1DVIXXX4.1HDMI

XXN/AEIA-108XXN/AEIA-364-90XXX4.5Serial ATAXXX6.3Infiniband

XX?IEEE 802.3aeX2.4Fully Buffered DIMM

XN/AIPC

XX

Loss

S21

X7.5Serial Attached SCSIXXPCI-XXXX1.25PCI Express

XX5PCI Express Gen 2

CrosstalkReturn Loss

S11

ImpedanceMax Freq, GHz

Standard

Add: FSB, 1 GbEIPC was Institute of Interconnecting and Packaging Electronic Circuits

Page 18


Feb.23, 2006

Introducing 86100C option 202- TDR S-Parameters capability

S-parameter display TDR -> S11 (Return loss)TDT -> S21 (Insertion loss)

Single-end & Differential

No external PC needed

Run on only 86100”C”

10

Page 19


Feb.23, 2006

Introducing 86100C option 202- Corrected Impedance Profile - Peeling

Peeling mitigate measurement errors caused by multiple reflections at each impedance mismatch.

Blue: raw dataYellow : corrected

Page 20


Feb.23, 2006

E50 75 ∞

WHAT IF THE TRANSMISSION LINE OR CABLEDOES NOT MATCH THE SOURCE IMPEDANCE?

WHAT WILL THE RESPONSE LOOK LIKE?

Matching source Z0 to transmission line ZL

11

Page 21


Feb.23, 2006

Peeling - Voltage Bounce Diagram

ΓR = = 1.0ΓS = - 0.2

240 mV

-48 mV

(192 –1.92)mV

240 mV

201.6 mV

383 mV

t=0

t=2

t=4

-Γl = - 0.2

192 mV

192 mV

75Ω 50Ω Open

Keeps on approaching steady state of 400 mV

9.6 mV

Raw Voltage

Peeled Voltage

50Ω

source

Page 22


Feb.23, 2006

Corrected Z Profile into a 75 Ω Cable

Peeled Trace ImpedanceNotice that multiple reflections have been removed

Peeling assumes Loss-less device.

Loss, Resistance [R], degrade accuracy of peeling.

Initial Z mismatch is the most accurate.

Benefit is enhanced with TDR calibration

12

Page 23


Feb.23, 2006

What is Normalization?

• Built-in Firmware• Removes Test Fixture Error• Increases Accuracy• Allows Customer to Simulate

his own system risetime

Originally Licensed from Stanford University (BracewellTransform)

Critical for Rambus!

TDR normalization (As VNA’s Calibration)

Page 24


Feb.23, 2006

•First part of the calibration removes systematic errors due to trigger coupling, channel crosstalk, and reflections from cables and connectors by measuring the response with the DUT replaced by a short circuit.

•The second part of the calibration generates a digital filter. The filter removes errors by attenuating or amplifying and phase-shifting components of the frequency response as necessary.

•For TDR, this is done by replacing the DUT with a termination having an impedance equal to the characteristic impedance of the transmission line, all of the energy that reaches it will be absorbed.

The procedure of TDR Normalization

13

Page 25


Feb.23, 2006

The procedure of TDR Normalization

Page 26


Feb.23, 2006

Effect of TDR Normalization Calibration

Reference plane by CalibrationFixture DUT

Remove Error caused by Test Fixture, Cable, connectors

14

Page 27


Feb.23, 2006

Fixture Error Correction Techniques

Measurement Goals•Accuracy•Repeatability•High Dynamic range•Complete characterization

= Post-measurement process= Pre-measurement process

TDR Peeling

By VNA

Source : DesignCon 2005 “Designing Transceiver FPGA's Using Advanced Calibration Techniques”

Page 28


Feb.23, 2006

Comparison of TDR and PNA

PNATDR Norm@20pSTDR with RPC

•TDR has wide band receiver•Higher noise floor•Lower S/N ratio•Lower dynamic range

•VNA has narrow band receiver•Lower noise floor•Higher S/N ratio•Higher dynamic range

Agree well to 9-10 GHz

15

Page 29


Feb.23, 2006

Comparison of TDR and PNA (Error Correction)

RPC

@30pS

@20pS & PNA

PhasePNA

Norm@20pS

Norm@30pS

RPC

Magnitude

TDRWaveforms

Comparison: TDR Calibration Methods versus PNA SOLT CalibrationDevice Under Test: 3.5 mm Thru AdapterResults: The magnitude loss increases as a function of frequency and is dependent upon the calibration method for TDR-based measurements. Phase error due to timing jitter exists in TDR-based measurements.

Good Calibration yields ~1dB error below 10GHz

Page 30


Feb.23, 2006

Mismatch Line Device #1 Insertion Loss S21 (Magnitude dB)

-35

-30

-25

-20

-15

-10

-5

05.00E+07 2.54E+09 5.04E+09 7.53E+09 1.00E+10 1.25E+10 1.50E+10 1.75E+10 2.00E+10

-35

-30

-25

-20

-15

-10

-5

0

VNA

TDR

TDR vs VNA comparison

50MHz 20GHz10GHz

16

Page 31


Feb.23, 2006

Mismatch Line Device #1 Return Loss S11 (Magnitude dB)

-35

-30

-25

-20

-15

-10

-5

05.00E+07 2.54E+09 5.04E+09 7.53E+09 1.00E+10 1.25E+10 1.50E+10 1.75E+10 2.00E+10

-35

-30

-25

-20

-15

-10

-5

0

VNA

TDR

TDR vs VNA comparison

50MHz 20GHz10GHz

Page 32


Feb.23, 2006

N1024A TDR Calibration KitBest for Differential normalization 2 x Loads and 2 x Shorts

2 36” SMA cables2 3.5mm-f precision load2 3.5mm-m precision load2 SMA-f flush short2 3.5mm-m flush short2 3.5mm f-f adapter1 SMA-f to BNC-m1 Torque wrench

3 36” SMA cables1 SMA-f load1 SMA-m load1 SMA-f short

2 SMA-m to BNC-f5 3.5mm 20dB pads

Accessory Kit

N1024ACurrent 54754A-100

17

Page 33


Feb.23, 2006

Diff. TDR Probe

Used for handheld Differential meas.

2 x Diff. and 2 x Single Ended Probes

2 SMA cables2 SMA-m precision load2 SMA-m flush short2 Size Diff. TDR probe2 Size Single Ended Probe1 Calibration Subtract1 Hand Held holder1 ESD protection (option)

3 36” SMA cables1 SMA-f load1 SMA-m load1 SMA-f short

2 SMA-m to BNC-f5 3.5mm 20dB pads

Accessory Kit

PS-X10-100Current 54754A-100

Page 34


Feb.23, 2006

TDR Accessories

Do you know we have ;

N1020A-K08 FireWire TDR Cable

(IEEE 1394)

N1020A-K09 HSSDC* TDR Cable

Gigabit Ethernet (IEEE 802.3

Standard)

N1020A-K10 DB-9 TDR Cable

Fibre Channel (ANSI x3.297-1997)

* High Speed Serial Data Connector InfiniBand 1x, 4x will be available

USB2.0 & HDMI are under investigation

18

Page 35


Feb.23, 2006

On Wafer & Packages measuring example

Page 36


Feb.23, 2006

Interconnects – Using Excess L/C

19

Page 37


Feb.23, 2006

How close can two reflection sites be and still be seen as independent events?

The TDR edge needs time to reach its full height before the next event is encountered

So what determines the two-event resolution?

Answer: It’s not just the TDR step speed!

Page 38


Feb.23, 2006

A 35 picosecond step is insufficient to see closely spaced reflections

With a 35 ps step, all you know is the device is there

If there is more than one reflection, we can’t tell

35ps

20

Page 39


Feb.23, 2006

High resolution allows your customers to see what they could never see before

At 9 ps step speed, we see 5 separate reflections

Each event is easily seen and quantified

9ps

V-connectorpin-collette

V-connectorpin-collette

hermeticfeedthrough

coaxialfeed-

through

microstriptransmission line

coaxial-microstriplaunch

Page 40


Feb.23, 2006

86100/Picosecond Pulse Labs 4020/4022 Measurement capabilities

35ps<9ps

The Picosecond Pulse Labs 4020 modules takes the 35 Picosecond pulse from the Agilent TDR and increases the speed to under 9 picoseconds

Two-event resolution is improved by a factor of 4!

(1.5 mm ‘air’, less than 1 mm in common dielectrics)

21

Page 41


Feb.23, 2006

Optimizing Measurements

You will lose your edge speed if you have:

• Excess or poor quality cabling to and from the DUT

• The scope receiver channel has insufficient BW

Recommend TDR with the 86118A ~75 GHz remote plug-in:

• Max. bandwidth• Minimum cabling distances• Connector recommend as

2.4mm

4020 RemoteTDR Head

SamplingPort

DeviceUnderTest

54754A TDR module

86118A

Page 42


Feb.23, 2006

Configuring a system

86100 C mainframe

54754A TDR plug-in

86118A 70 GHz plug-in • Lower BW channels can be used, but edgespeed

and resolution will be reduced• Cabling between the DUT and the receive

channel degrades TDR speed

Picosecond 4020 (Single-end) or 4022 (differential) TDR or TDT enhancement module

22

Page 43


Feb.23, 2006

Physical Layer Test System (PLTS) is the Most Complete for Differential S parameters

•Extensive Calibration

•Eye diagram simulation

•N5320A-225 20G VNA

•N5320A-240 20G VNA

•54754Ax2 TDR base

Page 44


Feb.23, 2006

1


Feb.23, 2006Page 1

Using ADS for Signal Integrity Design

Signal Integrity and Advanced Design System


Ming Chih, Lin Application EngineerFeb, 23, 2006

Page 2


Feb.23, 2006

Overview

Part I

• Unified Environment for SI Design

Part II

• Application Guides for SI• Eye Diagram• IBIS Model• Momentum

2


Feb.23, 2006Page 3


Unified Environment for SI Design

Page 4


Feb.23, 2006

Signal Integrity Problems are Everywhere!

WafersBackplanes

IC Packages

Cables

PC Boards

3

Page 5


Feb.23, 2006

Signal Integrity (SI)- What is it?

It is the application of engineering principles to:Control impedance and reflectionsMinimize parasitic and unwanted coupling effectsControl skewAdjust for skin-effect and dielectric lossesTransmitter Pre-emphasisReceiver Equalization

So chips can communicate at higher data rates

“Signal integrity is a field of study half-way between digital design and analog circuit theory”

Dr. Howard Johnson

Page 6


Feb.23, 2006

Projected Increase of Clock Frequencies

Source: ITRS 2003 SIA Roadmap

0

2500

5000

7500

10000

12500

15000

17500

1998 2000 2002 2004 2006 2008 2010 2012 2014 2016

Year

Clo

ck F

requ

ency

(MH

z) on-chip on-board

Microprocessor based products

Parallel busSerial bus

Production

R&D

4

Page 7


Feb.23, 2006

Computer Interconnect Standards

XAUI

On Chip

PCI 32/33 & 64/66

Chip-to-Chip Local Bus SystemBackplane

CoreConnect SCSI

USB

Serial ATA

IEEE 1394

1Gb Ethernet

CompactPCI

VME

PCI-X 66 & 100

POS-PHY L3/L4

XAUI

3GIO/PCI-Express 2.5Gb/s

RapidIO 3.125Gb/s

3.125Gb/s

Fibre-Channel

InfiniBand 2.5Gb/s

1.5Gb/sHyperTransport 1.6Gb/s

Second gen PCI-Express (5-6.25Gb/s)

6Gb/s SATA III

6.25Gb/s double XAUI

VXS Backplane (VITA41)

AdvancedTCA (PICMG 3.x)

GigE Backplane (VITA 31.1)

StarFabric Backplane (PICMG 2.17)

Serial Mesh Backplane (PICMG 2.20)VME320

1.0Gb/s

2.5Gb/s

2.0Gb/s

3.0Gb/s

5.0Gb/s

6.0Gb/s

10Gb Ethernet

CSIX

Flexbus 4

10.0Gb/s

Page 8


Feb.23, 2006

High-Speed Signaling Standards

StandardData Rate

(Gb/s)Driver Edge

Rate (ps)Receiver

Sensitivity

Receiver Eye Opening or Setup/Hold

Serial PCI Express (3GIO) 2.5 RapidIO Serial 3.125 10GbE XAUI 3.125 50ps 200mVpp 100ps Fibre Channel 2125 2.125 to to to Infiniband 2.5 140ps 400mVpp 140ps Serial ATA 1.5Parallel RapidIO 8/16 2 HyperTransport 1.6

Edge rates are decreasing below 100psDifferential voltage swings are shrinkingThe model bandwidth required for accurate measurements is primarily

dependent on the signal’s risetime, not its data rate.

5

Page 9


Feb.23, 2006

Agilent’s Signal Integrity Solutions

Page 10


Feb.23, 2006

CapabilitiesCapabilities

High Speed High Speed Interconnect Interconnect

LibraryLibraryMomentumMomentum Layout Layout

ComponentsComponentsAdvanced Model

Composer

Circuit and NumericCircuit and NumericCoCo--Simulation Simulation

Phys

ical

Phys

ical

Ptolemy Ptolemy Synchronous Synchronous

DataflowDataflow

HFHFSPICE SPICE

(Transient)(Transient)

LinearHarmonic Balance

Circuit Envelope

ConvolutionHigh Frequency SPICE

PtolemyPtolemy Fixed Point

Planar EM (Quasi-static)Planar EM (Full-wave)

Custom EM-based Models

AC/AC/SS--ParametersParameters

ConvolutionConvolution

Harmonic Balance

Dom

ain

Dom

ain

Num

eric

Num

eric

Tim

eTi

me

Freq

uenc

yFr

eque

ncy

Circuit Envelope

Advanced Design System

Simulation Leadership

PtolemyPtolemyTimed Timed

Synchronous Synchronous Dataflow Dataflow (TSDF)(TSDF)

Vector SignalInstrument Links

6

Page 11


Feb.23, 2006

YEAR

TECH

NOLO

GY

Yield Optimization

Microwave System Simulation

Harmonic Balance Simulator

1980

1990

2000

Discrete-valued Optimization

Transient Convolution Simulator

GaAs Foundry Design Kits

Multilayer Interconnect Library

Circuit Envelope Simulator

High-speed Krylov Harmonic

Balance

Yield Analysis

ROOT MOSFET, Schottky and Varactor Models

Transient-assisted Harmonic Balance

2.5D EM Adaptive polygonal meshing

Ptolemy Time-synchronous

Dataflow Simulator

8510A Vector Network Analyzer

High-Frequency SPICE

PC-based Linear Simulator

MDS for Unix

Layout-driven simulation

Agilent – 20 years of Simulation InnovationFrom Touchstone to ADS

EEsof Touchstone & Libra, Academy, Series IV

Advanced Design System

MDS

Phase-noise Analysis

Optimization from Layout

Microwave

High-speed digital

RFIC

RFIC Foundry Design Kits

Standards-based Communications

Libraries

DesignGuides

Wireless Design Libraries

RF/ Analog co-simulation

Genetic Optimization

Fast 2.5D EM simulator for RF

Smart Simulation Wizards

Developer’s Studio

RFDE

2004

Advanced Model Composer

Automated thick-metal EM

Signal Integrity DesignGuide

4-PORT VNAand PLTS

Page 12


Feb.23, 2006

ADS for Signal Integrity

1924 pin LTCC Package Designed using ADSMeasured vs Modeled, 50 ps TDT response

2 4 6 8 10 12 14 16 18 200 22

-30

-20

-10

-40

0

freq, GHz

dB(S

(2,1

))dB

(S(4

,3))

Measured vs Modeled, Insertion Loss (S21)

7

Page 13


Feb.23, 2006

4-port Measurement of Connector

Page 14


Feb.23, 2006

Simulated Step-response of Measured Connector

differential, true/complement skew +/- 50 ps.Both output steps shown Below.

0.4 0.5 0.6 0.7 0.8 0.9 1.0-600

-400

-200

0

200

400

600

time, nsec

Vpo

rt2, m

VV

port4

, mV

•Differential pair simulated their response to a voltage step.

•Main through line is held fixed during simulation

• The complement line is swept from +/-50ps

• magnetic effect in board is evident in measurement.

8

Page 15


Feb.23, 2006

Simulated Eye Diagram of Measured Connector

Differential, true/compliment skew +/- 50 ps• Eye opening on left-side is smaller than on right-side of crossing point for –50, -40, -30ps.

• Jitter is higher for – 50, -40 and -30 ps eyes

• Slope of rise is shallower for + and – 50 ps eyes

• Eye opening is balanced and and rise is faster for 0, +10 and +20ps

• Physical line added to board to adjust delay based on these results

Page 16


Feb.23, 2006

Typical SI Problem

IBIS or Spice model

Pattern Generator

Pre-emphasis / Driver

Encoder

DecoderReceiver

Equalizer

Physical Channel

Board Traces 2” (51mm) – 10” (254mm)Card

CardPackage

Die

Package

Die Driver

Receiver

CardHigh speed Connectors

IBIS or Spice model

Backplane Traces 10” (254mm) – 40” (1016mm)

Physical Channel

Channel Adaptation

Signal Recovery

9

Page 17


Feb.23, 2006

PackageCard

Card

Die

Package

Die

Driver

Receiver

ADS for Signal Integrity – Link Level Simulation

Simulators• Frequency-domain • Time-domain• Numeric Domain • 3-D Planar Electromagnetic• 3-D Electromagnetic Models• Optimized equivalent circuit models • Analytic transmission line models• Static field-solver based models• EM simulation models• Models from measurements• Matlab, VHDL, C++, SystemC, Verilog_AMeasurements• TDR and TDT• 2-port and 4-port VNA• Eye Diagram

Pattern Generator

Pre-emphasis / Driver

Decoder Receiver

Encoder

Equalizer

Physical ChannelChannel Adaptation

Signal Recovery

Page 18


Feb.23, 2006

Simulators - Solve the Whole Problem

Each part of the Link can be modeled and designed separately, however…

What happens when the parts are brought together for the first time?

Would it be beneficial if the Link could be analyzed as a whole?

10

Page 19


Feb.23, 2006

Agilent Ptolemy

• Agilent Ptolemy is the Data Flow simulator

• System Level Simulation Kernel • based on UC Berkeley Ptolemy• Timed Synchronous Data Flow (TSDF)• Numeric Synchronous Data Flow (SDF) • Links to other simulators & instruments

Ptolemy Data Flow (discrete numeric/time-domain)• Signal Processing Verification – FEC, Encoding/Decoding• System Performance Verification – uncoded/coded BER

Page 20


Feb.23, 2006

• Statically Scheduled Simulation1. A component maps input tokens (current or numbers) onto

output tokens2. A set of firing rules specify when a node (component) runs3. A firing consumes input tokens and produces output token4. Nodes (components) connected by arcs (wires)5. Schedule is constructed once and repeatedly executed

• Suitable for synchronous multi-rate signal processing• Synchronous Data Flow has no concept of time, just

numeric data• Tokens can also be “time stamped” - then they

become samples. Now you can simulate time and frequency domain models and impairments such as reflections and dispersion TSDF

Enabled

Fired

What is Synchronous Data Flow (SDF)?

11

Page 21


Feb.23, 2006

Agilent Ptolemy - The “IP Integrator”ADS Ptolemy is a solution for the following:• Design & verification of Communication Systems

(physical path).• Co-Simulation of Baseband (DSP) and Analog/RF (A/RF)

circuits in a single simulation:Ptolemy system with ADS circuit simulators (which can also contain Verilog-A models).Ptolemy system with 3rd party tools (Matlab, RTL-HDL simulators, C++, SystemC)

• ”Connected Solutions” connect Simulation, Design & Verification flows to Instrumentation and Measurements

• Circuit verification with System Test Benches (WTBs) to link ADS and Cadence (IC) design tools.

Page 22


Feb.23, 2006

Link Level Simulation

Trace_Spacing sets the distance betwen line pairsas a multiple of intrapair spacing.

This upsample sets measurement resolution

Bipolar signal, +1, -1

The S ampleDelay of 3 will work for thedefault design. If the Channel is changedthis delay can be set via a slider in the Tkcontroller. Set the slider to the same delayas the E ye delay slider when the widest part of the eye is at t=0 on the eye plot.

The SampleDelay of 11 will work for thedefault design. If the Channel is changedthis delay can be set via a slider in the Tkcontroller. S et the slider to the same delayas the Eye delay slider when the widest part of the eye is at t=0 on the eye plot.

For the histograms to be correctthe phase needs to be set to the correct bit slice sample delay.(11 will work for the default design).

For the histograms to be correctthe phase needs to be set to the correct bit slice sample delay.(3 will work for the default design).

Typical Pre-emphasis is progrmaple in steps from 5% to 25%This equates to 1.05 to 1.25 on this controller.

Adding noise or other artefacts to thesignal can be done in this fashion.

Channel Model

PTOLEMY-SPICE CO-SIM SI CHANNEL WITH TX PRE-EMPHASIS AND RX EQUALIZATION

(Using the "drive_lines" channel example)Post Eq measurements

Receiver with Equalization

Bit-stream Transmitterwith Pre-emphasis

Adding Noise

Post-channel measurements

Post-channelInteractive Measurements

Post EqInteractive Measurements

Pre-channel measurements

Pre-channelInteractive Measurements

1

2

TkConstellationT20

Style=dotSampleDelay=10Amplitude=1.5NumSamplesPerSymbol=Samples_per_clockLabel="Bit S lice"

1

2

TkConstellationT18

Style=dotSampleDelay=6Amplitude=1.5NumSamplesPerSymbol=Samples_per_clockLabel="Bit S lice Eq"

1 2

RateLimiterR8RMax=4e10

1 2

drive_lines_cosim3_sub_s2pX7Trace_Spacing=3

I O

31

2

LMS_TkPlotL4

Identifier="LMS filter taps"SaveTapsFile="tapsout.tap"ErrorDelay=1StepSize=0.02DecimationPhase=0Decimation=1Taps="-2.3 0 0.4 1.0 1.3 1.3 1.2 0.8 -0.1 -0.8 -1.6"

1 2

FloatToTimedF3TStep=Sample_step sec

1 2

RepeatR5

BlockSize=1NumTimes=Samples_per_clock

1 2

LogicToNRZL5Amplitude=1.0

1

2

3

Add2A2

1

Tk Sl i de rSc al e 1

Gra nu la rity =1 00Pu tIn Co ntrol Pan el =YESIde nti fi e r= "Pre-e m ph as i s Ga in "Va l ue =1Hi g h= 2Lo w= 1

1 2

3

P re-EmphasisX 6

3

21 12

3

S plitterRFS 2

1

BitsB1

LFSR_InitState=1LFSR_Length=12ProbOfZero=0.5Type=Random

1

ConstC2Level=0.0

1

TkHistogramT19

DataPoints=10000NumberOfBars=32Bottom=-1.5Top=1.5Label="Bit S lice Histogram Eq"

1 2

DownSampleD3

P hase=11Factor=S amples_per_clock

1

TkHistogramT21

DataPoints=10000NumberOfBars=32Bottom=-1.5Top=1.5Label="Bit S lice Histogram"

1 2

DownSampleD2

P hase=3Factor=S amples_per_clock

1

TkEyeT14

Amplitude=1NumSymbols=2NumSamplesPerSymbol=S amples_per_clockLabel="Pre Channel Eye"

1

SpectrumA nalyzerPre_channel

WindowConstant=0.0Window=K aiser 7.865Stop=Data_Collection_time nsecStart=DefaultTimeStartRLoad=DefaultRLoadPlot=None

1

SpectrumAnalyzerPost_channel

WindowConstant=0.0Window=Kaiser 7.865Stop=Data_Collection_time nsecStart=DefaultTimeS tartRLoad=DefaultRLoadPlot=None

1

TimedS inkPost_E q_t

ControlSimulation=YESStop=Data_Collection_time nsecStart=DefaultTimeS tartRLoad=DefaultRLoadPlot=None

1 2

TimedToFloatT22

12

1

RR7R=50 Ohm

2

1

RR3R=50 Ohm

1

TkPlotT13

Style=connectyRange="-2 2"xRange="0 1000"yTitle="amplitude"xTitle="waveform"Label="Pre Channel scope"

1

TkEyeT5

Amplitude=1.5NumSymbols=2NumSamplesPerSymbol=Samples_per_clockLabel="Eye Post Channel "

1

TimedS inkPre_channel_t

ControlSimulation=YESStop=Data_Collection_time nsecStart=DefaultTimeStartRLoad=DefaultRLoadPlot=None

1 2 31

2

SubS9

2

1

RR6R=50 Ohm

1

1 2

TimedToFloatT12

1

TkPlotT7

Style=connectyRange="-1 1"xRange="0 1000"yTitle="amplitude"xTitle="waveform"Label="Post Channel scope"

12

Del a yD1N=1

1

ConstC1Level=0.0

1

TkEyeT17

Amplitude=1.5NumSymbols=2NumSamplesPerSymbol=Samples_per_clockLabel="Eye Eq"

12

3

SplitterRFS7

1

TimedS inkPost_channel_t

ControlSimulation=YESStop=Data_Collection_time nsecStart=DefaultTimeS tartRLoad=DefaultRLoadPlot=None

12

3

S plitterRFS 6

1

1 2

TimedToFloatT6

12

3

SplitterRFS8

12

3

S plitterRFS 4

DFDF2

VA RVA R1

Data_Collection_start=4Data_Collection_time=40Sample_step=1/S ample_rateSample_rate=Clock*S amples_per_clockSamples_per_clock=12Clock=12.8e9

EqnVar

1

2

3

Mpy2M3

1

TkSl id erSca l e2

Gran ul ari ty= 10 0PutInCon tro l Pa ne l= YESId en ti f i er="Add ed Noi s e"Val u e= 0Hi gh =1L ow=0

12

FIRF4

Interpolation=1DecimationP hase=0Decimation=1

1

IID_GaussianI1

V ariance=.1Mean=0

Pre-emphasis Channel Equalization

12

Page 23


Feb.23, 2006

Transmitter with Pre-Emphasis

Page 24


Feb.23, 2006

Channel Model

Aggressor Lines

Channel Subnetwork

13

Page 25


Feb.23, 2006

Channel Subnetwork

Page 26


Feb.23, 2006

ModelsAccurate models of interconnects

Accurate models of the active devices

Robust simulator

Accurate Prediction of performance

+

+

=

The earlier in the design cycle that problems are found and designed out, the shorter the cycle time,

the lower the development costs

Accurate models of Tx and Rx Functions+

14

Page 27


Feb.23, 2006

Interconnect Models

Account for impedance, delay, conductor loss, dielectric loss, and coupling

Momentum EM simulator for arbitrary planar structures. Has layout and schematic representations

Analytic models are fast, and have a layout and schematic representation

Multilayer Interconnect Models use a built-in field-solver, and have both layout and schematic representations

Page 28


Feb.23, 2006

Current ADS Capabilities• Integrated Momentum EM Simulator• Momentum RF• Model Composer• Co-Simulation w/Layout Components• Co-Optimization w/Layout Components• Layout lookalike components

30 GHz transition

Layout editing and port

assignment

Layout look-alike component in the

schematic

EM Models - Momentum

15

Page 29


Feb.23, 2006

• near field / low freq approximation

L(ω) = L0 + L1ωR + L2(ωR)2 + …

C(ω) = C0 + C1ωR + C2(ωR)2 + …

• neglecting far field radiation

• [L0] & [C0] frequency independent

• [Z0] matrix reload very fast

Momentum RFQuasi-Static Electromagnetics

Low Frequency approximation :

|'|1'|| rrrr −−≈−− jke jk

[Z] matrix load is frequency independent !

[Z].[I]=[V]

[S]

Mesh strips, Vias and slots with rectangles and triangles (conformal surface mesh)

Performs mesh reduction while maintaining integrity of solution

Model surface current in each mesh cell (linear distribution)

Solve matrix equation for the unknown current coefficients

Calculate S-parameters

Electro- and magnetostatic Green’s functions

Quasi-static frequency scaling (jw, 1/jw)

L’s and C’s are real and frequency independent

R’s are complex (DC loss + skin effect √w)mesh topology

reduction

reduction 1 cell

4 cells

10 cells

Page 30


Feb.23, 2006

Comparison of Models

• quasi-static inductance . . . . . . • quasi-static capacitance . . . . . • DC conductor loss (s) . . . . . . . .• DC substrate loss (s) . . . . . . . . • dielectric loss (tgd) . . . . . . . . . . . . . . . . . . . . . . . . . . .• skin effect loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Layout

S parameters

RF

Spice model

DC Spice Momentum

16

Page 31


Feb.23, 2006

Models in Matlab, VHDL, C++, SystemC, Verilog-A

IP for “Link Level” blocks and functions often already exist, e.g.

Pre-emphasisEQEncoding/DecodingInterleaving/De-interleavingSource descriptions

Easy to include with Ptolemy, either natively or with Co-simulation

Page 32


Feb.23, 2006

Models - MATLAB Co-Simulation in ADS Ptolemy

scripting code

MatlabSinkM6

NumberOfFirings=1MatlabWrapUp=""MatlabFunction=""MatlabSetUp=""DeleteOldFigures=YESScriptDirectory=""

MatlabCx_MM1

MatlabWrapUp=""MatlabFunction=""MatlabSetUp=""DeleteOldFigures=YESScriptDirectory=""

Matlab_MM8


MatlabSinkFM7

NumberOfFirings=1MatlabWrapUp=""MatlabFunction=""MatlabSetUp=""DeleteOldFigures=YESScriptDirectory=""

MatlabFCx_MM2


MatlabF_MM3


script files

MATLAB compiler – generate native shared librariesMatlabLibLinkCx

M5

Mode=AUTOFunction=""SetupParm=""Setup=""Library=""

MatlabLibLinkM4

Mode=AUTOFunction=""SetupParm=""Setup=""Library=""

Co-simulate with Matlab in ADS

Use full Matlab UI or as math function only

Components in “Numeric Matrix” library

17

Page 33


Feb.23, 2006

Models - HDL Co-Simulation in ADS Ptolemy

In the HDL Blocks library

VxlCosimV1

HdlSimulatorGUI=OffHdlModelName=""OutputPrecisions=""Outputs=""InputPrecisions=""Inputs=""HdlSrcFile=""

OUT

IN

Clock

___ Set

NCCosimN1

HdlSimulatorGUI=OffHdlModelName=""OutputPrecisions=""Outputs=""InputPrecisions=""Inputs=""HdlSrcFile=""

OUT

IN

Clock

___ Set

HdlCosimH1

HdlSimulatorGUI=OffHdlLibrary=""HdlModelName=""OutputPrecisions=""Outputs=""InputPrecisions=""Inputs=""HdlSrcFile=""

OUT

IN

Clock

___ Set

Page 34


Feb.23, 2006

Integration of other ModelsC++ Based Model Creation and SystemC

C++• Native Language for Ptolemy Kernel• Model Development Through GUI and Command Line

Interface• Full Debug Capability Through 3rd Party Development

Environments• Microsoft Visual Studio for PC Platforms

SystemC• Application Note 1482: Importing SystemC Designs into

Advanced Design System• http://eesof.tm.agilent.com/pdf/5989-0234EN.pdf

18

Page 35


Feb.23, 2006

Measurement-based Models Probing Solution + PLTS + ADS

ADS Design SW

S-parameters• Citifile• TouchstoneRLCG• Measured Parameters• ML2CTL Model

Device Under Test, Microprobes & Probe Station

4-Port TDR or VNAPLTS Software

View and analyze measurement data

Calibration and Measurements

View and analyze measurement data

using PLTS software

Page 36


Feb.23, 2006

TranTran2

MaxTimeStep=Sample_stepStopTime=Data_Collection_time nsec

TRANSIENT

DataAccessComponentDAC1

iVal2=Trace SpacingiVar2="Trace_Spacing"iVal1=freqiVar1="freq"ExtrapMode=Interpolation ModeInterpDom=RectangularInterpMode=LinearType=DatasetFile="drive_lines_s2p.ds"

DAC

2

3

4

1

S2P_EqnS2P1

Z[2]=fileDAC1, "PortZ[2]"OhmZ[1]=fileDAC1, "PortZ[1]"OhmS[2,2]=fileDAC1, "S[2,2]"S[2,1]=fileDAC1, "S[2,1]"S[1,2]=fileDAC1, "S[1,2]"S[1,1]=fileDAC1, "S[1,1]"

1 1

1

PortP1Num=1

1

PortP2Num=2

Link Level SimulationData based Channel Models can be derived from simulation models or measurements.

Radia l1

arbitrary4p_1

Radial2

CLin6

Slant 1

R4

R12

CLin5

CLin4

R10

R9

arbit rary4p

MLRADIAL2 MLRA DIAL2

MLSLANTED2

ML6CTL_V

ML4CTL_V ML4CTL_V

R

R

R

R

Channel Model

1 2

drive_lines_cosim3_sub_s2pX7Trace_Spacing=3

I O1

SplitterRFS2

2

3

SplitterRFS4

Direct co-sim

ulation

Parameterized Data

Simulated ChannelTDR or VNA Measurements

19

Page 37


Feb.23, 2006

Bringing it All Together

•ADS has been used for SI design for over 10 years

•ADS can act as a scalable design whiteboard

•ADS encourages you to be curious about your design ideas

•ADS has a multitude of accurate built-in models

•ADS allows you to build accurate physical models

•ADS lets you use your existing models

•ADS agrees with measurements

•ADS shows results the way you want to see them

•ADS brings IP, simulations and measurements together

•ADS Ptolemy lets you work with the whole Link before you build it!

Page 38


Feb.23, 2006

Signal Integrity Resources

Gigatest for probe stations and package modeling services www.GigaTest.com

CST for 3D EM Simulator www.cst.com

Fastest, Inc for designing high speed hardware and resolving signal integrity problems. www.fastestco.com

Admos for active and passive model extraction serviceswww.admos.com

20

Page 39


Feb.23, 2006

SI Resources on the Agilent EEsof website

Agilent EEsof EDA home pagehttp://eesof.tm.agilent.com

Signal Integrity Applications and Wireline Applications http://eesof.tm.agilent.com/applications/signal_integrity-b.htmlhttp://eesof.tm.agilent.com/applications/wireline-b.htmlMomentumhttp://eesof.tm.agilent.com/products/e8921a-a.htmlAgilent Signal Integrity eSeminar Series www.agilent.com/find/sigintNetSeminar: Challenges of Differential Bus Design -http://eesof.tm.agilent.com/news/news400.html#bus_design

Page 40


Feb.23, 2006

Application Web site for 2005A

http://eesof.tm.agilent.com/applications/signal_integrity-b.html

21

Page 41


Feb.23, 2006

Signal Integrity Training Class

http://www.agilent.com/find/educationSignal Integrity Class: N3215A Designing for Signal Integrity with ADS

Transient Simulation SetupConvolution and Frequency-Domain SimulationsTransmission Lines, Crosstalk and Resonances TDR/TDTNoise and Jitter2.5D EM Simulations (Momentum)Differential Circuits and Mixed-Mode S-Parameters

– Length – 2 days – hands-onPtolemy training: N3206A Signal Processing using ADS

Ptolemy SDF / TSDFCo-simulation

• Length – 3 days – hands-on


Feb.23, 2006Page 42

Using ADS for Signal Integrity DesignModels, Simulations and Measurements

22


Feb.23, 2006Page 43


Application Guides for SI

Page 44


Feb.23, 2006

Amplifier

DesignGuides in ADS – Bridging the Gap

FilterSI

Linearization

Mixer OscillatorPLL

RF System

Passive

DesignGuides

Simulation TechnologyApplications

Linear, NonlinearCircuit EnvelopeTime DomainAgilent PtolemyElectromagneticOthers

Amplifier, FiltersMixers, OscillatorPassives, SystemMod/DemodsPackagingRadar, A-to-D, UWB,High-Speed Digital

23

Page 45


Feb.23, 2006

DesignGuides / Application Guides

IBIS model import and examples

Signal integrity simulations and examples

Highspeed circuits typical for wireline

Helps SI designer to use ADS for common tasks

Des

ignG

uide

sA

pplic

atio

n G

uide

s

Page 46


Feb.23, 2006

Wireline ApplicationsPhotodiode

Bandgap

Transimpedance Amp

Limiting Amp

Laser Driver

VCSEL

TWA

Ring Oscillator

24

Page 47


Feb.23, 2006

Wireline Applications

Multiplexer

Buffer, Divider

Latch, Selector

Page 48


Feb.23, 2006

Wireline Applications Ckt-level Logic

Bandgap

Behavioral Logic

D Flip Flop

Phase Detectors

Multivibrator VCOClock Recovery

25

Page 49


Feb.23, 2006

IBIS Library

IBIS Model Import

Page 50


Feb.23, 2006

Ideal Source BuffersOctal Pulse Source

Octal Loads

Oscilloscope Probe

Components from the IBIS Library Component Palette

Impedance Optimizer

Impedance Meter

26

Page 51


Feb.23, 2006

Signal Integrity Applications

Eye Diagram measurements including jitter, FrontPanel and DCA file import

Single Ended TDR/TDT

Linear/Nonlinear Differential TDT

Mixed Mode S-ParametersImpedance Simulations

Pre-emphasis and Equalization

Page 52


Feb.23, 2006

TDR Simulation Instrument

27

Page 53


Feb.23, 2006

TDR Responses Using Time-domain Simulation

Page 54


Feb.23, 2006

Differential Nonlinear Test Component

28


Feb.23, 2006Page 55


Eye Diagram

Page 56


Feb.23, 2006

Qualitative vs. Quantitative: How close are these waveforms?“This 40 Gb/s eye diagram was then compared to the 40 Gb/s eye diagram

derived from the internal PLTS eye diagram generating algorithms. The qualitative correlation of these two simulated eye diagrams was very good.“

DesignCon 2004 paper “Utilizing TDR and VNA Data to Develop 4-port Frequency Dependent Models for Simulation” Mayrand, Resso, Smolyansky

29

Page 57


Feb.23, 2006

Data Display strengths and weaknessesData Displays are flexible but require extensive use of equations and a

lot of user expertise.

Some measurements are calculated, but most characteristics are left up to the user to determine.

Page 58


Feb.23, 2006

FrontPanels: Eye DiagramConvenience – dedicated display and push-button measurements focused on

a common task. Provides over 30 data display pages and over 300equations.

Consistency – measurement algorithms checked against instrumentation.

30

Page 59


Feb.23, 2006

Inspired by Agilent DCA-J Instrument

Oscilloscope and Eye Modes of operation

Measurements/TestsSummary of measurement results

Histograms

Pointers, masks

Page 60


Feb.23, 2006

Oscilloscope Mode

31

Page 61


Feb.23, 2006

Eye/Mask Mode

Page 62


Feb.23, 2006

Convert DCA data (*.csv format) into Dataset

Data Parser available in Signal Integrity Application Guide

*.csv file from DCA

Dataset file

32

Page 63


Feb.23, 2006

Compare Eye FP to DCA on Same Data

DCA Measurement

1G Data Rate through 20” trace

Eye Diagram FrontPanel on the DCA output file.

[NOTE: FrontPanel data is from a single trace. DCA measurements are averaged with 16 measurements.]

5.7/5.85.7pS5.8pSJitter rms22.2/22.222.2pS22.2pSJitter p-p

10.01/10.2310.0710.18Eye S/N273.9/274.9274.7mV274.7mVEye Height386.3/389.4389mV389.4mVEye Amp

211/219215pS212pSFall Time219/226222pS219pSRise Time

-177.5/-178.5-177.5mV-177.4mVLevel 0211.3/213.5211.3mV212mVLevel 1

DCA min/max

DCA typFrontPanel

[NOTE: FrontPanel results are preliminary until ADS 2005A final release.]

Page 64


Feb.23, 2006

Compare Eye FP to DCA on Same Data

DCA Measurement


Eye Diagram FrontPanel on the DCA output file.



3.79/3.803.793.79Eye S/N60.8/61.561mV61.3mVEye Height

293.4/293.8293.7mV293.8mVEye Amp140.6/140.6140.6pS140.6pSFall Time136.2/136.9136.2pS136.3pSRise Time-136.6/-136-136mV-136mVLevel 0156.4/157.5157.5mV157mVLevel 1

DCA min/maxDCA typFrontPanel


33


Feb.23, 2006Page 65


Example Measurements

Page 66


Feb.23, 2006

Common SI Problem

Objective: 1m of “improved FR-4” through multiple high speed connectors.10” (254mm) Line Card > 20” (508mm) Backplane > 10” (254mm) Line Card. Check Eye Diagram at various points along the path.

Board Traces 2” (51mm) – 10” (254mm)

Backplane Traces 2-3 chassis/rack = 10” (254mm) worst case5-8 chassis/rack = 40” (1016mm) worst case

Card

CardPackage

Die

Package

DieDriver

Receiver

CardHigh speed Connectors

IBIS or Encrypted Hspice model

IBIS or Encrypted Hspice model

34

Page 67


Feb.23, 2006

Example Test Board

Several trace lengths on “improved FR-4” six metal layers, 62.5 mil total thickness

10” (254mm) 15” (381mm) 40” (1016mm)

30” (762mm) 20” (508mm)

Launch detail

Page 68


Feb.23, 2006

Measurements on various length of trace

10” (254mm)15” (381mm)

20” (508mm)

30” (762mm)

40” (1016mm)

S-Parameter measurements

Differential S-Parameter measured with PLTS

Traces are lossy

Measurement shows multiple reflections

Data is band limited

35

Page 69


Feb.23, 2006

Create Models from Data

Data-based ModelMeasure with 4-port NWA

Layout Look-alike component

Page 70


Feb.23, 2006

DCA/BERT Measurement SetupMeasure the input waveformBypass the Board, record the waveform

Capture waveform with Connection Manager or output *.csv file to translate to dataset.

E8251A+5dBm

1 GHz, 2.5 GHz, 5 GHz11636B

Splitter

86100C

Trigger

BERT

E8251A+5dBm

1 GHz, 2.5 GHz, 5 GHz11636B

Splitter

86100C

Trigger

BERT

PRBS Data Out

Measure the DUT (board and cable)

*.csv *.ds

PRBS Data Out

36

Page 71


Feb.23, 2006

Simulation through Measured S-Parameter Data

SimulationSimulation of

measurement-based waveform through measured S-Parameter data for the board and cable.

Adjust gain to compensate for loss through resistor. May need to adjust gain slightly to match measurements.

Page 72


Feb.23, 2006

Simulation compared to DCA Measurement


DCA Measurement of BERT

Simulation with Measured Data

Gain set to 1.95


386.3/389.4389mV389mVEye Amp211/219215pS192pSFall Time219/226222pS197pSRise Time

-177.5/-178.5-177.5mV-179mVLevel 0211.3/213.5211.3mV210.8mVLevel 1

DCA min/max

DCA typFrontPanel



37

Page 73


Feb.23, 2006


2.5G Data Rate through 20” trace



Gain set to 1.90

9.1-9.49.4pS9.39pSJitter rms37.1-38.537.1pS40.8pSJitter p-p344-345.8344mV346mVEye Amp172-176172pS157.9pSFall Time169-178178pS157.9pSRise Time

-158.6-157.4-157.7mV-158.9mVLevel 0186.8-188.6186mV187mVLevel 1

DCA min/max

DCA typFrontPanel



Page 74


Feb.23, 2006





Gain set to 1.90

12.43/12.6512.5pS12.3pSJitter rms53.28/54.0254.02pS54pSJitter p-p293.4/293.8293.7mV292mVEye Amp140.6/140.6140.6pS133pSFall Time136.2/136.9136.2pS133pSRise Time-136.6/-136-136mV-137mVLevel 0156.4/157.5157.5mV155mVLevel 1

DCA min/max

DCA typFrontPanel



38


Feb.23, 2006Page 75


IBIS Model

Page 76


Feb.23, 2006

IBIS (Input/Output Buffer Information Specification) models enable IC vendors to communicate device characteristics without revealing circuit / process information.

Behavioral Level

Digital IC

Digital IC

Simulation requirements• Non Linear driver and receiver circuits• High speed board layout ( critical paths)

Circuit Level

Intellectual property

IBIS Model

IBIS Model

39

Page 77


Feb.23, 2006

IBIS Model

A basic IBIS model consists ofFour I-V curves: pullup & Power clamp, pulldown and Gnd

clamp

Two ramps (Rampup and Rampdown) and/or Two/Four Vttables

Die capacitance: C_comp

Packaging: RLC values

For each buffer on a chip

Ramp up (or Vt table)

Ramp down (or Vt table)

Pull up I-V

Pull down I-V

Power clamp I-V

GND clamp I-V

inputI/O pin

Vcc

Gnd

Page 78


Feb.23, 2006

For one pair of V(t) waveform,The other pair is created for a different value of V-fixture.

Red- V(t) waveformpair in IBIS data

Blue- SynthesizedV(t) waveformpair in IBIS data

40

Page 79


Feb.23, 20062.0E-8

2.2E-8

2.4E-8

2.6E-8

2.8E-8

3.0E-8

3.2E-8

3.4E-8

3.6E-8

3.8E-8

1.8E-8

4.0E-8

1.0

1.5

2.0

0.5

2.5

time

Am

plitu

de

Rise/Fall TimeVt Table

Comparison of IBIS model Vt table vs. Rise/FalltimeRise/Fall Time

uses an average value of risetime/falltime to set the time constant of a capacitor.

Usable back to IBIS v1.0

Uses SDD-based equivalent circuit

Can be used in HB as well as Transient simulation

Vt Table

uses voltage lookup table (Vt)

Usable starting with IBIS v2.x

Uses FDD-based equivalent circuit

Can be used only in Transient simulation

Page 80


Feb.23, 2006

Importing IBIS Component

1. Select*.ibs file

2. Define design kit name

3. Define bitmap label

4. Create design kit

41

Page 81


Feb.23, 2006

Installation of design kit

Select the design kit from $HOME directory

Install design kit

Page 82


Feb.23, 2006

IBIS design kit components

42

Page 83


Feb.23, 2006

Simulation Setup and Simulation Results

Pin Number

V_fixture

Page 84


Feb.23, 2006

IBIS Model with Transistor Level Simulation

43


Feb.23, 2006Page 85


Momentum

Page 86


Feb.23, 2006

Momentum RF for Digital Board Interconnect

full boardisolated trace

port 1

port 2

port 1

port 2

S(1,1)

isolated trace

S(1,2)

isolated trace

MomentumMomentum RF

S(1,1)

full board

S(1,2)

full board

44

Page 87


Feb.23, 2006

Digital Board Interconnect - off resonance

isolated trace

port 1

port 2

harmonic signal 0.4 GHz

output

S(1,1)

isolated trace

S(1,2)

isolated trace

Page 88


Feb.23, 2006

Digital Board Interconnect - on resonance

isolated trace

port 1

port 2


resonanceblocks the signal

no output

S(1,1)

isolated trace

S(1,2)

isolated trace

45

Page 89


Feb.23, 2006

Digital Board Interconnect


harmonic signal is coupled to neighboring traces and spread around the board

Page 90


Feb.23, 2006

Momentum RF for Package Models

S(1,3)

S(1,1)

Momentum

Mesh: 20 cells/wavelength, 5 GHz

Matrix size : 8244Process size : > 1 GBUser time : > 2 days

Momentum RF

Mesh: 20 cells/wavelength, 5 GHz

Matrix size : 1354Process size : 106.57 MBUser time : 5h 17m 53s

Rule of thumb: freq < 13.8 GHz

port 1

port 2

port 3

7.6 mm

7.6 mm

port 4

ref 3

ref 4

S(1,2)

S(1,4)

1 2

4 3

ref 3ref 4

GNDVboard

Vchip

epoxy

FR4

96-Ball Grid Array Package

PC-NT Pentium II workstation (330 MHz)

46

Page 91


Feb.23, 2006

Transient Simulation from Schematic

Layout lookalike component used in the schematic

Page 92


Feb.23, 2006

Bringing it All Together

•ADS has been used for SI design for over 10 years

•ADS can act as a scalable design whiteboard

•ADS encourages you to be curious about your design ideas

•ADS has a multitude of accurate built-in models

•ADS allows you to build accurate physical models

•ADS lets you use your existing models

•ADS agrees with measurements

•ADS shows results the way you want to see them

•ADS brings IP, simulations and measurements together

•ADS Ptolemy lets you work with the whole Link before you build it!

1


Feb.23, 2006Page 1

Advanced Calibration Techniques and Fixturing

Issues for VNAs


Ming-Fan, Tsai Application EngineerFeb, 23, 2006

Page 2


Feb.23, 2006

AgendaOverview of PNA FW Rev. 6.0

Cal Registers

TRL Calibration with 4-port 20 GHz PNA-L

Unknown Thru Calibration

Offset Load Cal

Fixture And Probe Techniques

• Auto port extensions

• Embedding/de-embedding

• Frequency Converter Applications – SMC

• Measuring fixtures/probes

Q&A

2

Page 3


Feb.23, 2006

Introduction - Goals and Objectives

Course Goal• Understand new calibration paradigm and features of PNA• Get hands-on time on analyzer

Objectives• Upon completion of this course you will be able to:

– Calibrate a PNA and save a user cal set– Explain concept of Unknown Thru cal– Understand how a two-tier TRL cal is done– Recommend best cal approach for fixtured measurements

Page 4


Feb.23, 2006

Welcome to PNA Firmware Revision A.06.0x

A.01.xx A.02.xx A.03.xx A.06.xx

A.04.xx

A.05.xxOriginal RF PNA code(released Sep 2000)

Added 3-port RF and 50 GHz PNAs(released Dec 2001)

Added 20, 40, 67 GHzand frequency offset(released Dec 2002)

Added PNA-L models(released Dec 2003)

4-port PNA-L ONLY(released Aug 2004)

Re-merged code set(released Dec 2005)

“Hawaii”

3

Page 5


Feb.23, 2006

What’s Totally New in 6.0…

• Target release date: 12 December, 2005• Features

– Calibrate using external trigger (e.g., during wideband pulse detection)– Calibrate with offset loads– External test set control– New FCA capability

• file embedding during cal(for wafer probes and fixtures)

• fixed input for up converters

– 1.1 GHz CPU and related capabilities– Agilent VEE Runtime installed

Page 6


Feb.23, 2006

What’s New in 6.0 From 5.0…

TRL calibration for 4-port PNA-LDedicated calibration window Calibration class label Data-based cal kits can now be modified Guided SmartCal supports ECal modulesOption H11 verification Safely shutdown the PNA without a mouse New *.csa save/recall file type 4-port fixture simulator functions

• 4-Port network embed/de-embed• Balanced conversion• Differential-/ common-mode port Z conversion• Differential matching circuit embedding

Automatic port extensions Interface control Agilent 5091A test set control 8 traces per window (previously 4)

C∆ on status bar .pdf version of Help file available New 4-port PNA Models:

• N5230A Options 240 and 245• Balanced measurements

Calibration registers Number of user ranges expanded to 16

(Stats and Markers) Port extension toolbar features Magnitude offset2-port fixture compensation Two LO sources for millimeter-wave measurements Material handler trigger controlGlobal pass / fail dialog Revised operator's checkRevised system verificationGuided calibration COM interface

Receiver power cal saved with cal set

Note: Highlighted text describes features that are new for 2-port PNA/PNA-L models. These features have already been released for 4-port PNA-L models.

covered in this module

4

Page 7


Feb.23, 2006

Will A.06.xx Work on Discontinued PNAs?

“T1” RF PNA’s (E8356/7/8A): Yes, with upgrade to Windows XP

“T2” 2-port (E8801/2/3A): Yes, with upgrade to Windows XP

“T2” 3-port (N3381/2/3A): No

“M1” (E8364A): Yes, with upgrade to Windows XP

XP upgrade: Order new disk drive from Agilent

x

Order N8980A ($550)

Page 8


Feb.23, 2006

What’s New for the ENA

Rev 6.0 released 11/1/05

New features

• TRL/LRM & waveguide calibration• Automatic port extensions• 20,001 measurement points• Complex reference impedance for balanced matching• Flexible marker value display function• User preset• User recovery • 13/16-port configurable test set control function

More info at: kobemktg.jpn.agilent.com/field_eng/product/ena/customer_viewable/index.htm

5

Page 9


Feb.23, 2006


Cal Registers



Offset Load Cal






Q&A

Page 10


Feb.23, 2006

Old Calibration Paradigm

All calibrations were saved in a “calibration set”

“.cst” file pointed to data in a calibration set, but did NOT contain calibration data itself

“.cal” files contained calibration data but NOT instrument parameters

Saves instrument state using current state name(does not automatically select a .cst file if current state is .sta)

Opens a file dialog box to save instrument state with a new file name (choose .sta or .cst)

Saves instrument state with an auto-incremented name that won’t overwrite existing states (e.g. “at004.cst”)

Old file save dialog

6

Page 11


Feb.23, 2006

New Calibration ParadigmCal Registers

• Each channel has its own cal register• All cal data is saved to the channel cal register• Data in cal register is “temporary” –

data is saved on hard drive, BUT will be overwritten by the next calibration in that channel

User Cal Sets• Old “Cal Sets” are now called “User Cal Sets”• User must manually save data to a User Cal Set• User cal sets are stored on the hard drive as before

You no longer have a choice to save an instrument state!

Page 12


Feb.23, 2006

Cal Registers Should Be Familiar…

Cal register model is similar to that used in 8720s and 8510s

Cal registers prevent accumulation of unneeded cal sets

7

Page 13


Feb.23, 2006

Old Calset File Location

All calset data was contained in this file

Page 14


Feb.23, 2006

New Cal File Locations

8

Page 15


Feb.23, 2006

Saving Instrument States and Cal Data*.cst - save instrument state and reference pointer to the cal set data

• data could be in cal register (not recommended)• data could be in a user cal set (recommended)*.csa - save instrument state and actual cal data (cal/state archive)

*.sta - save instrument state ONLY (no calibration data)

*.cal - save actual calibration data ONLY (no instrument state)

New!

Page 16


Feb.23, 2006

Instrument States and Cal Data

Limited Instrument State• Frequency range• Number of points• IF bandwidth• Sweep type• Sweep mode

• Alternate sweep• Port powers• Source attenuators• Receiver attenuators• Testset map

Extended Instrument State• Channels/Traces• Windows• Triggering• Format• Scale

• Averaging• Markers• Math/memory• Limits• More…

Pointer to Calset• Name• Description• GUID

Error Terms• Crosstalk (1,2)• Crosstalk (2,1)• Directivity (1,1)• Directivity (2,2)• Load match (1,2)• Load match (2,1)

• Reflection tracking (1,1)• Reflection tracking (2,2)• Source match (1,1)• Source match (2,2)• Transmission tracking (1,2)• Transmission tracking (2,1)

.cst

.sta

.cal

.csa

9

Page 17


Feb.23, 2006

Receiver calibrationReceiver calibration gives corrected absolute power reading (forunratioed traces as opposed to an S-parameter traces)

Often used with FOM for measurements like harmonics, TOI

Uses power-meter-corrected internal source as a reference (source power cal)

Now saved as a cal set

Multiple receiver cals requires separate channels for each cal

Source power calibrations• No change from current behavior• Saved as part of instrument states• Not saved in cal sets

New!

Page 18


Feb.23, 2006

Correction Indicator on Status Bar

C - Full correction“C” is displayed immediately after a calibration is performed or when a valid Cal Set is applied. If you require optimum accuracy, avoid adjusting the analyzer’s settings after calibration.

C* - Interpolated correction"C*" appears in the status bar when interpolation is used during a measurement.

C∆ − Changed settings"C∆" appears in the status bar when one or more of the following stimulus settings change. The resulting measurement accuracy depends on which parameter has changed and how much it has changed. For optimum accuracy, recalibrate using the new settings.

• Sweep time• IF bandwidth• Port power• Stepped sweep enabled/disabled

LowestNo correctionNo CorUncertainChangedC∆UncertainInterpolatedC*HighestFullC AccuracyCorrection levelSymbol

10

Page 19


Feb.23, 2006


Cal Registers



Offset Load Cal






Q&A

Page 20


Feb.23, 2006

TRL Calibration with 4-port 20 GHz PNA-L’s

Yes, it can be done! (requires firmware A.05.25 and later)

Is “true” TRL calibration, not an approximation like TRL*

Two-step (two-tier) calibration process:• Step 1: “Delta Match” calibration• Step 2: Normal TRL calibration

What is a “Delta Match” cal?• characterizes the difference (delta) between the source match

and load match of each port of the VNA• allows a VNA having a single reference receiver to

perform TRL-style calibrations (including Unknown-Thru)

Why 2 steps?

11

Page 21


Feb.23, 2006

Assumptions for TRL (and Unknown Thru)

8-term error model assume match at each test port remains constant, independent of whether it is a source or receiver

With real hardware, assumption is poor due to port switch

Generalized S-parameters for a two-port device:

1

11

2122

12

22

22

11

2122

12

11

11

2221

1211

1

1−

•

=

aa

aa

ab

ab

ab

ab

SSSS

Ideal S-parameters Switch correction Note: a11 = a1f ; a12 = a1

r

a21 = a2f ; a22 = a2

r

b1 a1 a2 b2

Page 22


Feb.23, 2006

Two-Port Four-Receiver VNAs (like PNA)Dual reflectometers replaced by splitters and 3-port couplers

Incident wave detection is still after the port switch

Switch corrections a12/a22 and a21/a11 can be directly measured

R1 R2

RF Source

LO

Test port 2

BA

Test port 1

12

Page 23


Feb.23, 2006

Test port 1 Test port 2

C DBA

Test port 3 Test port 4

R

Single Reference Receiver VNAs (like 4-Port PNA-L)Reference receiver is prior to port switchSwitch corrections cannot be directly measuredTRL* ignores switch correction terms by setting them to zero

1

22

22

11

2122

12

11

11

2221

1211

1001 −

•

≅

ab

ab

ab

ab

SSSS

TRL* sets switch correction to zero

Page 24


Feb.23, 2006

Alternative to Measuring Switch CorrectionsInstead of ignoring the switching terms, we can characterize the

match differences and then apply them during the TRL cal

To do so, we can restate the switch correction terms:

Gf and Gr are “delta-match” terms, and theycan be derived from an SOLT calibration

1

11

2122

121

21

21

11

2112

12

22

121

11

2122

12

1

1

1

1

1

1−−−

Γ

Γ=

=

f

r

ab

ab

ba

ab

ba

ab

aa

aa

Thru

SHORT

OPEN

LOAD

SHORT

OPEN

LOAD

13

Page 25


Feb.23, 2006

Delta Match Cal

Delta match cal characterizes internal match differences,so it can be performed…• with mixed connector types• with or without test port cables, in any combination• with adapters that can remain or be removed for subsequent TRL cals

Page 26


Feb.23, 2006

When is Delta Match Used?

Definitions• Flush thru: insertable, zero-length• Known thru: characterized (all 4 S-parameters)• Unknown thru: reciprocal (S21=S12); usually low-loss and well matched

YesTRL - Adapter RemovalNoECal Internal ThruYesECal Unknown Thru

YesTRL - Known ThruYesSOLT - Unknown ThruNoSOLT - Adapter Removal

NoSOLT - Known Thru(Includes Flush-Thru, Known-Thru and Minimized Thru)

Uses Delta Match?Cal Method

14

Page 27


Feb.23, 2006

Two Ways to Perform the Delta-Match Calibration

Global Delta Match

• Covers entire frequency range of instrument

• Interpolation used for TRL cals with smaller spans and/or less points

• Only one global delta match cal set can exist at a time

• Future: considering providing factory global delta match cal set

User Delta Match

• Perform a non-TRL calibration, such as mechanical SOLT, SOLR or ECal

• Save data as a normal user cal set

• Frequency range and number of points must be identical to that of the follow-on TRL calibration

• Interpolation is not used during the calibration, but can be used for measurements

Page 28


Feb.23, 2006

Performing the Global Delta Match Cal

Default Settings:Points: 1601IF BW: 100 HzFreq: 300 kHz -

20.1 GHz

User cannot changethese settings!

15

Page 29


Feb.23, 2006

Performing the Global Delta Match Cal

• Select DUT connectors (the only choice you have is in choosing the “DUT Port 1” connector)

• Add adapters to match those shown in the table

• ECal provides the easiest solution, especially with the new 4-port 20 GHz module (N4432/3A)

Page 30


Feb.23, 2006

With a 2-port ECal, it only takes two steps to complete the cal!Step 1 of 2: connect ECal to ports 1 and 2Step 2 of 2: connect ECal to ports 3 and 4

Using 2-Port ECal Modules

Note: when using a 2-port ECal module to perform the Global Delta Match calibration,

you must use an N4691B (300 kHz – 26.5 GHz)

16

Page 31


Feb.23, 2006

User Delta Match

Instead of selecting the Global Delta Match CalSet, select an available user CalSet that matches the current stimulus conditions

Page 32


Feb.23, 2006

Performing the TRL CalibrationCalibration > Calibration Wizard

17

Page 33


Feb.23, 2006

Here, as a test case, we created a cal kit definition using “probe” as connector type. In this cal kit, we defined Short, Thru and Line standards. Plus, we have given them TRL class assignments.

Use dropdown menu to select connectors.

Appropriate cal kits should appear based on connector type. Use dropdown menu to select Cal Kit.

Select this and the following screen will appear. Otherwise, the default uses the existing Global Delta Match Cal.”

Performing the TRL Calibration

Page 34


Feb.23, 2006

Select this to choose the “delta match” calset.

Select to modify thru path choices and cal standards.

Default is “minimum thru’s” (known bug: TRL always measures all paths, regardless of the status of this box)


18

Page 35


Feb.23, 2006

• Selecting “Mod Stds” brings up this screen • In this case, the default is TRL with Defined Thru• If you select another thru choice, then cal type will be SOLT• Generally, you do not need to select “View/Modify”

Click here to view class assignments


Page 36


Feb.23, 2006

• All cal sets will appear, but not all will work for delta match• Highlight the file you want and click OK• If you pick a “bad” user

cal set, you get this error:

Selecting “Choose Delta Match” brings up this screen Performing the TRL Calibration

19

Page 37


Feb.23, 2006

• At this point, the calibration should start.• Based on the “probe” cal kit we created, we went through the

following steps for a 3-port TRL cal:Step 1 of 9, short to port 1Step 2 of 9, short to port 2Step 3 of 9, thru between ports 1 and 2Step 4 of 9, line between ports 1 and 2Step 5 of 9, short to port 3Step 6 of 9, thru between ports 1 and 3Step 7 of 9, line between ports 1 and 3Step 8 of 9, thru between ports 2 and 3Step 9 of 9, line between ports 2 and 3


9

Page 38


Feb.23, 2006

What About Calibrating On-Wafer?

Because delta-match cal can be performed at any interface,on-wafer customers have the following options:• Use ECal (or mechanical cal kit) at the end

of the cables, before connecting to the probes (probes tend to have female connectors, sosimply add adapters to make up two pairs of insertable cals)

• Use the probes with a 4-port with SOLT ISS

Cascade’s WinCal 2006• Will not support 4-port TRL calibrations initially

• Allows advanced 2-port calibrations, such as the LRRM family

20

Page 39


Feb.23, 2006

Frequently Asked QuestionsCan I perform a 4-port TRL calibration?

-- Yes, simply follow the same steps covered in this presentation

Is TRL calibration limited to only 2 ports?-- No, it can be used with 3- or 4-port calibrations as well

Can I perform a 4-port TRL calibration on-wafer? -- Yes

Since the 4-port 20 GHz PNA-L has only one reference receiver, do I need a hardware upgrade before I can perform a TRL calibration?-- No, the 2-step calibration process does NOT require any hardware upgrade, but may require a firmware upgrade

Since the 4-port 20 GHz PNA-L has only one reference receiver, does this mean we can only do TRL*?-- No, the 2-step cal process provides true TRL calibration

Page 40


Feb.23, 2006

TRL Summary

TRL – first characterize the match differences with delta match cal and then use them during TRL calibration

4-port 20 GHz PNA-L with one reference receiver (switch occurs after the incident wave detector)

TRL* – ignore “switch correction” terms

Legacy 872x family with one reference receiver (switch occurs after the incident wave detector)

TRL – directly measure “switch correction” terms

PNA’s & 2-port PNA-L’s with dedicated two reference receivers (incident wave detectors occur after the switch)

New application note:On-Wafer Calibration Using a 4-Port 20 GHz PNA-L, 5989-2287EN

21

Page 41


Feb.23, 2006


Cal Registers



Offset Load Cal






Q&A

Page 42


Feb.23, 2006

Unknown Thru – Agilent’s Secret Weapon!

“Unknown Thru” (aka SOLR) algorithm is useful for both insertable and non-insertable calibrations

Traditional non-insertable methods:• Swap equal adapters• Use characterized thru (S-parameters known)• Perform adapter removal cal• Add adapters after cal, then, during measurement…

– use port extensions– de-embed adapters (S-parameters known)

22

Page 43


Feb.23, 2006

Compromises of Traditional Methods

Swap equal adapters• Need phase matched adapters of different sexes (e.g., f-f, m-f)• Error results from loss and mismatch differences of adapters

Use characterized thru• Multi-step process• Need a non-insertable cal to measure S-parameters of characterized thru

Perform adapter removal cal• Accurate but many steps in calibration (two 2-port calibrations)

Add adapters after cal, then, during measurement…• Use port extensions – doesn’t remove adapter mismatch effects• De-embed adapters (S-parameters known) – similar to characterized thru

Page 44


Feb.23, 2006

Non-Insertable ECal Modules

ECal resolves many, but not all non-insertable situations

23

Page 45


Feb.23, 2006

Unknown Thru to the Rescue!Unknown Thru calibration makes 2-port calibrations much easier!

No need for matched or characterized thru adapters!

Works great for

• Non-insertable calibrations

• Fixed port positions

• Physically looooooooong DUTs

• Port orientations that are not in-line

• Multiport devices Note: Unknown Thru only works with guided calibrations

Page 46


Feb.23, 2006

Unknown Thru Algorithm

Unknown thru algorithm uses “TRL” 8-term error model

α

EDF ESF

ERF/α

S11 S22

S21

S12b1m

a1m

b1

a1

a2

b2

β

ESR EDR

a2m

b2m

ERR/β

[ A ] [ T ] [ B ]a1

b1

b2

a2a2m

b2m

b1m

a1m

24

Page 47


Feb.23, 2006

Unknown Thru Calibration Requirements

Systematic errors of all test ports (directivity, source match, reflection tracking) can be completely characterized

“Unknown thru” calibration standard:• Must be reciprocal (Sij = Sji)• Phase known to within a quarter wavelength

VNA signal-path switch errors can be quantified• Requires dual reflectometers on all ports

(e.g., a 2-port 4-receiver VNA) OR• Requires delta-match correction

Page 48


Feb.23, 2006

Two-Port Unknown Thru Calibration SequenceMeasure open, short, load on port 1Measure open, short, load on port 2Measure insertable adapter (unknown thru)

between ports 1 and 2Confirm estimated electrical

delay of unknown thru

1-port calibrations

Unknown thru

Unknown Thru calibration is performed just like a “flush thru” 2-port calibration!

25

Page 49


Feb.23, 2006

Measuring Physically Long Devices (Usual Way)

2-PORT CALIBRATION PLANE

CABLE MOVEMENT


DUT

Page 50


Feb.23, 2006

Cable Movement Drift Error

-0.20

-0.18

-0.16

-0.14

-0.12

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.00 5.00 10.00 15.00 20.00 25.00 30.00

Frequency

dB

Good CableBad Cable

Cable Movement Error

26

Page 51


Feb.23, 2006

Measuring Physically Long Devices (Unknown Thru)

2-PORT CALIBRATION PLANES

DUT


Unknown thru

No cable movement!

Page 52


Feb.23, 2006

Measuring Devices with Non-Aligned Ports(Usual Way)


CABLE MOVEMENT

DUT


27

Page 53


Feb.23, 2006

Measuring Devices with Non-Aligned Ports(Unknown Thru)

DUT

Unknown thru1-PORT

CALIBRATION PLANES2-PORT

CALIBRATION PLANES

Page 54


Feb.23, 2006

Multiport and Non-Aligned Case (Usual Way)


3 PORT DEVICE

L

DUTA

C

B


CABLE MOVEMENT

28

Page 55


Feb.23, 2006

OR

L

L

Multiport and Non-Aligned Case (Usual Way)

3 PORT DEVICE

L

DUTA

C

B


CABLE MOVEMENT

DUT

A

C

B

DU

TA

C

B

CABLE MOVEMENTCABLE MOVEMENT

Page 56


Feb.23, 2006

Multiport and Non-Aligned Case (Unknown Thru)


ANY THRU DEVICE 3 PORT DEVICE

L

DUTA

C

B

29

Page 57


Feb.23, 2006

Multiport and Non-Aligned Case (Unknown Thru)


ANY RECIPROCOL 3-PORT THRU

3-PORT DEVICE

DUTA

C

BA

C

B

Page 58


Feb.23, 2006

Port 1

Port N

Port 2

Port 3

Port 1

Port N

Port 2

Port 3Unknown thru’s (adapters)

1-port calibrations, ECal or mechanical

Multiport Unknown Thru with Different Connectors

Different connector on each port

Finish multiport calusing unknown thru’s

30

Page 59


Feb.23, 2006

Port 1

Port 4

Port 2

Port 3

Port 1

Port 4

Port 2

Port 3Unknown thru’s

and/or

TRL on-wafer cal

On-Wafer Calibrations Using Unknown Thru’s

Imperfect thru’s

Straight Thru’s

Page 60


Feb.23, 2006

1.85 f-f adapter comparison

-0.25

-0.23

-0.20

-0.18

-0.15

-0.13

-0.10

-0.08

-0.05

-0.03

0.00

0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00Frequency GHz

Mag

nitu

de d

B

1.85 adapter removal cal 1.85 unknown thru cal

Unknown Thru and Adapter Removal Compared

31

Page 61


Feb.23, 2006

Long (Aspect Ratio) Device, 3.5 inch x 1 mm cable, Test Comparison

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.0E+00 2.0E+01 4.0E+01 6.0E+01 8.0E+01 1.0E+02

Frequency in GHz

Mag

nitu

de (d

B)

Unknown Thru Flush Thru

Unknown Thru and Flush Thru Compared

Page 62


Feb.23, 2006

Unknown Thru For Different Waveguide Bands

Watch out for these potential problems:1. Non-overlapping waveguide bands2. Attenuation near cutoff may be too high for thru calibration3. Higher-order modes

(longer adapters better attenuate undesired modes)

Higher cutoff frequencyLong enough?

Band X Band Y

Tapered or stepped adapter

32

Page 63


Feb.23, 2006

Known Thru Versus Unknown Thru

Any passive device OKCan not use any device

Bad connection not a problemCan not tolerate bad connection

NARequires periodic calibration

NACharacterization error sensitive to cable movement stability

NAS-parameters can change

Accuracy sensitive to ES and ER errorsAccuracy sensitive to ED, ES, S-parameter errors and thru S21

Requires S21=S12Requires data or model and VERY stable device

Unknown ThruKnown Thru

Page 64


Feb.23, 2006


Cal Registers



Offset Load Cal






Q&A

33

Page 65


Feb.23, 2006

Offset Load Calibration OverviewOffset load calibration originated with 8510

Offset load is a compound standard – load is connected multiple times with differing offsets

In simplest and most common form, there are just two connections: the load by itself, and the load with an offset

Similar to a sliding load standard, except offsets are set by a known, precise transmission line (e.g., a waveguide section)

Not the same as a load standard with defined delay, which is a single standard

Offset (shim)

Load

1. Measure load by itself 2. Measure load plus offset

offset

Page 66


Feb.23, 2006

Offset Load Calibration AdvantagesProvides higher directivity and load match accuracy when the definition of the offset is better known than the load definitionDoes not require a dual reflectometer VNA as it uses SOLT error model instead of TRL error modelIdeal for 1-port calibrationsAlso helpful in situations where calibration planes cannot physically move, such as fixed probe or waveguide positions, where TRL calibrations are difficultOffset standard can include loss term (especially valuable near cutoff frequency)

Probe Probe

Probe Probe

Not a good TRL standardAttenuation constant

in WR-159 waveguide

34

Page 67


Feb.23, 2006

Offset Load Definition

Only available in guided calibration (SmartCal)

Math is enhanced over what 8510 did

New FW added offset load standards to waveguide cal kits

Page 68


Feb.23, 2006

Offset Load Class AssignmentsSmartCal uses as many standards as it needs to complete calibration, based on frequency range of standards

In this case, only offset load is used

35

Page 69


Feb.23, 2006

Thru Loss Definition

8510 did not use loss term

PNA includes loss for better accuracy, especially near cutoff and with poor raw source match

Enter waveguide loss here (different model than coaxial loss model)

×r

co

ev

hf ρπµoffset loss (waveguide) =

µo = free space permeabilityfc = waveguide cut off frequencyp = resistivity of waveguide metalh = waveguide height (short dimension)v = velocity of lighter = permitivity of dielectric (usually air)

Page 70


Feb.23, 2006

Waveguide Connector Definition

New!

When defining waveguide cal kits,be sure to set Media to WAVEGUIDE

36

Page 71


Feb.23, 2006


Cal Registers



Offset Load Cal






Q&A

Page 72


Feb.23, 2006

Normalization (response cal)

Full 2/3/4-port corrections(SOLT, TRL, LRM...)

Port Extensions

DifficultyEasier HarderAccuracyLower Higher

Mod

elin

gD

irect

M

easu

rem

ent

De-embedding

Error Correction ChoicesPort extensions have gone APE!

37

Page 73


Feb.23, 2006

APE = Automatic Port Extensions

• First solution to apply both electrical delay and insertion loss to enhance port extensions

• First approach to give reasonable alternative to buildingin-fixture calibration standards or de-embedding fixture

1st

APE accounts for loss and phase of fixture transmission lines

Page 74


Feb.23, 2006

Automatic Port Extensions – Step 1

• First, perform coaxial calibration at fixture connectors to remove errors due to VNA and test cables

• At this point, only the fixture loss, delay and fixture mismatch remain as sources of error.

Coaxial calibration reference planes

38

Page 75


Feb.23, 2006

Automatic Port Extensions – Step 2• After coaxial calibration, connect an open or short to portion of fixture

being measured• Perform APE: algorithm measures each portion of fixture and computes

insertion loss and electrical delay• Values calculated by APE are entered into port extension feature• Now, only fixture mismatch remains as source of error

(dominated by coaxial connector).Coaxial calibration reference planes

Ports extended

Open or short placed at end of each

transmission line

Page 76


Feb.23, 2006

Measurement Results

Without Automatic Port

Extension

With Automatic Port Extension

Delay & loss compensation (values computed by APE)

DUT Opens

Stepped Impedance

Adjacent Structure

ShortsBalanced

Unbalanced

Balanced

Unbalanced

Balanced

Unbalanced

“Quattro”demo board

39

Page 77


Feb.23, 2006

Automatic Port Extension – Implementation

Measures Sii (reflection) of each portUses ideal open or short modelsComputes electrical delay using best-fit straight-line modelComputes insertion loss using a best-fit dielectric loss model

• Default setting uses frequencies in Active Channel Stimulus(results in loss at two frequencies)

• Active Marker choice uses frequency at Active Marker(results in loss at one frequency only)

Computed delay & loss values are automatically displayed via new port-extension tool bar

Values can be saved as part of instrument state or recorded for manual insertion next time

Page 78


Feb.23, 2006

How is the Loss Term Calculated?

Loss is calculated for each frequency data point (f) as follows:

If Use1 is checked and NOT Use2 then: • Loss(f) = Loss1 * (f/Freq1) ^ 0.5 (coaxial loss model)

If Use1 AND Use2 are checked, then:• Loss(f) = Loss1 * (f/Freq1) ^ n (printed circuit board dielectric loss model)• Where n = log10 [abs(Loss1/Loss2)] / log10 (Freq1/Freq2)

40

Page 79


Feb.23, 2006

Which Standards Should I Use?For broadband applications, shorts or opens work equally wellChoose the most convenient standard (often an open) –this is a key benefit of Automatic Port Extensions!Will using both an open and a short improve accuracy?• Using two standards makes little difference for broadband applications, as

many ripples occur and calculated loss is the same for open or short• Using two standards improves accuracy

for narrowband applications, where a full ripple cycle does not occur

Broadband

Calculated loss is basically same for open or short

open

short

Page 80


Feb.23, 2006

Broadband APE Example

Very little difference up to 10 GHz

APE with short

APE with open

DUT = short

No port extension applied

41

Page 81


Feb.23, 2006

Narrowband APE Example

400 MHz span

Large variation betweenopen and short

DUT = short

APE with short

APE with open

APE with both open and short

Page 82


Feb.23, 2006

Adjusting for Mismatch

Don’t adjust for mismatch

Adjust for mismatch

No port extension applied

Adjusting for mismatch keeps reflection below 0 dB

42

Page 83


Feb.23, 2006

Active Span or Active Marker

Note: when using active marker, selecting or not selecting “adjust for mismatch” makes no difference

APE using active marker

APE using active span

Page 84


Feb.23, 2006

Loss at DC

Offsets the entire freq span to account for a fixed loss (e.g. 3 dB attenuator)

Use positive value to compensate for loss added after APE

Fixture, no padFixture and 3 dB pad with DC loss compensation

Fixture and 3 dB pad

43

Page 85


Feb.23, 2006

Summary of Automatic Port Extensions

Ideal for in-fixture applications where complete calibration standards are not available

Eliminate the need to design and build difficult load standards

Applicable to a wide range of fixture designs

Works with probes too

Easy to use and quick to get results

1st

50

Page 86


Feb.23, 2006


Cal Registers



Offset Load Cal






Q&A

44

Page 87


Feb.23, 2006

Fixturing for the Masses

Fixturing features are same or similar to 4-port PNA-L, ENA, and PLTS

Page 88


Feb.23, 2006

Order of Fixturing Operations

First, single-ended functionsare processed in this order:• Port extensions• 2-port de-embedding• Port Z (impedance) conversion• Port matching / circuit embedding• 4-port network embed/de-embed

Then, balanced functions areprocessed in this order:• Balanced conversion• Differential- / common-mode port Z conversion• Differential matching / circuit embedding

Example circuit simulation

45

Page 89


Feb.23, 2006

Port Matching

Port matching feature is same as embedding

Page 90


Feb.23, 2006

Differential Port Matching

46

Page 91


Feb.23, 2006

Port Z (Impedance) Conversion

Zs

Page 92


Feb.23, 2006

Differential Port Z (Impedance) Conversion

Zs

Zs

Zs

47

Page 93


Feb.23, 2006

2-Port De-Embedding

In all cases, the assumption is:• Port 1 of the fixture is connected to the PNA• Port 2 of the fixture is connected to the DUT

1 2.s2p file .s2p file

2 1

Fixture A Fixture B

DUT

If “Fixture B” is measured in the forward direction, the columns in the .s2p file must be swapped:

S11 S22S21 S12

Page 94


Feb.23, 2006

4-Port Embedding/De-Embedding

For one-port balanced devices

For balanced to single-ended devices

For two-port balanced devices

48

Page 95


Feb.23, 2006

Two Versus Four Port Embedding / De-Embedding

Question: On a balanced port, what is the difference between:• Two .s2p embedding/de-embedding files• One .s4p embedding/de-embedding files

Answer: Crosstalk terms!

.s2p file

.s2p fileDUTPNA

1

2

.s4p file DUTPNA1

2

Cannot simulate fixture leakage between PNA ports 1 and 2

Can use full leaky model to simulate fixture

Page 96


Feb.23, 2006

Don’t Forget to Turn Fixturing On!

49

Page 97


Feb.23, 2006

On-wafer SMC MeasurementsPrevious versions of FCA (Option 083) did not allow on-wafer measurements using Scalar Mixer Cal (SMC)

A.06.xx allows embedding of probe data files during SMC

Perform power-meter and S-parameter calibrations in coax

After coax calibrations, reference plane is at probe tip

Power-meter and S-parameter

calibration plane

Extended (de-embedded) measurement plane

.s2p data

Page 98


Feb.23, 2006


Cal Registers



Offset Load Cal






Q&A

50

Page 99


Feb.23, 2006

How Do I Get My Probe De-Embedding Data?

Perform an SOLT or TRL cal using wafer probes

Measure thru device and save data in .s2p file for de-embedding in later step

Probe

Measure thru after 2-port calibration

Probe

2-port calibration planes

Thru

Page 100


Feb.23, 2006

How Do I Get My Probe De-Embedding Data?

Perform an adapter removal calibration using coaxial and on-wafer standards

Probe Probe

Final 2-port calibration planes

Probe Probe2-port cal

“Adapter”

coaxial cal

Probe Probe2-port cal

wafer cal

51

Page 101


Feb.23, 2006

How Do I Get My Probe De-Embedding Data?Measure thru plus probe

De-embed swapped thru data to obtain probe data

Save probe data in .s2p file for later use in measuring DUTs

Repeat for other probe(s) if desired

ThruProbeProbe


DUT De-embed swapped thru data from DUT

data to get probe dataProbe


2 1DUT

Page 102


Feb.23, 2006

Alternate Way to Get Probe + Thru DataPerform unknown thru cal in coax and with probeMeasure thru plus probeDe-embed swapped thru data to obtain probe dataSave probe data in .s2p file for later use in measuring DUTsRepeat for other probe(s) if desired

ThruProbeProbe


Unknown thru and DUT De-embed swapped thru data from DUT

data to get probe dataProbe


2 1DUT

52

Page 103


Feb.23, 2006

How Do I Get My Fixture De-Embedding Data?

Perform an unknown thru cal using coax on one side, a probe on the other side, and the fixture itself for the unknown thru

Measure the fixture section and save data as .s2p file

Repeat for each section of fixture

Probe


Unknown thru and DUT

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