Sem5 ae nota v1
Transcript of Sem5 ae nota v1
LECTURE 01 SSCP3323-Advanced Electronics 1
SSCP 3323 – ADVANCED ELECTRONICS
Pre-requisites : Basic Electronics
Lecturer : Assoc. Prof. Dr. Yaacob Mat Daud
Room : C21-314
Contacts
Tel. : 07 - 5534070
Mobile : 012 - 7581247
e-mail : [email protected]
LECTURE 01 SSCP3323-Advanced Electronics 2
Synopsis
This course is designed to expose the students to
• small signal analysis using an equivalent circuit h-parameter
• analysis of simple circuits such as:
• Filters
• wave generators
• Oscillators
• basic digital system
At the end of the course, students should be able to
• analyze small signal amplifier and analyze simple circuits
• explain various logic principles and devices employed in digital system, as
well as the function of digital circuit in the development of a simple computer
LECTURE 01 SSCP3323-Advanced Electronics 3
Synopsis
This course introduces students to the basic concepts and knowledge
of the analogue and digital electronics.
For the analogue part, the transistor circuits, small signal amplifiers,
power amplifies, differential amplifiers, operational amplifiers (OPAMP)
and its application circuits are discussed.
For the digital part, basic concepts and principles in understanding
digital circuits and systems including number codes and systems,
Boolean algebra, logic gates, Karnaugh maps, IC specification and
interfacing, encoding and decoding, flip-flops, counters, shift registers
and digital arithmetic circuits are discussed.
LECTURE 01 SSCP3323-Advanced Electronics 4
Learning Outcomes
After completing this course, the student must have the ability to:
1. State and explain the characteristics and equation of the transistor
equivalent circuits model
2. Analyze and solve the various type of amplifier circuit problems
3. State and explain the characteristics and operations of the OPAMP
4. Design the OPAMP circuits for simple application
5. State the characteristics and specifications of the TTL and CMOS digital
ICs
6. State and explain the principle of digital systems and devices such as logic
gates, encoders, decoders, flip-flops, counters and shift registers
7. Explain and solve problems involving digital arithmetic circuits
LECTURE 01 SSCP3323-Advanced Electronics 5
Evaluation
The evaluation will be based on the following:
Test 1 : 10%
Test 2 : 10%
Assignments (6) : 30%
Total Course Work : 50%
Final Exam. : 50%
LECTURE 01 SSCP3323-Advanced Electronics 6
Text and References
Text Book:
Donald A. Neamen – MICROELECTRONICS Circuit
Analysis and Design, 3rd Edition, 2007, McGraw-Hill.
References:
1. T.F. Bogart Jr., J.S. Beasley and G. Rico, ELECTRONIC
DEVICES AND CIRCUITS, Prentice Hall
2. A.P. Malvino, ELECTRONIC PRINCIPLES, McGraw-Hill
3. Roger L. Tokheim, DIGITAL ELECTRONICS, McGraw-
Hill
LECTURE 01 SSCP3323-Advanced Electronics 7
Quick Review
What are DC and AC ?
DC (Direct Current)
The polarity (sign) of the voltage/current does not change
Examples:
Constant DC voltage DC wave voltage
LECTURE 01 SSCP3323-Advanced Electronics 8
Quick Review
AC (Alternating Current)
The polarity (sign) of the voltage/current changes periodically with
time
Examples:
LECTURE 01 SSCP3323-Advanced Electronics 9
Quick Review
LECTURE 01 SSCP3323-Advanced Electronics 10
Quick Review
Electronic Components
1. Source
Current source
LECTURE 01 SSCP3323-Advanced Electronics 11
Quick Review
2. Passive components
LECTURE 01 SSCP3323-Advanced Electronics 12
Quick Review
LfLXL 2
Reactance
Capacitor :
Inductor :
For DC (f 0)
Capacitor : XL 0
Inductor : XC
)2/(1/1 CfCXC
LECTURE 01 SSCP3323-Advanced Electronics 13
Quick Review
Resistors
Its nature that opposes the current is independent of
frequency
Capacitors
When frequency increases, the opposition to the current
decreases
Inductors
When the frequency decreases, the opposition to the
current increases
LECTURE 01 SSCP3323-Advanced Electronics 14
Quick Review
Transformers
LECTURE 01 SSCP3323-Advanced Electronics 15
Quick Review
3. Active Components
Semiconductor Devices
Diode
LECTURE 01 SSCP3323-Advanced Electronics 16
Quick Review
LECTURE 01 SSCP3323-Advanced Electronics 17
Quick Review
LECTURE 01 SSCP3323-Advanced Electronics 18
Quick Review
LECTURE 01 SSCP3323-Advanced Electronics 19
Quick Review
LECTURE 01 SSCP3323-Advanced Electronics 20
Quick Review
Circuit Analysis/Problem Solving
LECTURE 01 SSCP3323-Advanced Electronics 21
Quick Review
LECTURE 01 SSCP3323-Advanced Electronics 22
Quick Review
Manufacturing has many distinct forms that can be classified into
five groups
• Project
• Job shop
• Repetitive
• Line
• Continuous
Overlap between categories cannot be avoided, and most
companies use two or more of the manufacturing system in the
production of an entire production line.
INDUSTRIAL ELECTRONICS
Manufacturing Classification
Project
Product are complex, have many parts and most often one of a kind.
Example to built oil refineries, large office buildings, cruise ship, large aircraft,
large shopping complex etc.
The production and assembly labor is mostly manual, with machines used make
some of the component parts.
The equipment and parts are moved to the construction site, and the product is
not moved until it is finished.
INDUSTRIAL ELECTRONICS
Manufacturing System Classification
Job shop
Non-complex products with few parts and small production volume.
The size and weight of parts are very small.
Parts are moved or routed between fixed production work cells and machines
for material processing.
Combination of manual and automated machines are used to produce the parts.
The low production volume prohibits the use of production automation in most
cases and requires a significant level of manual labor.
Machining a nonstandard-size bearing for a pump is an example of a job shop
order.
INDUSTRIAL ELECTRONICS
Manufacturing System Classification
Repetitive
Order approach 100%, multiple layer contracts on products is common, and
production quantity varies widely but is generally high.
Because the product orders are predictable and spread over long periods,
automated processes and special-purpose automation is often used.
The manual labor component is present, but it is usually much smaller than the
automated element.
Example include components for automotive industry like water pumps,
alternators, and transmissions.
INDUSTRIAL ELECTRONICS
Manufacturing System Classification
Line
The delivery time required by the customer is often shorter than the total time it
take to build the product.
The product has many options or models.
An inventory of subassemblies is normally present.
Automotive production is a good example. A complete car is assembled in a
matter of hours because most of the parts (i.e. the engine, seats..) are
assembled and ready to be placed in the car.
Can have large manual labor and automation components for some products
and totally automated process with no manual labor for another.
INDUSTRIAL ELECTRONICS
Manufacturing System Classification
Continuous
The term continuous manufacturing describes a flow of products from a
manufacturing system that is never interrupted.
Examples of products include breakfast cereal, soft drinks, mouthwash, and
toothpaste. Raw materials enter on one end, and finished products flow from
the other end.
The system stops for product changeover or cleaning, then restarts. The
products produced in this method are frequently products that customers
must be able to buy whenever they desire. Products produced with this
technique have a steady and predictable product demand, must have a
finished goods inventory, have high product volume, and are products with
few options. Systems producing this type of product are highly automated
with little manual labor.
INDUSTRIAL ELECTRONICS
Manufacturing System Classification
Figure 1 integrates the manufacturing systems with the classification categories
for industrial automation.
The horizontal axis has the machine and system groups arranged from least
complex on the left end to most complex on the right end.
Above the axis, the manufacturing system are positioned to indicate the type of
industrial machines and system most commonly used.
For example, the repetitive bar starts to the left of programmable machines and
extends past flexible manufacturing systems (FMCS). This indicates that a
repetitive-type production system might use any of the technologies from
programmable machines to FMCS to build the system.
INDUSTRIAL ELECTRONICS
Manufacturing Systems and Industrial
Electronics / Automation
INDUSTRIAL ELECTRONICS
Figure 1: Manufacturing Systems and
Industrial Electronics / Automation
Figure 1 also illustrates the degree of automation present in each of the
manufacturing systems compared to their manual labor components.
The shaded area in each of the bars indicates the labor portion that would
likely be manual. For example, the project type is almost entirely manual, while
the continuous type has the smallest manual labor component.
The automated portions of the systems use hardware and software from the
industrial control technologies listed across the bottom of the figure.
INDUSTRIAL ELECTRONICS
Manufacturing Systems and Industrial
Electronics / Automation
Therefore, the area of the graph to the right of the dashed line indicates the
demand for industrial electronic skills.
It is easy to see that industries using the repetitive, line, and continuous
manufacturing systems need engineers and technicians with these skills.
The technologies present in the area to the right of the dashed line are
highlighted in the technology pyramid illustrated in Figure 2
INDUSTRIAL ELECTRONICS
Manufacturing Systems and Industrial
Electronics / Automation
INDUSTRIAL ELECTRONICS
Figure 2: TECHNOLOGY PYRAMID
The technology pyramid in Figure 2 illustrates a set of necessary
competencies for the engineers and technicians who design, build, test,
program, and maintain automated production systems.
The three levels at the bottom of the pyramid focus on learning the
devices that are the building blocks for industrial automation.
In the bottom three levels, devices as simple as a push-button switch
and as complex as an operational amplifier are covered.
INDUSTRIAL ELECTRONICS
TECHNOLOGY PYRAMID
The switches, transistors, operational amplifiers, and AC switching
devices identified in the first three levels are used to build the discrete
and analog sensors at the next highest level.
Safety is level 5 because it is a high priority in industry and
understanding of it is needed before proceeding to the higher levels.
The sensors and motors in levels 4 and 6 and solid-state principles are
components for the controllers in level 7.
INDUSTRIAL ELECTRONICS
TECHNOLOGY PYRAMID
Level 8 covers open- and closed-loop process control and robots used
in industrial automation such as computer numerical controlled mills and
lathes, and systems to move, store, and track material and assembled
products.
The systems identified in level 8 are built using the devices and
concepts in the first seven levels. The top level, called data networking,
describes how the information from all of the different industrial
automation systems is transferred between the automated machines
and systems. The pyramid gives you a snapshot of technologies.
INDUSTRIAL ELECTRONICS
TECHNOLOGY PYRAMID
LECTURE 02 SSP 2323 - Advanced Electronics 1
BJT Amplifier Analysis Using h-Parameters
Introduction
There are three simple
configurations of BJT
amplifiers: common-emitter,
common-collector, and
common-base
We will look at the the
common-emitter because it
provides voltage gain
The figure shows a typical
CE amplifier
+VCC
RC
vs
B
C
E
R1
C1
C2
RE
R2
RL
RS
LECTURE 02 SSP 2323 - Advanced Electronics 2
BJT Amplifier Analysis Using h-Parameters
The purpose of the analysis is to determine various quantities
related to the amplifier, such gain, input and output impedances
To analyze the circuit we need to use a model of the amplifier
A basic amplifier model of all amplifiers is as shown below:
RS
vin
Zin A
v v
in
Zout
vout
General Amplifier Model
LECTURE 02 SSP 2323 - Advanced Electronics 3
BJT Amplifier Analysis Using h-Parameters
The amplifier model represents input conditions, the amplification
factor or gain (hFE or ), and output conditions
The signal source has some internal resistance and is shown as RS
The transistor can be shown as input impedance (Zin), a voltage
source (vin), the output voltage (vout), and some output impedans
(Zout)
The value of vout is vin times the voltage gain (Av) of the transistor
vout is the voltage developed across the load resistance (RL)
As vin changes, vout changes by a factor of Av
LECTURE 02 SSP 2323 - Advanced Electronics 4
BJT Amplifier Analysis Using h-Parameters
TWO PORT NETWORKS – h-PARAMETER BJT MODEL
Depending on the application, it may be used in a number of
different ways to develop different models
We will use it to develop the h-parameter model
The h-parameter model is typically suited to transistor circuit
modeling. It is important because:
its values are used on specification sheets
it is one model that may be used to analyze circuit behavior
it may be used to form the basis of a more accurate transistor
model
LECTURE 02 SSP 2323 - Advanced Electronics 5
BJT Amplifier Analysis Using h-Parameters
The h - parameter model has values that are complex numbers that
vary as a function of:
Frequency
Ambient temperature
Q-Point
A two-port network is shown below:
Two-port active device
LECTURE 02 SSP 2323 - Advanced Electronics 6
BJT Amplifier Analysis Using h-Parameters
We may select two of the four quantities as the independent
variables and express the remaining two terms of the chosen
independent variables
If the current i1 and the voltage v2 are independent and if the two-
port is linear, we may write
2121111 vhihv
2221212 vhihi
The quantities h11, h12, h21, h22 are the h, or hybrid, parameters
because they are not all alike dimensionally
LECTURE 02 SSP 2323 - Advanced Electronics 7
BJT Amplifier Analysis Using h-Parameters
Then, the h parameters are defined as follows :
01
111
2
iv
hi
vh
This is defined as input resistance
with output short circuited (ohm)
02
112
1
ri
hv
vh
This is defined as reverse open–
circuit voltage gain (dimensionless)
01
221
2
fv
hi
ih
02
222
1
oi
hv
ih
This is defined as forward short-
circuit current gain (dimensionless)
This is defined as output conductance
with input open circuited (mho)
LECTURE 02 SSP 2323 - Advanced Electronics 8
BJT Amplifier Analysis Using h-Parameters
Rewrite:
211 vhihv ri
212 vhihi of
The Model:
Hybrid circuit
LECTURE 02 SSP 2323 - Advanced Electronics 9
BJT Amplifier Analysis Using h-Parameters
TRANSISTOR HYBRID MODEL
Consider the common emitter configuration,
sticscharacteri input ),(1 CEBBE vifv
sticscharacteri output ),(2 CEBC vifi
Using Taylor’s series expansion and neglecting higher order terms,
CE
ICE
BEB
VB
BEBE v
v
vi
i
vv
BCE
CE
ICE
CB
VB
CC v
v
ii
i
ii
BCE
LECTURE 02 SSP 2323 - Advanced Electronics 10
BJT Amplifier Analysis Using h-Parameters
Rewrite
ce
ICE
BEb
VB
BEbe v
v
vi
i
vv
BCE
ce
ICE
Cb
VB
Cc v
v
ii
i
ii
BCE
or
cerebiebe vhihv
ceoebfec vhihi
LECTURE 02 SSP 2323 - Advanced Electronics 11
BJT Amplifier Analysis Using h-Parameters
Subscript e indicates common emitter configuration, and
0
ceCE vb
be
VB
BEie
i
v
i
vh
0
bBice
be
ICE
BEre
v
v
v
vh
0
ceCE vb
c
VB
Cfe
i
i
i
ih
0
bBice
c
ICE
Coe
v
i
v
ih
LECTURE 02 SSP 2323 - Advanced Electronics 12
BJT Amplifier Analysis Using h-Parameters
Summary
LECTURE 02 SSP 2323 - Advanced Electronics 13
BJT Amplifier Analysis Using h-Parameters
LECTURE 03 SSP 2323 - Advanced Electronics 1
BJT Amplifier Analysis Using h-Parameters
BJT Amplifier Analysis Using h-Parameters
The common-emitter (CE) h-parameter model for a BJT amplifier is
shown below :
h - parameter model for CE
LECTURE 03 SSP 2323 - Advanced Electronics 2
BJT Amplifier Analysis Using h-Parameters
For the configuration, we note from KCL that
cbe iii
The circuit models and equations are valid for either an npn or a
pnp transistor and are independent of the type of load or the
method of biasing
The h-parameters can be obtained graphically from the transistor
characteristics
LECTURE 03 SSP 2323 - Advanced Electronics 3
BJT Amplifier Analysis Using h-Parameters
For example, the parameters hfe and hoe can be obtained from the
output characteristics of the CE transistor
Similarly the parameters hre and hie can be obtained from the input
characteristics
The h-parameters will depend on the temperature and the
quiescent point
Manufacturers usually provide curves of h-parameters versus
temperature, VCE and IC
LECTURE 03 SSP 2323 - Advanced Electronics 4
BJT Amplifier Analysis Using h-Parameters
Graphical Representation of h-Parameter for BJT Small-Signal
Model Small-signal models for the BJT describe the operation of the
transistor as a linear amplifier of small AC signals
They make use of the relative linearity of the base and collector
curves near the Q point, and are quite useful if the transistor
voltages and currents remain within some range near the Q point
We will use the convention that each voltage and current is the sum
of a DC component (the quiescent value, denoted by uppercase)
and a small-signal AC component (Δuppercase). Subscript Q
indicates a value at the Q point:
LECTURE 03 SSP 2323 - Advanced Electronics 5
BJT Amplifier Analysis Using h-Parameters
h-Parameter Small-Signal Model
LECTURE 03 SSP 2323 - Advanced Electronics 6
BJT Amplifier Analysis Using h-Parameters
Parameter hie represents the forward resistance of the BE junction
and equals the slope of the IB - VBE curve at the Q point
Parameter hre indicates the small dependence of the IB-VBE curve
on the value of VCE. We can usually assume that hre = 0
LECTURE 03 SSP 2323 - Advanced Electronics 7
BJT Amplifier Analysis Using h-Parameters
Parameter hfe represents the current gain of the transistor and is
approximately equal to β
Parameter hoe represents the slope of the IC-VCE curves in the
linear active region, indicating that they are not flat
LECTURE 03 SSP 2323 - Advanced Electronics 8
ANALYSIS USING h-PARAMETER
Analysis of a BJT Amplifier Using h-Parameters
Objectives of the analysis are to find:
Current gain, AI = IL/I1 = - I2/I1
Input impedance, Zi = V1/I1
Voltage gain, Av = VL/V1
Output impedance, Zo = V2/I2 with Vs = 0 and ZL=
LECTURE 03 SSP 2323 - Advanced Electronics 9
ANALYSIS USING h-PARAMETER
Assumption:
Sinusoidal varying voltages and currents
h-parameters remain substantially constant over the operating
range
To form a transistor amplifier, it is only necessary to connect an
external load and signal source, as shown below, and to bias the
transistor properly
A two-port network equivalent of a transistor amplifier
LECTURE 03 SSP 2323 - Advanced Electronics 10
ANALYSIS USING h-PARAMETER
This two-port active network represents a transistor in any one of
the three possible configurations
When the active network in the circuit is replaced by the small-
signal hybrid model of the transistor, the circuit becomes
A two-port network with small-signal hybrid model
LECTURE 03 SSP 2323 - Advanced Electronics 11
ANALYSIS USING h-PARAMETER
Using h-parameter model,
The current gain, or current amplification, AI
For the transistor amplifier stage, AI is defined as the ratio of output
to input currents, or
From the figure,
211 VhIhV ri
212 VhIhI of
1
2
1 I
I
I
IA L
I
LLL ZIZIV 22
LECTURE 03 SSP 2323 - Advanced Electronics 12
ANALYSIS USING h-PARAMETER
Substituting V2 into the previous equation gives
)( 212 Lof ZIhIhI
12 )1( IhZhI fLo
Lo
fI
Zh
h
I
IA
11
2
LECTURE 04 SSP 2323 - Advanced Electronics 1
ANALYSIS USING h-PARAMETER
The Input Impedance Zi
The resistance Rs in the figure represents the signal-source
resistance
The impedance seen looking into the amplifier terminals (1, 1’) is
the amplifier input impedance Zi, or
Dividing equation by I1, gives
1
1
I
VZ i
211 VhIhV ri
1
2
1
1
I
Vhh
I
VZ rii
LECTURE 04 SSP 2323 - Advanced Electronics 2
ANALYSIS USING h-PARAMETER
Substituting V2 into the above equation gives
Substituting AI into the above equation gives
ILriLL
ri AZhhI
ZIhh
I
V
11
1 )(
Lo
Lfrii
Zh
Zhhh
I
VZ
11
1
LECTURE 04 SSP 2323 - Advanced Electronics 3
ANALYSIS USING h-PARAMETER
The Voltage Gain, or Voltage Amplification, Av
The ratio of output voltage V2 to input voltage V1 gives the voltage
gain of the transistor, or
Substitute V2 and V1 into the above equation gives
1
2
V
VA v
i
LI
i
LLv
Z
ZA
ZI
ZIA
1
LECTURE 04 SSP 2323 - Advanced Electronics 4
ANALYSIS USING h-PARAMETER
Voltage gain taking into account the source resistance
This gain is defined as
The Thevenin’s equivalent for the source is shown below
sv
ssV
V
VA
VV
VV
V
VA
s
1
1
122
Thevenin’s equivalent for the source
LECTURE 04 SSP 2323 - Advanced Electronics 5
ANALYSIS USING h-PARAMETER
From the Thevenin’s equivalent for the source
Substitute V1 into the equation of gain above gives
Substitute Av into the equation gives
ssi
i VRZ
ZV
1
si
ivV
RZ
ZAA
s
si
LIV
RZ
ZAA
s
LECTURE 04 SSP 2323 - Advanced Electronics 6
ANALYSIS USING h-PARAMETER
Current gain AIs taking into account the source resistance
This gain is defined as
The Norton’s equivalent for the source is shown below
sI
ssI
I
IA
II
II
I
IA
s
1
1
122
Norton’s equivalent for the source
LECTURE 04 SSP 2323 - Advanced Electronics 7
ANALYSIS USING h-PARAMETER
From the Norton’s equivalent for the source
Hence
Note that, if Rs = , then AIs = AI.
ssi
s IRZ
RI
1
Isi
sI A
RZ
RA
s
LECTURE 04 SSP 2323 - Advanced Electronics 8
ANALYSIS USING h-PARAMETER
Hence AI is the current gain for an ideal current source Independent of the transistor characteristics, the voltage and
current gains, taking source impedance into account are related as
The output admittance
By definition, the output impedance
s
LIsV
R
ZAA
s
oo
YI
VZ
1
2
2
LECTURE 04 SSP 2323 - Advanced Electronics 9
ANALYSIS USING h-PARAMETER
This is obtained by setting the source voltage Vs to zero and the
load impedance ZL to infinity, and driving the output terminal from a
generator V2 and drawing a current of I2
with Vs = 0 and RL =
But,
Divide this equation by V2:
2
2
V
IYo
212 VhIhI of
of hV
Ih
V
I
2
1
2
2
LECTURE 04 SSP 2323 - Advanced Electronics 10
ANALYSIS USING h-PARAMETER
Applying KVL at the input terminal:
Substitute the above equation in Yo gives
21)(0 VhIRh rsi
si
r
Rh
h
V
I
2
1
si
rfoo
Rh
hhh
V
IY
2
2
LECTURE 04 SSP 2323 - Advanced Electronics 11
ANALYSIS USING h-PARAMETER
Summary
Table 1 – Small-signal analysis of a transistor amplifier
LECTURE 05 SSP 2323 - Advanced Electronics 1
ANALYSIS USING h-PARAMETER
Equivalent Circuit
An equivalent circuit is a simplified version of the original amplifier
circuit obtained when considering the flow of DC or AC current in
the circuit.
A capacitor appears as an open circuit and an inductor appears as
a short circuit to DC current flow.
Conversely, a capacitor appears as a short circuit and an inductor
appears as an open circuit to AC current flow.
Hence, for an amplifier circuit there are two types of equivalent
circuit, i.e. the DC equivalent circuit (also known as the bias circuit)
and the AC equivalent circuit.
LECTURE 05 SSP 2323 - Advanced Electronics 2
ANALYSIS USING h-PARAMETER
DC Equivalent Circuit
DC equivalent circuit of an amplifier circuit is obtained by
open circuiting all capacitors and short circuiting all
inductors found in the circuit.
For example, consider the amplifier circuit in figure (a).
After open circuiting all the capacitors in the amplifier
circuit, the DC equivalent circuit is obtained as shown in
Figure (b).
LECTURE 05 SSP 2323 - Advanced Electronics 3
ANALYSIS USING h-PARAMETER
Figure (a) Figure (b)
+ VCC
R1
R2
RC
RE
+ VCC
R1
R2
RC
RE
CE
C1
C2
LECTURE 05 SSP 2323 - Advanced Electronics 4
ANALYSIS USING h-PARAMETER
AC Equivalent Circuit
AC equivalent circuit of an amplifier circuit is obtained by short circuiting all capacitors and open circuiting all inductors found in the circuit.
Coupling capacitors may be regarded as short-circuits to the AC signal, and therefore need not be included, together with any resistors which themselves are short circuited by capacitors
The DC supply in the amplifier circuit is a very low resistance path to the signal frequencies and can be replaced (in the AC equivalent circuit only!) by a short circuit.
LECTURE 05 SSP 2323 - Advanced Electronics 5
ANALYSIS USING h-PARAMETER
Example:
+ VCC
R1
R2
RC
RE
CE
C1
C2
+ VCC
R1
R2
RC
LECTURE 05 SSP 2323 - Advanced Electronics 6
ANALYSIS USING h-PARAMETER
+ VCC
R1
R2
RC R
1
R2
RC
Sumber
unggul
Rs
= 0
VCC
LECTURE 05 SSP 2323 - Advanced Electronics 7
ANALYSIS USING h-PARAMETER
R1
R2
RC R
1
R2
RC
LECTURE 05 SSP 2323 - Advanced Electronics 8
ANALYSIS USING h-PARAMETER
Finally….
R1
B
E
C
E
hre
vce
hfe
ib
hoe
hie
R2
RC
R2
R1
RC
AC Equivalent Circuit Hybrid Parameter Circuit
LECTURE 05 SSP 2323 - Advanced Electronics 9
ANALYSIS USING h-PARAMETER
Example
The transistor used as an amplifier in a circuit has the h-parameters as shown in the Figure below:
(a) Draw the equivalent circuit
(b) Calculate
(i) the effective input resistance,
(ii) the output resistance,
(iii) the current gain, and
(iv) the voltage gain,
if component values are as follows:
R1 = 47 k, R2 = 10 k and RL = 1.5 k
LECTURE 05 SSP 2323 - Advanced Electronics 10
ANALYSIS USING h-PARAMETER
The Amplifier Circuit:
LECTURE 05 SSP 2323 - Advanced Electronics 11
ANALYSIS USING h-PARAMETER
The hybrid parameter equivalent circuit:
LECTURE 05 SSP 2323 - Advanced Electronics 12
ANALYSIS USING h-PARAMETER
Solution
(a) The effective input resistance is the result of R1, R2 and
hie in parallel.
hie = 8.8 k
Thus
k 3.4
1111
21
in
iein
R
hRRR
The larger the values of R1 and R2, the closer Rin will
be to the value of hie.
LECTURE 05 SSP 2323 - Advanced Electronics 13
ANALYSIS USING h-PARAMETER
(b) The output resistance is the reciprocal of hoe.
hoe = 60 S
Thus
Rout = (1/ hoe)
which gives Rout = 16.7 k
(c) The current gain (Ai) is given by Ib/Ic.
where R’L is the result of RL and 1/hoe in parallel.
Lbfece
L
cec RIhV
R
VI and
LECTURE 05 SSP 2323 - Advanced Electronics 14
ANALYSIS USING h-PARAMETER
The ‘minus’ signs here are the result of the assumed direction of
the output current.
Thus,
552 k 1.5
k 1.38 x 600 gain current
k 1.38 giving
k 16.71
and k 38.1
)( gain current and
L
out
oe
L
L
Lfe
b
ci
L
Lbfec
R
Rh
R
R
Rh
I
IA
R
RIhI
LECTURE 05 SSP 2323 - Advanced Electronics 15
ANALYSIS USING h-PARAMETER
(d) The voltage gain (Av) is given by Vce/Vbe.
192 - k 4.3
k 38.1600
gain voltage thus
,k 3.4
and
in
Lfe
be
cev
in
inbbeLbfece
R
Rh
V
VA
R
RIVRIhV
The ‘minus’ sign represents the 180 phase shift between
output and input signal voltages for the common emitter
amplifier
LECTURE 05 SSP 2323 - Advanced Electronics 16
ANALYSIS USING h-PARAMETER
Important Points
If the effect of hoe is negligible, which is sometimes the
case, then R’L becomes RL, resulting in the current and
voltage gains being as follows
in
Lfev
fei
R
RhA
hA
)( gain Voltage
)( gain Current
Further more, if Rin = hie, then
ie
Lfev
h
RhA )( gain Voltage
LECTURE 07 SSP 2323 - Advanced Electronics 1
The Hybrid- Model of BJT
Introduction
Since long, industrial and educational institutions have heavily relied
on the hybrid parameters because they produce more accurate
results in the analysis of amplifier circuits
In fact, hybrid-parameter equivalent circuit continues to be popular
even today
But their use is beset with the following difficulties:
– The values of h-parameters are not so readily available
– Their values vary considerably with individual transistors even of the same type
number
– Their values are limited to a particular set of operating conditions for reasonably
accurate results
– The dominant model used for small-signal analysis of a BJT in the forward-active
region, the h-parameter model, does not contain frequency sensitive elements
and is therefore invariant with respect to changes in frequency
LECTURE 07 SSP 2323 - Advanced Electronics 2
The Hybrid- Model of BJT
It is therefore necessary to
introduce a new BJT model or
to reinterpret an old model to
include frequency-dependent
terms using the Ebers-Moll
model as a basis for creating
the new model
Consider the base current
versus base emitter voltage
characteristics, with small
time-varying signals
superimposed at the Q-point,
as shown in the figure:
LECTURE 07 SSP 2323 - Advanced Electronics 3
The Hybrid- Model of BJT
Since the sinusoidal signals are small, we can treat the slope at the
Q-point as a constant, which has units of conductance
The inverse of this conductance is the small signal resistance define
as r
The resistance r is called the diffusion resistance or base emitter
input resistance
LECTURE 07 SSP 2323 - Advanced Electronics 4
The Hybrid- Model of BJT
Note that r is a function of the Q-point parametes
Another parameter is called transconductance and is written as gm
This conductance relates a current in the collector to a voltage in
the BE circuit
LECTURE 07 SSP 2323 - Advanced Electronics 5
The Hybrid- Model of BJT
By considering the Early effect, there is a small signal transistor
output resistance, ro that lies between collector and emitter
LECTURE 07 SSP 2323 - Advanced Electronics 6
The Hybrid- Model of BJT
We can develop a slightly different form for the output of the
equivalent circuit
We can relate the small-signal collector current to the small-signal
base current
LECTURE 07 SSP 2323 - Advanced Electronics 7
The Hybrid- Model of BJT
Stray Elements in a BJT at High Frequencies
At high frequencies, there exists some transistor characteristics that
have to be considered:
(a) Bulk Resistance
The recombination of charge carriers occurs at point B’, which lies
between JE and JC
The base current flows from the base terminal, B, to point B’
through the base region and forming a voltage drop between B’ and
B
Hence, it can be figured out that there exists a resistance known as
the bulk resistance (denoted as rx or rb) of the base
At the emitter and collector there exist bulk resistance re’e and rc’c
too, but these resistance are too small and can be neglected
LECTURE 07 SSP 2323 - Advanced Electronics 8
The Hybrid- Model of BJT
(b) Diffusion Capacitance The effect of forward bias at the emitter-base junction
(JE) is to inject charge carriers from a region to another
The number of charge carriers injected into the base are
changing due to the applied alternating signal
The level of injection cannot change immediately
following the change in the signal, especially for high
frequency signal
In effect, a charge storage is formed between base and
emitter – the effect of capacitance, known as diffision
capacitance (Cbe)
LECTURE 07 SSP 2323 - Advanced Electronics 9
The Hybrid- Model of BJT
(c) DepletionCapacitance On both sides of the base-emitter junction (JE) and the
collector-base junction (JC), a depletion layer is formed
When the voltage change slightly, due to the small-
signal alternating voltage at the input of the transistor,
the charge stored in the depletion layer also change
Hence, the effect of capacitance, known as the depletion
capacitance formed at the junctions
At JE, the capacitance is denoted as Cje and when it is
combined with Cbe, it is denoted as C.
At JC, the depletion capacitance is denoted as Cjc or C.
LECTURE 07 SSP 2323 - Advanced Electronics 10
The Hybrid- Model of BJT
(d) Reverse-Biased Collector-Base Junction Resistance
There exists a base-collector junction resistance, known
as the reverse-biased collector-base junction resistance,
denoted as r.
The resistance provide some feedback between the
output and the input, meaning that the base current is a
slight function of the collector-emitter voltage
LECTURE 07 SSP 2323 - Advanced Electronics 11
The Hybrid- Model of BJT
The Hybrid- Model
In this model, proposed by L.J. Giacoletto, the circuit
elements are arranged in a -configuration known as the
hybrid- model The hybrid- BJT model includes elements that are
negligible at low frequencies and midband, but cannot
be ignored at higher frequencies of operation
In hybrid- model, some h-parameters changes in name,
i.e.
LECTURE 07 SSP 2323 - Advanced Electronics 12
The Hybrid- Model of BJT
In hybrid- model, some h-parameters changes in name,
i.e.
– hie is changed to rbe or r
– 1/hoe is changed to rce or ro
– ib is written as ib = vbe/rbe = vbe/r
– vbe is denoted as v
– Hence, hfeib = hfe(vbe/rbe) = gmvbe
LECTURE 07 SSP 2323 - Advanced Electronics 13
The Hybrid- Model of BJT
The hybrid- BJT model at high frequencies is as shown
below:
LECTURE 07 SSP 2323 - Advanced Electronics 14
The Hybrid- Model of BJT
Hybrid- Parameters
1. rx = ohmic resistance of base region, a few tens of ohms
2. r = dynamic resistance of base region
3. ro = collector resistance of BJT
4. C = diffusion capacitance of the base-emitter junction, 100 pF to 1000 pF.
5. gm = BJT transconductance (gm = /r = ICQ/VT)
Note:
r, C represent the characteristics of the reverse-biased collector-base junction (r several Megohms, while C 1 pF to 10 pF)
LECTURE 08 SSP 2323 - Advanced Electronics 1
The Hybrid- Model of BJT
Analysis of a CE Amplifier Configuration Using
Hybrid- Model in Low- and Mid-Frequency Range
In the low- and mid-frequency range, the reactance of
the capacitances are very large and can be considered
open circuit
The hybrid- model using the transconductance and
current gain parameters is shown below:
LECTURE 08 SSP 2323 - Advanced Electronics 2
The Hybrid- Model of BJT
The hybrid- model of (a) NPN and (b) PNP transistor
LECTURE 08 SSP 2323 - Advanced Electronics 3
The Hybrid- Model of BJT
Basic Common Emitter Amplifier
(a) Common emitter circuit with a voltage-divider biasing
(b) The small-signal equivalent circuit
LECTURE 08 SSP 2323 - Advanced Electronics 4
The Hybrid- Model of BJT
Input Resistance, Ri :
rRRRi //// 21
Output Resistance, Ro :
coo RrR //
Voltage Gain (Taking source into consideration), Avs :
s
o
s
ovs
V
V
V
V
V
VA
LECTURE 08 SSP 2323 - Advanced Electronics 5
The Hybrid- Model of BJT
where
)//( como RrVgV
and
ssi
i VRR
RV
therefore
si
icomvs
RR
RRrVgA ))//((
LECTURE 08 SSP 2323 - Advanced Electronics 6
The Hybrid- Model of BJT
Current Gain (Taking source into consideration), Ais :
where
and
i
o
i
ois
I
V
V
I
I
IA
VgR
RrI m
c
coo
//
ii RIV
therefore
ic
comis R
R
RrgA
)//(
LECTURE 08 SSP 2323 - Advanced Electronics 7
The Hybrid- Model of BJT
Circuit with Emitter Resistor
(a) CE with emitter resistor (b) The small-signal equivalent circuit
LECTURE 08 SSP 2323 - Advanced Electronics 8
The Hybrid- Model of BJT
Input Resistance, Ri :
where
Output Resistance, Ro :
bi RRRR //// 21
Eb
bb Rr
I
VR )1(
co RR
LECTURE 08 SSP 2323 - Advanced Electronics 9
The Hybrid- Model of BJT
Voltage Gain (Taking source into consideration), Avs :
where
Therefore
s
b
b
b
b
o
s
ovs
V
V
V
I
I
V
V
VA
s
si
ib
b
bbcbo V
RR
RV
R
VIRIV
and , ),
si
i
Ecvs
RR
R
RrRA
)1(
1)(
LECTURE 08 SSP 2323 - Advanced Electronics 10
The Hybrid- Model of BJT
If Ri >> Rs and if (1 + )RE >> r then the small-signal gain
is approximately
E
c
E
cvs
R
R
R
RA
)1(
Current Gain (Taking source into consideration), Ais :
i
b
b
o
i
ois
I
I
I
I
I
IA
LECTURE 08 SSP 2323 - Advanced Electronics 11
The Hybrid- Model of BJT
where
E
ii
b
iibbo
Rr
IR
R
IRIII
)1( and
Therefore
E
iis
Rr
RA
)1(
If (1 + )RE >> r then the small-signal current gain is
approximately
E
i
E
iis
R
R
R
RA
)1(
LECTURE 08 SSP 2323 - Advanced Electronics 12
The Hybrid- Model of BJT
Effect of C and C
Recall the hybrid- model of BJT :
LECTURE 08 SSP 2323 - Advanced Electronics 13
The Hybrid- Model of BJT
Notice the small values of C and C, especially when
compared to typical values of Cin, Cout, and CE.
At low and midband frequencies, C and C appear as
open circuits
At high frequencies, where C and C have an effect,
Cin, Cout, and CE appear as short circuits
LECTURE 09 SSP 2323 - Advanced Electronics 1
The Hybrid- Model of BJT
Introduction
At high frequencies, where C and C have an effect, Cin,
Cout, and CE appear as short circuits
LECTURE 09 SSP 2323 - Advanced Electronics 2
The Hybrid- Model of BJT
To focus our attention, we will assume rx 0 and r ,
and we will use Miller Effect to replace C:
Simplified hybrid- BJT model using the Miller Effect
LECTURE 09 SSP 2323 - Advanced Electronics 3
The Hybrid- Model of BJT
Using Miller Effect equation,
CAACC vv )1(1
CA
CCv
112
Individually, all capacitors in the figure has a single-pole
low-pass effect
As frequency increases they become short circuits, and
vo approaches zero
LECTURE 09 SSP 2323 - Advanced Electronics 4
The Hybrid- Model of BJT
Thus there are two low-pass poles with the
mathematical form:
Thevenineqb
RCf
2
1
Because (C1 + C) >> C2, the pole due to (C1 + C) will
dominate
The pole due to C2 is usually negligible, especially when
R’L is included in the circuit
LECTURE 09 SSP 2323 - Advanced Electronics 5
The Hybrid- Model of BJT
Typical amplifier response in the mid-band and high
frequencies regions. fh1 is normally due to (C1 + C),
and fh2 is normally due to C2
f
A
LECTURE 09 SSP 2323 - Advanced Electronics 6
The Hybrid- Model of BJT
High-Frequency Performance of CE Amplifier
We now have tools we need to analyze (actually,
estimate) the high frequency performance of an
amplifier circuit
Consider the common-emitter amplifier, as shown
Figure (a):
Using the hybrid- equivalent for the BJT, we construct
the small-signal equivalent circuit for the amplifier, as
shown in Figure (b):
LECTURE 09 SSP 2323 - Advanced Electronics 7
The Hybrid- Model of BJT
Figure (a)
LECTURE 09 SSP 2323 - Advanced Electronics 8
The Hybrid- Model of BJT
Figure (b):
LECTURE 09 SSP 2323 - Advanced Electronics 9
The Hybrid- Model of BJT
The circuit can be simplified further by using a Thevenin
equivalent on the input side, and by assuming the effect
of r to be negligible
Modified small-signal equivalent
LECTURE 09 SSP 2323 - Advanced Electronics 10
The Hybrid- Model of BJT
Note that the Thevenin resistance
])//([//' sBxs RRrrR
Recognizing that the dominant high-frequency pole
occurs on the input side, we endeavor to calculate fh1
Thus, we ignore the effect of C on the output side,
calculate the voltage gain, and apply the Miller Effect on
the input side only
Lmo
v Rgv
vA '
LECTURE 09 SSP 2323 - Advanced Electronics 11
The Hybrid- Model of BJT
Final (approximate) equivalent after applying the Miller
Effect
LECTURE 09 SSP 2323 - Advanced Electronics 12
The Hybrid- Model of BJT
So we have
totalsh
CRf
'2
11
where
Lmtotal RgCCC '1
and
)//(//' sBxs RRrrR
LECTURE 09 SSP 2323 - Advanced Electronics 13
The Hybrid- Model of BJT
Text
LECTURE 09 SSP 2323 - Advanced Electronics 14
The Hybrid- Model of BJT
Text
LECTURE 06 SSP 2323 - Advanced Electronics 1
ANALYSIS USING h-PARAMETER
Miller’s Theorem and Its Dual Certain configurations can be analyzed more simply by using
Miller’s theorem
Consider an arbitrary circuit configuration, as shown below, with N distinct nodes 1, 2, …, N
Let the node voltages be V1, V2, …, VN and the node voltage VN = 0 since N is the ground node
LECTURE 06 SSP 2323 - Advanced Electronics 2
ANALYSIS USING h-PARAMETER
By definition,
The two circuits are the same if the voltage ratio AV can be found
by some independent means
KV
VAv
1
2
LECTURE 06 SSP 2323 - Advanced Electronics 3
ANALYSIS USING h-PARAMETER
Proof :
where
This can be written as
where
Also, it can be shown that
'
)1(
'121
1Z
AV
Z
VVI v
1
2
V
VAv
1
111
)1/(' Z
V
AZ
VI
v
vA
ZZ
1
'1
1
'
1
'
/11
'
/11
'2
v
v
v A
AZ
K
KZ
A
Z
K
ZZ
LECTURE 06 SSP 2323 - Advanced Electronics 4
ANALYSIS USING h-PARAMETER
Example on Miller’s Theorem
LECTURE 06 SSP 2323 - Advanced Electronics 5
ANALYSIS USING h-PARAMETER
Dual of Miller’s Theorem
Consider the network, as shown below, with arbitrary active and
passive linear elements between nodes 1, 2, and 3
LECTURE 06 SSP 2323 - Advanced Electronics 6
ANALYSIS USING h-PARAMETER
By definition,
The two circuits are the same if excited by the same voltages V1’N
and V2’N
1
2
I
IAI
LECTURE 06 SSP 2323 - Advanced Electronics 7
ANALYSIS USING h-PARAMETER
Proof :
Therefore
1113
113
1
2113
2113'1
')1(
'1
')(
ZIV
ZAIV
ZI
IIV
ZIIVV
I
N
')1(1 ZAZ I
LECTURE 06 SSP 2323 - Advanced Electronics 8
ANALYSIS USING h-PARAMETER
Also, it can be shown that
Therefore,
2223'2 ZIVV N
2223
223
2
1223
2123'2
'1
1
'1
')(
ZIV
ZA
IV
ZI
IIV
ZIIVV
I
N
I
I
A
AZZ
)1('2
LECTURE 06 SSP 2323 - Advanced Electronics 9
ANALYSIS USING h-PARAMETER
Example on Dual of Miller’s Theorem
SSCP 3323 – Advanced Electronics
MULTISTAGE AMPLIFIER Introduction
• To obtain the gain an electronic system needs, it is often necessary to connect amplifiers in series
• When amplifiers are connected in series, they are said
to be cascaded
• In the previous analysis, the circuit consists of only one transistor
• But the circuit analysis has involved the use of
multistage concept, e.g. in the calculation of voltage gain
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛==
s
o
s
ovs v
vvv
vvA 1
1
• A multistage amplifier is an amplifier with more than
one stage of a transistor amplifier which is formed by combining several stages of such amplifier
• The objective of constructing a multistage amplifier is to
increase the overall gain or just for the purpose of impedance matching
vi1 vo1 vi2 vo2 vi3 vo3 vi4 vo4 vin von Amp #1 Amp #2 Amp #3 Amp #4 Amp #n
Figure 7.1 –An n-stage amplifier
SSCP 3323 – Advanced Electronics
• The overall gain of the amplifier can be written as
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛==
in
on
i
o
i
o
i
o
i
o
i
onv v
vvv
vv
vv
vv
vvA .....
4
4
3
3
2
2
1
1
1
where , 21 io vv = 32 io vv = , …, inno vv =− )1(
• Therefore,
vnvvvv AAAAA ××××= ...321
• Current gain can also be written in the same form:
iniiii AAAAA ××××= ...321
• There are several ways to connect the amplifiers: o RC-coupled amplifiers o Direct-coupled amplifiers o LC-coupled amplifiers o Transformer-coupled amplifiers
SSCP 3323 – Advanced Electronics
RC-Coupled Amplifiers
• Figure 7.2 shows a three-stage cascaded amplifier
Figure 7.2 – RC-coupled amplifier
• The first two stages are common-emitter amplifiers and the third is a common collector amplifier
• The technique used for coupling the stages together in
the circuit is called RC coupling
• The term “RC” comes from the fact that capacitors are used between stages and form an RC circuit with the impedance of the next stage
• The coupling capacitors act like an open for dc currents
but are a short for signal currents
SSCP 3323 – Advanced Electronics
• Because of this, each stage’s bias circuitry is independent and the dc bias current and voltages can be calculated in the same manner as that used for a single-stage amplifier
DC analysis First stage:
V6 k 22 k 37
k 22 V 16 21
2 =Ω+Ω
Ω×=
+×=
bb
bccb RR
RVV
V5.3 V 0.7 - V 6 ==−= bebe VVV
mA 2.8 k 1.9 V3.5 =Ω
==e
ee R
VI
V 5mA 2.8 k 1.8 =×Ω=×= ccRc RIV
V 11 V5 - V 61 ==−= Rcccc VVV
Second stage:
V2.9 k 2.7 k 12
k 2.7 V 16 21
2 =Ω+Ω
Ω×=
+×=
bb
bccb RR
RVV
V2.2 V 0.7 - V 2.9 ==−= bebe VVV
mA 8.4 262 V.22 =Ω
==e
ee R
VI
SSCP 3323 – Advanced Electronics
V 9.6mA 8.4 820 =×Ω=×= ccRc RIV
V 1.9 V6.9 - V 61 ==−= Rcccc VVV Third stage:
V8.8 k 2.2 k 1.8
k 2.2 V 16 21
2 =Ω+Ω
Ω×=
+×=
bb
bccb RR
RVV
V8.1 V 0.7 - V 8.8 ==−= bebe VVV
mA 45 180 V.18 =Ω
==e
ee R
VI
V 61 == ccc VV
• The output signal from each stage will see the input
impedance of the next stage as its load
• Figure 7.3 is an equivalent circuit of each stage of the circuit and how each stage interacts with the next
Figure 7.3 - Equivalent circuit of an RC-coupled amplifier
SSCP 3323 – Advanced Electronics
• The signal generator’s internal impedances is in series with the input impedance of the first stage (Q1)
• The voltage out (unloaded) of the first stage drives the
second stage’s (Q2) input impedance through the output impedance of the first stage (Q1)
• The voltage out (unloaded) of the second stage (Q2)
drives the input impedances of the third stage (Q3) through the output impedance of the second stage (Q2)
• The voltage out (unloaded) of the third stage drives the
load through the output impedance of the third stage
• As far as the signal generator is concerned, the input impedance of the circuit is equal to the input impedance of the first stage
• The output inpedance of the total circuit is equal to the
output impedance of the final stage of the system
• The gain (voltage, current, and power) of the total circuit is equal to the product of the individual stages
• In RC-coupled amplifier circuits, the capacitors block dc
bias current between stages, so each transistor’s bias circuitry is independent
• Hence, RC-coupling method is suitable for amplifying
ac signal only
• The capacitor acts like a short for the signal current and the effect each stage has on an adjacent stage must be considered
SSCP 3323 – Advanced Electronics
• By considering the interaction between stages the signal parameters of each stage can be calculated
• RC-coupled amplifiers are popular because each stage
has its own independent bias circuit
• Fluctuations in the dc operating point in one stage are not amplified by the next stage
Transfer Function at the Interconnecting Stage
• The exists an RC combination in between stages of an RC-coupled amplifiers, as shown in Figure 7.4
Figure 7.4 – RC coupling beween stages of amplifiers
• For dc, the output voltage is
RCtco evv /−=
• For ac, the input-output relationship is
ωω
ωωβj
CRjCjR
Rvv
i
o
−=
+=
+=
1
111
11
where RC1
=βω
SSCP 3323 – Advanced Electronics
Example 7.1 Figure 7.5 shows a two-stage BJT cascaded amplifier. For each transistor, hie = 1 kΩ and hfe = 100; hre, hoe, and the biasing network may be neglected. At mid frequencies, (a) draw the small-signal model, (b) find the overall voltage gain.
Figure 7.5
Solution (a) The small-signal model is shown in Figure 7.6. Because at mid frequencies the coupling and bypass capacitors act as short circuits, they are shown as direct connections in the figure.
Figure 7.6
SSCP 3323 – Advanced Electronics
(b) Output voltage vo is 22 100- )k 1(100 bbo iiv =Ω−= Because of the current division,
11
2 50k 1)(1
)k 1(100b
bb iii −=
Ω+Ω
−=
Also,
2k 1)(11ss
bvvi =
Ω+=
Hence,
ss
o vvv 25002
50100 =⎟⎠⎞
⎜⎝⎛ −−=
2500==s
ov v
vA
SSCP 3323 – Advanced Electronics
Direct-Coupled Amplifiers
• Often it is necessary to have an amplifier that is capable of amplifying dc current and voltages
• To couple a dc signal from one stage to the next, it is
necessary to remove the coupling capacitor and connect the output of one stage directly to the input of the next, as shown in Figure 7.7
Figure 7.7 – Direct-coupled amplifiers
• Voltage gain at the interconnecting stage is 1==i
ov v
vA
• In the ac equivalent circuit of a multistage amplifier, the
emitter bypass capacitors are removed so that the voltage gain of the dc signal will be the same as the gain of the dynamic signals
• Figure 7.8 shows an example of a three-stage direct-
coupled amplifiers
SSCP 3323 – Advanced Electronics
Figure 7.8 – Direct-coupled amplifier
DC Analysis First stage:
V2.3 k 15 k 90
k 15 V 16 21
2 =Ω+Ω
Ω×=
+×=
bb
bccb RR
RVV
V1.6 V 0.7 - V 2.3 ==−= bebe VVV
mA 1.07 k 1.5 V.61 =Ω
==e
ee R
VI
V 5mA 2.8 k 1.8 =×Ω=×= ccRc RIV
V 3.5 V10.7 - V 61 ==−= Rcccc VVV
SSCP 3323 – Advanced Electronics
Second stage:
V5.3 stage first == cb VV
V4.6 V 0.7 - V 5.3 ==−= bebe VVV
mA 0.92 k 5 V6.4 =Ω
==e
ee R
VI
V 9.2 k 10 mA 0.92 =Ω×=×= ccRc RIV
V 8.6 V9.2 - V 61 ==−= Rcccc VVV
Third stage:
V6.8 stage second == cb VV
V6.1 V 0.7 - V 6.8 ==−= bebe VVV
V61 == ccc VV
• The first two stages are in the common-emitter
configuration and the last stage is a common collector
• The bias for the first stage is accomplished by the standard voltage divider of Rb1 and Rb2
• The last two stages also use voltage-divider biasing,
but the voltage divider is made up of the output circuitry of the previous stage
SSCP 3323 – Advanced Electronics
• The voltage on the base of Q2 is the same as the
voltage on the collector of Q1
• If we assume that the base current of Q2 is small enough not to upset the output circuit of Q1, the voltage on the collector of Q1 is a function of the voltage drop across Rc and the voltage drop from the collector of the transistor to ground
• If the collector current of Q1 is much larger than the
base current of Q2, the voltage on the collector of Q1 can be calculated in the same manner as used in single-stage voltage-divider biased circuits
• Once the collector voltage of Q1 is known, the base
voltage of Q2 is also known because they are directly coupled, and at the same potential
• With the base voltage of Q2 known, the collector
voltage of Q2 can be found in the same manner used in a single-stage amplifier
• This method can be continued for the following stages
SSCP 3323 – Advanced Electronics
Example 7.2 For the two-stage CE-CC configuration in Figure 7.9 the hybrid parameters of each stage are hie = 2 kΩ and hfe = 100. Find the input and output resistances and individual, as well as overall, voltage and current gains.
Figure 7.9
Solution
• Note that, in a cascade of stages, the collector resistance of one stage is shunted by the input resistance of the next stage
• Hence it is advantageous to start the analysis with the last stage.
• In addition, it is convenient to compute, first, the current gain, then the input resistance and the voltage gain.
• Finally, the output resistance may be calculated if desired by starting this analysis with the first stage and proceeding toward the output stage.
SSCP 3323 – Advanced Electronics
• For the CC output stage, we have, using standard formulas,
10112 =+= feI hA
507)5)(101(2)1(2 =+=++= Lfeii RhhR
996.0507
2112
2 =−=−=i
ieV R
hA
• Note the high input resistance of the CC stage and that
its voltage gain is close to unity
1001
11 −=−=
−= fe
b
cI h
iiA
Ω=+=++= k 1.12)1.0)(101(2)1( 11 efeieI RhhR
• The effective load on the first stage, its voltage gain, and the output resistance are
Ω==+
= k 95.4512
)507)(5(21
211
iC
iCL RR
RRR
9.401.12
)95.4)(100(1
111 −=
−==
i
Liv R
RAA
Ω== k 5' 11 Co RR
• Since R’o1 is is the effective source resistance for Q2, then,
SSCP 3323 – Advanced Electronics
Ω=+
=++
= 3.69101
500020001
' 12
fe
oieo h
RhR
oLo
Loo R
RRRRR ' 4.68
5069)5000)(3.69('
22
222 =Ω==
+=
• The voltage and current gains of the cascade are,
75.40)996.0)(9.40(21 −=−==≡ vvi
oV AA
vvA
6.98
50755)101)(100(
21
121
1
2
−=⎟⎠⎞
⎜⎝⎛
+−=
+=
−≡
iC
Cii
b
eI RR
RAAiiA
• Alternatively, Av may be computed from
74.401.12
)5)(6.98(1
2 −=−
==i
Liv R
RAA
• The biasing resistors R1 and R2 have had no effect
upon the above calculations
• They do influence the calculation of the overall voltage gain
97.35539.8539.7)74.40(
''
1
1 −=⎟⎠⎞
⎜⎝⎛−=
+=≡
sii
vs
ovs RR
RAvvA
where from Figure 7.10 we see that
SSCP 3323 – Advanced Electronics
Ω==== k 539.71.32
)1.12)(20(1.12//)40//40(//' 11 ii RRR
Figure 7.10
• Note that whereas the input resistance of the cascaded amplifier is the input resistance of the first stage Ri1, the resistance seen by the signal source (vs in series with Rs) is R’i1
SSP 2323 – Advanced Electronics LECTURE 9
LC-Coupled Amplifier
• It is desirable to design circuit without inductors or transformers, if possible, in amplifier circuits because these components are large, heavy, and expensive
• However, there are applications where these
components must be used and the designer should know how they function in amplifier circuits
• Figure 9.1 shows an LC-coupled amplifier
Figure 9.1 – LC-coupled amplifier
75
SSP 2323 – Advanced Electronics LECTURE 9
• In the circuit, resistor Rc has been replaced with an
inductor Lc
• The circuit can be evaluated in the same manner as in a circuit with a resistor in the collector leg
• First, the base voltage is found by using the voltage
divider formula
• Then the emitter voltage is found by substracting Vbe from the base voltage
• With the emitter voltage known, the emitter current can
be found by dividing the emitter voltage by the dc resistance in the emitter leg
• The collector current is assumed to be the same as the
emitter current, so the collector current times the dc resistance of Lc will give the dc voltage drop across Lc
• To find the voltage on the collector we substract this
voltage from Vcc
• The dc resistance of Lc is usually small, however, and the drop across Lc very small. For this reason the voltage on the collector is approximately equal to Vcc
• Because the dc collector voltage is always equal to Vcc,
the collector current cannot be determined by measuring the collector voltage
76
SSP 2323 – Advanced Electronics LECTURE 9
• However, by measuring the emitter voltage and knowing the value of Re, the current flowing through the transistor can be calculated
• Signal parameters are calculated in the same way as
for the circuit with a resistor in the collector leg
• When calculating voltage gain, however, RL(ac) is equal to the XL of the collector inductor in parallel with the load
• Recall that XL = 2πfL and is dependent on frequency,
which in turn makes the voltage gain of the circuit dependent on frequency
• Because gain is a function of frequency, this circuit is
not usable in circuits such as audio amplifiers where the input varies over a range of frequencies
• Another important difference of the LC amplifier
compared to the RC amplifier is the output voltage swing
• The maximum output voltage swing an RC amplifier
can have is equal to the value of Vcc
• In the LC amplifier, however, the collector is sitting at the value of Vcc with no signal inserted
• If an input signal causes the collector current to
increase the inductor will develop a voltage across it opposing the increase in current
77
SSP 2323 – Advanced Electronics LECTURE 9
• This voltage is in series opposing with Vcc; therefore, the voltage on the collector goes down
• If the collector current increases enough, the voltage
drop developed across Lc will equal to Vcc and the voltage on the collector will drop to zero
• Now, if the input signal suddenly caused the collector
current to increase, the collector inductor would again develop a voltage across it to oppose the change in current
• However, this time it is opposing a decreasing current
rather than an increasing current, so the voltage developed is reversed
• This voltage is in series aiding with Vcc and the voltage
on the collector rises above the value of Vcc
• If the collector current decreases enough, the voltage developed across the collector inductor will equal the value of Vcc
• Because this voltage is in series aiding with Vcc, the
voltage on the collector will rise to twice the value of Vcc
• Three important things to note about LC amplifiers are: o The dc voltage on the collector is equal to
approximately Vcc o The voltage gain is dependent on frequency, and o The maximum output voltage swing can be
approximately twice the value of Vcc
78
SSP 2323 – Advanced Electronics LECTURE 9
Transformer-Coupled Amplifier
Figure 9.2 – (a) Transformer-coupled amplifier (b) Dot convention on transformer windings
• The sign convention for a transformer is that if i1 and i2
both enter the dot, then the equation of current becomes i1 +i2 = 0
• However, if one of the current (i1 or i2) enter the dot and
the other one leaves the dot, then 021 =− ii or 01 2 =− ii
• For a transformer with the number of turns n1 in the
primary and n2 in the secondary,
02211 =+ inin or 02211 =− inin or 01122 =− inin
• The second equation is the relationship between the primary and secondary voltages and their number of turns, i.e.
1
2
1
2nn
vv
= or 2
2
1
1nv
nv
=
• By using the above equations we can obtain the
relationship between input impedance Zi and ZL
79
SSP 2323 – Advanced Electronics LECTURE 9
• Define 1
1ivZi = , but 2
1
21 v
nnv ⎟⎟
⎠
⎞⎜⎜⎝
⎛=
• Hence ⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛=
1
2
2
1iv
nnZi and ZL22 iv −=
• Thus Li Zii
nnZ ⎟⎟
⎠
⎞⎜⎜⎝
⎛ −⎟⎟⎠
⎞⎜⎜⎝
⎛=
1
2
2
1
• But 2
1
1
2nn
ii
−=
• Therefore Li ZnnZ
2
2
1⎟⎟⎠
⎞⎜⎜⎝
⎛=
• ZL is the load which is connected at the output of the
transformer; if there is nothing connected at the output, ZL = ∞
• An example of transformer-coupled amplifier is shown
in Figure 9.3.
• Assume that the h-parameter of the transistor are
0 50 k 2 ===Ω= oerefeie hhhh
80
SSP 2323 – Advanced Electronics LECTURE 9
Figure 9.3 An example of transformer-coupled amplifier
• For small-signal analysis, all capacitors and voltage sources are shorted
Figure 9.4 – Circuit in Figure 9.3 when all capacitors and voltage sources are shorted
• Then, all transistors are replaced by their h-parameter equivalent circuit
• To calculate voltage gain Av = vo/vi, split this formula
into several intermediate stages
81
SSP 2323 – Advanced Electronics LECTURE 9
i
o
i
ov v
vvv
vv
vv
vv
vvA 1
1
2
2
3
3
4
4××××=≡
• Although the amplifier consists of two cascaded
transistors, the calculation of Av involves five stages
51
4=
vvo
• V4/V3 is the voltage gain of transistor Q2
Lrefeoeieie
LfeZhhhhh
Zhvv
)(3
4−+
−=
• Here, ZL is the load seen by transistor Q2, i.e. Z4, the
output impedance of transistor Q2
• Since 0= then = oere hhie
feh
Zhvv 4
3
4 −=
• Z4 can be calculated using the formula for input
impedance of a transformer, that is
Li ZnnZ
2
2
1⎟⎟⎠
⎞⎜⎜⎝
⎛=
• Hence,
20008015 2
4 =×⎟⎠⎞
⎜⎝⎛=Z
82
SSP 2323 – Advanced Electronics LECTURE 9
• Thus,
50k 2
)2000)(50(3
4 −=−=vv
51
2
3 =vv
dan ie
feh
Zhvv 2
1
2 −=
• Calculate Z2 from
3
2
2 15 ZZ ⎟⎠⎞
⎜⎝⎛=
• Calculate Z3 from
Ω==+
−== k 213 ie
Loe
Lfereiei h
ZhZhhhZZ
• Therefore,
125015 2
1
2 −=⎟⎠⎞
⎜⎝⎛−= ie
ie
fe hhh
vv
• But 141 =
ivv
• Thus,
3
1
1
2
2
3
3
4
4
1010
14)1250(
51)50(
51
×=
⎟⎠⎞
⎜⎝⎛−⎟
⎠⎞
⎜⎝⎛−⎟
⎠⎞
⎜⎝⎛=××××=≡
i
o
i
ov v
vvv
vv
vv
vv
vvA
83
SSCP 2323 – Advanced Electronics
84
POWER AMPLIFIER Introduction
The amplifier circuits we have studied so far deal with small signal
These form the early stages of signal processing systems which are designed to give good voltage gain, hence the name voltage amplifiers
Consider the block diagram of a simple audio amplifier, shown in figure 10.1
Figure 10.1 – Audio amplifier stages
The microphone produces a very small signal, in the millivolt range
The first two stages amplify this audio signal and it becomes larger in voltage level but can provide only low current (low power)
The last stage produces a much larger signal which also has to provide sufficient power to the drive the loud speakers coil
SSCP 2323 – Advanced Electronics
85
Thus the power content of the output stage of this amplifier must be much larger than the small power of the input
The output stage of the power amplifier must be designed to meet the power requirement
In this course, we are interested only in power amplifiers using BJTs, and will not consider other types of power electronics that, for example, use thyristors
Two important functions of the output stage are to provide a low output resistance so that it can deliver the signal power to the load without loss of gain and to maintain linearity in the output signal
A low output resistance implies the use of emitter-follower (for BJT) or source-follower (for MOSFET) circuit configurations
A power amplifier has to handle large voltage and current swings, and so it must have large power gain and high efficiency in converting the power drawn from the dc supply to signal form
A measure of linearity of the output signal is the total harmonic distortion (THD)
This figure of merit is the rms value of the harmonic components of the output signal, excluding the fundamental, expressed as a percentage of the fundamental
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86
A particular concern in the design of the output stage is to deliver the required signal power to the load efficiency
This specification implies that the power dissipated in the transistors of the output stage should be as small as possible
The output transistors must be capable of delivering the required current to the load, and must be capable of sustaining the required output voltage
Classes of Power Amplifier
Power amplifiers can be divided into four classes, i.e. o Class A o Class B o Class AB o Class C
The amplifier circuits covered in previous lectures are known as class A, which are linear as these operate in a small region in the middle of the load line, as shown in Figure 10.2
SSCP 2323 – Advanced Electronics
87
Figure 10.2 – Class A operating point
This gives the best possible output swing without clipping and so the output signal is a faithful replica of the input signal
In other words the signal distortion is kept low – the greatest advantage of class A operation
Class B amplifier operation is shown in Figure 10.3 wherein the operating point is at cut-off end of the load line
SSCP 2323 – Advanced Electronics
88
Figure 10.3 – Class B operation
This is achieved by operating the base-emitter junction of the transistor with zero bias, so that only the positive halves of the input signal will be amplified, while the negative halves are cut-off
Thus in the class B, the amplifier has a conduction
angle of 180 in contrast to class A where the
conduction angle is 360 , i.e. the entire input cycle
Biasing an amplifier at cut-off end of the load line saves power as there is no drain in the supply during the non-conduction period as in this period the transistor dc current is zero
In class A, however, the operating point is in the middle of the load line so that about half the supply voltage drops across the transistor
SSCP 2323 – Advanced Electronics
89
Hence, the current flowing through the transistor is half of its voltage drops across the transistor is half of its saturation current.
These values of voltage drop and current produce a power loss in the transistor which is constant in class A
Also there is a drain on power supply even if no signal is being amplified
There are also class AB and class C amplifiers – again, it is a question of bias which controls the operating point, the conduction angle and the class of operation
Figure 10.4 shows the relative location of class AB operating point which is mid between class A and class B operating points
Figure 10.4 – Location of operating points
In a class C amplifier the operating point is chosen that output current (or voltage) is zero for more than one half of the signal cycle
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90
Class-A Operation
• In class-A operation, an output transistor is biased at a quiescent current ICQ and conducts for the entire cycle of the input signal
Figure 11.1 – Collector current versus time characteristics
for class-A amplifier
• A basic common-emitter configuration is shown in Figure 11.2, where the bias circuitry has been omitted, for convenience
Figure 11.2 – A basic CE configuration
SSP 3323 – Advanced Electronics
91
• Also, in this standard class-A amplifier configuration,
no inductors or transformers are used
• The dc load line is shown in Figure 11.3, where the Q-point is assumed to be in the center of the load line, so that VCEQ = VCC/2
Figure 11.3 - Dc load line for a basic CE amplifier
• If a sinusoidal input signal is applied, sinusoidal variations are induced in the collector current and collector-emitter voltage
• The instantaneous power dissipation in the transistor,
neglecting the base current is
CCEQ ivP =
SSP 3323 – Advanced Electronics
92
• For a sinusoidal input signal, the collector current and collector-emitter voltage can be written as
tIIi pCQC ωsin+=
and
tVVv pCC
CE ωsin2
−=
• If we consider the absolute possible variations, then
Ip=ICQ and Vp=VCC/2
• Therefore, the instantaneous power dissipation in the transistor is
( )tIVivP CQCCCCEQ ω2sin1
2−==
• Figure 11.4 is a plot of the instantaneous transistor
power dissipation
Figure 11.4 - Instantaneous power dissipation versus time in
the CE transistor amplifier
SSP 3323 – Advanced Electronics
93
• Since the maximum power dissipation corresponds to
the quiescent value, the transistor must be capable of handling a continuous power dissipation of VCCICQ/2 when the input signal is zero
• The power conversion efficiency is defined as
( )
( )SL
PP
powersupply power load signal
=η
where LP is the average ac power delivered to the load
and SP is the average power supplied by the VCC power source
• For the standard class-A amplifier and sinusoidal input
signals, the average ac power delivered to the load is pp IV2
1
• Using the absolute possible variations, we have
4)(
221(max) CQCC
CQCC
L
IVIVP =⎟
⎠⎞
⎜⎝⎛⎟⎠⎞
⎜⎝⎛=
• The average power supplied by the VCC source is
CQCCS IVP =
• The maximum attainable conversion efficiency is therefore
SSP 3323 – Advanced Electronics
94
%25(max) 41
⇒=CQCC
CQCC
IVIV
η
• Keep in mind that the maximum possible conversion
efficiency may change when a load is connected to the output of the amplifier
• This efficiency is relatively low; therefore, standard
class-A amplifiers are normally not used when signal powers greater than approximately 1 W are required
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Class-B Operation Idealized Class-B Operation
• For class-B operation, an output transistor conducts for only one-half of each sine wave input cycle, as shown by the collector current versus time characteristics in Figure 11.5
Figure 11.5 – C collector current versus time
characteristics for class-B operation
• An idealized class-B output stage that consists of a complementary pair of electronic devices is shown in Figure 11.6
Figure 11.6 – Idealized class-B output stage with
complementary pair A and B, of electronic devices
SSP 3323 – Advanced Electronics
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• When vI = 0, both devices are off, the bias currents are zero, and vO = 0
• For vI > 0, device A turns on and supplies current to the
load, as shown in Figure 11.7
Figure 11.7 – Device A turns on for vI > 0,
• For vI < 0, device B turns on and sinks current from the
load, as shown in Figure 11.8
Figure 11.8 – Device B turns on for vI < 0,
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• The voltage transfer characteristics of the circuit is shown in Figure 11.9
Figure 11.9 – Voltage transfer characteristics for an idealized class-B output stage with complementary pair A and B, of electronic devices
Approximate Class-B Circuit
• Figure 11.10 shows an output stage that consists of a complementary pair of bipolar transistors
Figure 11.10 – Basic complementary push-pull output stage
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• When vI = 0, both transistors are cut off and the output voltage is vO = 0
• If we assumed a B-E cut-in voltage of 0.6 V, then the
output voltage vO remains zero as long as the input voltage is in the range -0.6 ≤ vI ≤ +0.6 V
• If vI becomes positive and is greater than 0.6 V, then Qn
turns on and operates as an emitter follower
• The load current iL is positive and is supplied through Qn, and the B-E junction of Qp is reverse biased
• If vI becomes negative by more than 0.6 V, then Qp
turns on and operates as an emitter follower
• Transistor Qp is a sink for the load current, which means that iL is negative
• The circuit is called a complementary push-pull
output stage
• Transistor Qn conducts during the positive half of the input cycle, and Qp conducts during the negative half-cycle
• The transistors do not both conduct at the same time
• The transfer characteristics for the complementary
push-pull output stage is shown in Figure 11.11
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Figure 11.11 – Voltage transfer characteristics of basic complementary push-pull output stage
• When either transistor is conducting, the voltage gain, which is the slope of the curve, is essentially unity as a result of the emitter follower
• The output voltage for a sinusoidal input signal is
shown in Figure 11.12
• When the output voltage is positive, the npn transistor is conducting, and when the output voltage is negative, the pnp transistor is conducting
• It can be seen from the figure that each transistor
actually conducts for slightly less than half the time
• The the bipolar push-pull circuit shown in Figure 11.10 is not exactly a class-B circuit
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Figure 11.12 – Crossover distortotion of basic
complementary push-pull output stage Crossover Distortion
• From Figure 11.11, it can be seen that there is a range of input voltage around zero volts where both transistors are cut off and vO is zero
• This portion of the curve is called the dead band, and it
produces a crossover distortion, as shown in Figure 11.12 for a sinusoidal input signal
• Crossover distortion can be virtually eliminated by
biasing both Qn and Qp with a small quiescent collector current when vI is zero
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Idealized Power Efficiency
• If the complementary push-pull output stage circuit is considered as an idealized version in which the base-emitter turn-on voltages are zero, then each transistor would conduct for exactly one-half cycle of the sinusoidal input signal
• The circuit would be a class-B output stage, and the
output voltage and load current would be replicas of the input signal
• The collector-emitter voltages would also show the
same sinusoidal variation
• Figure 11.13 shows the effective load line of the ideal class-B output stage
Figure 11.13 - Effective load line of the ideal class-B output stage
SSP 3323 – Advanced Electronics
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• The Q-point is at zero collector current, or at cutoff for both transistor – thus, the quiescent power dissipation in each transistor is zero
• The output voltage for this idealized class-B output
stage can be written
tVv po ωsin= where the maximum possible value of Vp is VCC
• The instantaneous power dissipation in Qn is
CnCEnQn ivp =
• The collector current is
πωπ
πωω
2for 0
0for sin
≤≤=
≤≤=
t
ttRV
iL
pCn
where Vp is the peak output voltage
• From Figure 11.13, it can be seen that the collector-emitter voltage can be written as
tVVv pCCCEn ωsin−=
• Therefore, the total instantaneous power dissipation in
Qn is
SSP 3323 – Advanced Electronics
103
( )πωπ
πωωω
2tfor 0
t0for sinsin
≤≤=
≤≤⎟⎟⎠
⎞⎜⎜⎝
⎛−= t
RV
tVVpL
ppCCQn
• The average power dissipation is therefore
L
p
L
pCCQn R
VRVV
P4
2
−=π
• The average power dissipation in transistor Qp is
exactly the same as that for Qn because of symmetry
• A plot of the average power dissipation as a function of Vp is shown in Figure 11.14
Figure 11.14 – Average power dissipation in each transistor versus peak output voltage for class-B output stage
SSP 3323 – Advanced Electronics
104
• The power dissipation first increases with increasing output voltage, reaches a maximum, and finally decreases with increasing Vp
• The maximum average power dissipation is determined
by setting the derivative of QnP with respect to Vp equal to zero, producing
L
CCQn R
VP 2
2
(max)π
=
which occurs when πCC
PpVV
Qn
2(max)
=
• The average power delivered to the load is
L
pL R
VP
2
21⋅=
• Since the current supplied by each power supply is half
a sinewave, the average current is )/( Lp RV π
• The average power supplied by each source is therefore
⎟⎟⎠
⎞⎜⎜⎝
⎛== −+
L
pCCSS R
VVPP
π
SSP 3323 – Advanced Electronics
105
• And the total power supplied by the two sources is
⎟⎟⎠
⎞⎜⎜⎝
⎛=
L
pCCS R
VVP
π2
• The conversion efficiency is
( )( ) CC
p
L
pCC
L
p
S
L
VV
RV
V
RV
PP
⋅=
⎟⎟⎠
⎞⎜⎜⎝
⎛
⋅==
42
21
power supply power load signal
2
π
π
η
• The maximum possible efficiency, which occurs when
Vp = VCC, is
%5.784
(max) ⇒=πη
• This maximum efficiency value is substantially larger
than that of the standard class-A amplifier
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Class-AB Operation
• In class-AB operation, an output transistor is biased at a small quiescent current IQ and conducts for slightly more than half a cycle
• The collector current versus time characteristics for a
class-AB amplifier is shown in Figure 12.1
Figure 12.1 - The collector current versus time characteristics for a class-AB amplifier
• Up to this point, we have used voltage divider bias for
all our class-B amplifiers
• Problems can develop with the class-B or class-AB amplifier when voltage divider bias is used
o Crossover distortion can occur o Thermal runaway can occur o The amplifier is not stable over a wide range of
temperatures
• The class-AB amplifier with diode bias eliminates the problem of crossover distortion, thermal runaway, and poor temperature stability
• By using diodes that have characteristics similar to the
emitter-base junctions within the transistors, the
SSP 3323 – Advanced Electronics
107
amplifier will be correctly biased for class-AB operation regardless of circuit temperature
• This eliminates the problem of crossover distortion
caused by temperature changes
• A biasing circuit that can be used to eliminate the problems of crossover distortion and thermal runaway is shown in Figure 12.2
Figure 12.2 – Diode biasing
• The circuit shown, called diode bias, uses two diodes in place of the resistor(s) between the base of Q1 and the base of Q2
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• The diodes in the bias circuit are called compensating diodes and are chosen to match the characteristic values of VBE for the two transistors
• In class-B amplifiers, the transistors are biased at
cutoff, causing the value of ICQ for the amplifier to be approximately equal to zero
• When diode biased is used, the transistors are actually
biased just above cutoff, i.e. there will be some measurable amount of ICQ when diode biased is used
• The dc voltages at various point in the circuit is shown
in Figure 12.3
Figure 12.3 – DC voltages at various point in diode biased class-AB amplifier
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• In order to understand the operation of the circuit, the following assumptions are made: 1. VCEQ is approximately one-half of the value of VCC 2. The current through R2 causes 5.3 V to be developed
across the resistor R2
• If the above conditions are met, the base of Q2 will be at 5.3 V and VE of Q2 will be 6 V
• Since VB for this pnp transistor is 0.7 V more negative
than VE, Q2 will conduct
• With 1.4 V being developed across the biasing diodes, VB of Q1 will be 5.3 V + 1.4 V = 6.7 V
• Since VB for this npn transistor is 0.7 V more positive
than VE, Q1 will also conduct
• Thus both transistors in the diode biased amplifier will conduct, and some measurable amount of ICQ will be present, as shown in Figure 12.4
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Figure 12.4 – DC currents in diode biased class-AB amplifier
Class-AB Operation
• To simplify the discussion, an assumption is made: a transistor will conduct until its base and emitter voltages are equal, at which time it will turn off
• The circuit response to the waveform is shown in Figure
12.5
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Figure 12.5 - Circuit response to the waveform
• Q1 will conduct as long as its base voltage is more positive than 0.7 V
• The value of VB drops to 6 V at t1 and t3 since the -0.7 V
value of Vin subtracts from the 6.7 V value of VB(Q1)
• Thus, it can be assumed that Q1 conducts for the entire time between t1 and t3
• The same principle applies to Q2: At t2 and t4, Q2 will
turn off, since the +0.7 V value of Vin adds to the value of VB(Q2), causing VB and VE to be equal
• Thus, Q2 conducts for the entire time between t2 and t4
• The transistors in the diode bias circuit will conduct for
slightly more than 180°, i.e. for a portion of the input cycle that is greater than 180° and less than 360°
• Both transistors will be conducting at the same time for
a small portion of the wave
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• Since both transistors in class-AB amplifier are conducting when the input signal is at zero volts, the amplifier does not have the crossover distortion problems that the class-B amplifier may have
• Crossover distortion only occurs when both transistors
are in cutoff, so the problem will not normally occur in class-AB amplifiers
Class-AB Amplifier Analysis
• Consider a class-AB amplifier, shown in Figure 12.6
Figure 12.6 – Class-AB amplifier and its load lines
• For this circuit, IC(sat) is found as
mA 750)8(2
122(sat) ===
L
CCC R
VI
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• VCE(off) is found as
V 62
122(off) === CC
CEVV
• Using these two values, the dc and ac load lines are
plotted, as shown in Figure 12.7
Figure 12.7 – Class-AB amplifier load lines
• Next, the value of I1 is determined as
mA 4.10 1020
V 1.4 - V 124.1
211 =
Ω=
+−
=RR
VI CC
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• The average current in the collector circuit of the amplifier is found as
mA 5.238 8
V) (0.159)(12159.0(ave) 1 =
Ω==
L
CCC R
VI
• Using this value and the value of I1 calculated earlier,
the value of ICC is found as
mA 248.9 mA 10.4 mA 5.2381(ave) 1 =+=+= III CCC
• The total power being drawn from the supply is
W2.99 mA) (248.9 V) 12( === CCCCS IVP
• The load power is
W2.25 )8(8
V) 12(8
22
=Ω
==L
CCL R
VP
• The efficiency of the amplifier is
%25.75%100 =×=S
L
PPη
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Inductively Coupled Class-A Amplifier
• Delivering a large power to a load generally requires both a large voltage and a high current
• In a common-emitter circuit, this requirement can be
met by replacing the collector resistor with an inductor, as shown in Figure 12.8
• The inductor is a short circuit to a dc current, but acts
as an open circuit to an ac signal operating at a sufficiently high frequency
• The entire ac current is therefore coupled to the load
Rajah 12.8 – Inductively coupled class-A amplifier
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• The dc and ac load lines are shown in Figure 12.9
Figure 12.9 – DC and AC load lines for inductively coupled class-A amplifier
• The resistance of the inductor is assumed to be negligible, and the emitter resistor value is small
• The quiescent collector-emitter voltage is then
approximately VCEQ ≈ VCC
• The ac collector current is
L
cec R
vi −=
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• To obtain the maximum symmetrical output-signal swing, which will in turn produce the maximum power, we want
L
CCCQ R
VI ≅
• For this condition, the ac load line intersects the vCE
axis at 2VCC
• The use of an inductor or storage device results in an output ac voltage swing that is larger than VCC
• The polarity of the induced voltage across the inductor
may be such that the voltage adds to VCC, producing an output voltage that is larger than VCC
• The absolute maximum amplitude of the signal current
in the load is ICQ; therefore, the maximum possible average signal power delivered to the load is
21
21(max)
22
L
CCLCQL R
VRIP ⋅==
• If the power dissipation in the bias resistors R1 and R2
is neglected, the average power supplied by the VCC source is
2
L
CCCQCCS R
VIVP ==
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• The maximum possible power conversion efficiency is then
50% 21(max)(max) 2
2
21
⇒=⋅
==L
CC
L
CC
RV
RV
S
L
PPη
• This demonstrates that, in a standard class-A amplifier,
replacing the collector resistance with an inductor doubles the maximum possible power conversion efficiency
Transformer-Coupled CE Amplifier
• The design of an inductively coupled amplifier to achieve high power conversion efficiency may be difficult, depending on the relationship between the supply voltage VCC and the load resistance RL
• The effective load resistance can be optimized by using
a transformer with proper turns ratio
• A CE amplifier with a transformer-coupled load in the collector circuit is shown in Figure 12.10
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Figure 12.10 – Transformer-coupled CE amplifier
• The dc and ac load lines are shown in Figure 12.11
Figure 12.11 – Dc and ac load lines of a transformer-coupled CE amplifier
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• If any resistance in the transformer is neglected and RE
is assumed small, the quiescent collector-emitter voltage is
CCCEQ VV ≅
• Assuming an ideal transformer, the currents and
voltages in Figure 12.9 are related
CL iai = and 12 a
vv =
where a is the ratio of primary to secondary turns, or simply the turns ratio
• Dividing voltages by currents, gives
2112 1/v
aiv
iaa
iv
CCL
⋅==
• The load resistance is RL ≡ v2/iL, and we can define a
transformed load resistance as
' 2221L
LCL Ra
iva
ivR =⋅==
• The turns ratio is designed to produce the maximum
symmetrical swing in the output current and voltage; therefore
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22' 2
LCQ
CC
CQ
CCL Ra
IV
IVR ===
• The maximum power delivered to the load is equal to
the maximum average power delivered to the primary of the ideal transformer, as follows:
CQCCL IVP21(max) =
where VCC and ICQ are the maximum possible amplitudes of the sinusoidal signals
• If the power dissipation in the bias resistors R1 and R2
is neglected, the average power supplied by the VCC source is
CQCCS IVP =
• The maximum possible power conversion efficiency is
%5021(max)(max) ⇒==
S
L
PPη
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Class-C Operation
• In class-C operation an output transistor conducts for less than half a cycle
• The collector current versus time characteristics of a
class-C amplifier is shown in Figure 12.12
Figure 12.12 - The collector current versus time characteristics of a class-C amplifier
• The transistor circuit ac load line, including an extension beyond cutoff, is shown in Figure 12.13
Figure 12.13 – Effective ac load line of a class-C amplifier
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• For class-C operation. The transistor has a reverse-biased B-E voltage at the Q-point
• The effect of this class of operation is illustrated in
Figure 12.13
• Note that the collector current is not negative, but is zero at the quiescent point
• The transistor conducts only when the input signal
becomes sufficiently positive during its positive half-cycle
• The transistor therefore conducts for less than a half-
cycle, which defines class-C operation
• Class-C amplifiers are capable of providing large amounts of power, with conversion efficiencies larger than 78.5%
• These amplifiers are normally used for radio-frequency
(RF) circuits, with tuned RLC loads that are commonly used in radio and television transmitters
• The RLC circuits convert drive current pulses into
sinusoidal signals
• Since this is a specialized area, these circuit will not be analyzed in this course
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DIFFERENTIAL AMPLIFIERS Introduction
• Differential amplifier, or diff-amp, is a special multitransistor circuit configuration
• Diff-amp is a fundamental building block of analog
circuits
• It is the input stage of virtually every opamp, and it is the basis of a high-speed digital logic circuit family, called emitter-coupled logic
• A block diagram of the diff-amp is shown in Figure 13.1
Figure 13.1 – Diff-amp block diagram
• There are two input terminals and one output terminal
• Ideally, the output signal is proportional to only the difference between the two input signals
• The ideal output voltage can be written as
)( 21 vvAv volo −=
where Avol is called open-loop voltage gain
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• In the ideal case, if v1 = v2, the output voltage is zero
• A non-zero output voltage is obtained if v1 and v2 are
not equal
• The differential-mode input voltage is defined as
21 vvvd −=
• The common-mode input voltage is defined as
221 vvvcm
+=
• This equations shows that if v1 = v2, the differential-
mode signal is zero and the common-mode input signal is vcm = v1 = v2
• If each pair of input voltages were applied to the ideal
difference amplifier, the output voltage in each case would be exactly the same
• However, amplifiers are not ideal, and the common-
mode input signal does not affect the output
• One goal of the design of diff-amps is to minimize the effect of the common-mode input signal
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Basic BJT Differential Pair
• Figure 13.2 shows the basic BJT differential-pair configuration
Figure 13.2 – Basic BJT differential-pair configuration
• Two identical transistors Q1 and Q2, whose emitters are connected together, are biased by a constant-current source IQ, which is connected to a negative supply voltage V-
• The collectors of Q1 and Q2 are connected through
resistors RC to a positive supply voltage V+
• By design, transistors Q1 and Q2 are to remain biased in the forward-active region
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• Here, it is assumed that the two collector resistors RC are equal, and that vB1 and vB2 are ideal sources, meaning that the output resistances of these sources are negligibly small
• Since both positive and negative bias voltages are used
in the circuit, the need for coupling capacitors and voltage divider biasing resistors at the inputs of Q1 and Q2 has been eliminated
• If the input signal voltages vB1 and vB2 in the circuit
shown in Figure 13.2 are both zero, Q1 and Q2 are are still biased in the active region by the current source IQ
• The common-emitter voltage vE would be on the order
of -0.7 V
• This circuit, then, is referred to as a dc-coupled diff-amp, so differences in dc input voltages can be amplified
• Although the diff-amp contains two transistors, it is
considered a single-stage amplifier – the analysis shows that it has characteristics similar to those of the common-emitter amplifier
Basic Diff-Amp With Common-Mode Input
• Consider the circuit in which the two base terminals are connected together and a common-mode voltage vcm is applied as shown in Figure 13.3
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Figure 13.3 - Basic Diff-Amp With Common-Mode Input
• The transistors are biased “on” by the constant-current source, and the voltage at the common emitters is
)(onVvv BEcmE −=
• Since , Q1 and Q2 are matched or identical, current IQ
splits evenly between the two transistors, and
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221Q
EEI
ii ==
• If base currents are negligible, then 11 EC ii ≅ and
22 EC ii ≅ , and
21 2 CCQ
C vRI
Vv =−= +
• This equation shows that for an applied common-mode
voltage, IQ splits evenly between Q1 and Q2 and the difference between vC1 and vC2 is zero
Basic Diff-Amp With Differential-Mode Input
• A basic diff-amp with differential-mode input is shown in Figure 13.4
• If vB1 increases by a few millivolts and vB2 decreases by
the same amount, or 2/1 dB vv = and 2/2 dB vv −= , the voltages at the bases of Q1 and Q2 are no longer equal
• Since the emitters are common, this means that the B-
E voltages on Q1 and Q2 are no longer equal
• Since vB1 increases and vB2 decreases, then vBE1>vBE2, which means that iC1 increases by ΔI above its quiescent value and iC2 decreases by ΔI below its quiescent value
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Figure 13.4 - A basic diff-amp with differential-mode input
• A potential difference now exists between the two collector terminals
• The differential output is
C
CCQ
CCQ
CC
RI
RII
VRII
Vvv
Δ=
⎥⎦
⎤⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛Δ+−−⎥
⎦
⎤⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛Δ−−=− ++
2
2212
• A voltage difference is created between vC1 and vC2
when a differential-mode input voltage is applied
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Small-Signal Equivalent Circuit Analysis
• If the diff-amp is assumed to be operating in the linear range, the gain and other characteristics of the amplifier can be derived using the small-signal equivalent circuit
• The small-signal equivalent circuit of the bipolar
differential-pair configuration is shown in Figure 14.1
Figure 14.1 - Small-signal equivalent circuit of the bipolar differential-pair configuration
• Here, it is assumed that the Early voltage is infinite for the two emitter-pair transistors, and that the constant-current source is not ideal but can be represented by a finite output impedance, Ro
• Resistances RB are also included, representing the
output resistance of the signal voltage sources
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• All voltages are represented by their phasor components
• Since the two transistors are biased at the same
quiescent current, then πππ rrr == 21
• Writing a KCL equation at node Ve, using phasor notation,
o
emm R
Vr
VVgVgr
V=+++
π
πππ
π
π 221
1 (14.1)
or
o
e
RV
rV
rV =⎟⎟
⎠
⎞⎜⎜⎝
⎛ ++⎟⎟
⎠
⎞⎜⎜⎝
⎛ +
ππ
ππ
ββ 1121 (14.2)
where βπ =rgm
• From the circuit, it can be seen that
B
eb
RrVV
rV
+−
=ππ
π 11 and
B
eb
RrVV
rV
+−
=ππ
π 22
• Solving for Vπ1 and Vπ2 and substituting in the above
equation,
o
e
Bebb R
VRr
VVV =⎟⎟⎠
⎞⎜⎜⎝
⎛++
−+π
β1)2( 21 (14.3)
• Solving for Ve, we obtain
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o
B
bbe
RRr
VVV
)1(2
21
βπ
++
+
+=
(14.4)
One-Sided Output
• If we consider a one-sided output at the collector of Q2, then
B
ebCCmCo Rr
VVRRVgVV+
−−=−==
ππ
β )()( 222 (14.5)
• Substituting Equation (14.4) into (14.5) gives
⎪⎪⎭
⎪⎪⎬
⎫
⎪⎪⎩
⎪⎪⎨
⎧
++
+
−⎥⎦
⎤⎢⎣
⎡++
+−=
o
B
bo
B
B
Co
RRr
VR
RrV
RrRV
)1(2
)1( 12
β
ββπ
π
π (14.6)
• In an ideal constant-current source, the output
resistance is ∞=oR , and Equation (14.6) reduces to
)(2)( 12
B
bbCo Rr
VVRV+−
−=π
β (14.7)
• The differential-mode input is
21 bbd VVV −= (14.8)
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• The differential-mode gain is
)(2 B
C
d
od Rr
RVVA
+==
π
β (14.9)
• It can be seen that when a common-mode signal
21 bbcm VVV == is applied, the output voltage is no longer zero
• 1bV and 2bV can be written in terms of dV and cmV as
21d
cmbVVV += (14.10)
and
22d
cmbVVV −= (14.11)
• Equation 14.10 and 14.11 simply state that the two
input signals can be written as the sum of a differential-mode input signal component and a common-mode input signal component
• Substituting Equation 14.10 and 14.11 into Equation
14.6 and rearranging terms results in the following:
cm
B
o
Cmd
B
Co V
RrR
RgVRr
RV ⋅
++
+−⋅
+=
π
πβ
β)1(21)(2 (14.12)
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• The output voltage in Equation 14.12 can be written in the general form
cmcmddo VAVAV += (14.13)
where Ad is the differential-mode gain and Acm is the common-mode gain
• Comparing Equations 14.13 and 14.13, it can be seen
that
)(2 B
Cd Rr
RA+
=π
β (14.14)
and
B
o
Cmcm
RrR
RgA
++
+
−=
π
β )1(21 (14.15)
• It can be observed that the common-mode gain goes to
zero for an ideal current source in which ∞=oR
• For an ideal current source, oR is finite and the common-mode gain is not zero for this case of a one-sided output
• A nonzero common-mode gain implies that the diff-amp
is not ideal
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Common-Mode Rejection Ratio
• The ability of a differential amplifier to reject a common-mode signal is described in terms of the common-mode rejection ratio (CMRR)
• The CMRR is a figure of merit for the diff-amp and is
defined as
cm
d
AA
=CMRR
• For an ideal diff-amp, 0=cmA and CMRR=∞
• Usually, the CMRR is expressed in decibels, as follows:
cm
d
AA
10log20CMRR =
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Differential- and Common-Mode Gains
• For greater insight into the mechanism that causes differential- and common-mode gains, reconsider the diff-amp when pure differential- and common-mode signals are applied
Diff-amp with applied differential-mode input signal
• Figure 15.1 shows the ac equivalent circuit of the diff-amp with two sinusoidal input signals
Figure 15.1 – Equivalent ac circuit of thediff-amp with
applied sinusoidal differential-mode input signal
• The two input voltages are 180° out of phase, so a pure differential-mode signal is being applied to the diff-amp
• For this these inputs, vb1 + vb2 = 0, so, from the
equation
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o
B
bbe
RRr
VVV
)1(2
21
βπ
++
+
+=
it can be seen that the common emitters of Q1 and Q2 remain at signal ground
• In essence, the circuit behaves like a balanced seesaw
• As the base voltage of Q1 goes into its positive-half
cycle, the base voltage of Q2 is in its negative half-cycle
• Then, as the base voltage of Q1 goes into its negative half-cycle, the base voltage of Q2 is in its positive half-cycle
• The signal current directions shown in the figure are
valid for vb1 in its positive half-cycle
• Since ve is always at ground potential, each half of the diff-amp can be treated as a common-emitter circuit
• Figure 15.2 shows the differential half-circuits, clearly
depicting the common-emitter configuration
• The differential-mode characteristics of the diff-amp can be determined by analyzing the half-circuit
• In evaluating the small-signal hybrid-π parameters, it
should be kept in mind that the half-circuit is biased at
2QI
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Figure 15.2 – Differential-mode half-circuits of a diff-amp
applied with differential-mode input signal Diff-amp with applied common-mode input signal
• The ac equivalent circuit of the diff-amp with a pure common-mode sinusoidal input signal is shown in Figure 15.3
• In this case, the two input voltages are in phase
• The current source is represented as an ideal source IQ
in parallel with its output resistance Ro
• Current iq is the time varying component of the source current
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• As the two input signals increase, voltage ve increases
and current iq increases
• Since this current splits evenly between Q1 and Q2, each collector current also increases
• The output voltage vo then decreases below its
quiescent value
• As the two input voltages go through the negative half-cycle, all signal currents shown in the figure reverse direction, and vo increases above its quiescent value
• Consequently, a common-mode sinusoidal input signal
produces a sinusoidal output voltage, which means that the diff-amp has a nonzero common-mode voltage gain
• If the value of Ro increases, the magnitude of iq
decreases for a given common-mode input signal, producing a smaller output voltage and hence a smaller common-mode gain
• With an applied common-mode voltage, the circuit
shown in Figure 15.3 is perfectly symmetrical
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Figure 15.3 – Equivalent ac circuit of diff-amp with common-mode input signal, and resulting signal current directions
• The circuit can therefore be split into the identical common-mode half-circuit shown in Figure 15.4
• The common-mode characteristics of the diff-amp can
then be determined by analyzing the half-circuit, which is a common-emitter configuration with an emitter resistor
• Each half-circuit is biased at 2QI
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Figure 15.4 – Common-mode half-circuits
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Differential- and Common-Mode Input Impedances • The input impedance, or resistance, of an amplifier is
as important a property as the voltage gain
• The input resistance determines the loading effect of the circuit on the signal source
Differential-Mode Input Resistance
• The differential-mode input resistance is the resistance seen by a differential-mode signal source
• It is the effective resistance between the two input base
terminals when a differential-mode signal is applied
• A diff-amp with a pure differential input signal is shown in Figure 15.5
Figure 15.5 – BJT diff-amp with differential-mode input signal, showing differential input resistance
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• The applicable differential-mode half-circuits are shown
in Figure 15.6
Figure 15.6 – Differential-mode half-circuits of a diff-amp applied with differential-mode input signal
• For this circuit, we have
πriv
b
d =2
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• The differential-mode input resistance is therefore
πrivR
b
did 2==
• Another common diff-amp configuration uses emitter
resistors, as shown in Figure 15.7
Figure 15.7 – BJT diff-amp with emitter resistors
• With a pure applied differential-mode voltage, similar differential-mode half-circuits are applicable to this configuration
• To find the differential-mode input resistance, the
resistance reflection rule is used;
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Eb
d Rri
v )1(2 βπ ++=
• Therefore,
[ ]Eb
did Rr
ivR )1(2 βπ ++==
• The above equation implies that differential-mode input
resistance increases significantly when emitter resistors are included
• Although the differential-mode gain decreases when
emitter resistors are included, a larger differential-mode voltage (greater than 18 mV) may be applied and the amplifier remains linear
Common-Mode Input Resistance
• A diff-amp with an applied common-mode voltage is shown in Figure 15.8
• The small-signal output resistance Ro of the constant-
current source is shown in Figure 15.8(a), and the equivalent common-mode half-circuits are shown in Figure 15.8(b)
• Since the half-circuits are in parallel, we can write
)2)(1()2)(1(2 ooicm RRrR ββπ +≅++=
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Figure 15.8 – (a) BJT diff-amp with common-mode input signal, including finite current source resistance and (b) equivalent common-mode half-circuit
• The above equation is a first approximation for
determining the common-mode input resistance
• Normally, Ro is large, and Ricm is typically in the megohm range
• Therefore, the transistor output resistance ro and the
base-collector resistance rμ may need to be included in the calculation
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• The more complete equivalent half-circuit model is shown in Figure 15.8(b)
• For this model, we have
])1[(||)]2)(1[(||2 ooicm rRrR ββμ ++=
• Therefore,
⎥⎦
⎤⎢⎣
⎡⎟⎠⎞
⎜⎝⎛++⎟⎟
⎠
⎞⎜⎜⎝
⎛=
2)1(||)])(1[(||
2o
oicmrR
rR ββμ
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OPERATIONAL AMPLIFIER Introduction
An operational amplifier (op-amp) is an electronic device that amplifies the difference voltage between the two inputs
A typical op-amp is made up of three types of amplifier circuits: a differential amplifier, a voltage amplifier, and a push-pull amplifier, as shown in Figure 16.1
Figure 16.1 – Basic internal arrangement of an op-amp
A differential amplifier is the input stage for the op-amp; it has two inputs and provides amplification of the difference voltage between the two inputs
The voltage amplifier is usually a class-A amplifier that provides additional gain
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Some op-amps may have more than one voltage amplifier stage
A push-pull class-B amplifier is generally used for the output stage
Symbol and Terminals
The standard op-amp symbol is shown in Figure 16.2
(a) Symbol (b) Symbol with dc supply connection
Figure 16.2 – Standard op-amp symbol
It has two input terminals, the inverting input (-) and the noninverting input (+), and one output terminal
The typical op-amp operates with two dc supply voltages, one positive and the other negative, as shown in Figure 16.2(b)
Usually these dc voltage terminals are left off the schematic symbol for simplicity but are always understood to be there
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Some typical op-amp IC packages are shown in Figure 16.3
Figure 16.3 - Some typical op-amp IC packages Ideal Op-Amp
The ideal op-amp has infinite voltage gain and an infinite input resistance (open), so that it does not load the driving source
Also, it has a zero output resistance
These characteristics are illustrated in Figure 16.4
Figure 16.4 – An ideal op-amp representation
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The input voltage Vin appears between the two input terminals, and the output voltage is AvVin, as indicated by the internal voltage source symbol
The concept of infinite input resistance is a particularly valuable analysis tool for the various op-amp configurations
A practical op-amp, of course, falls short of these ideal standard, but it is much easier to understand and analyze the device from an ideal point of view
The Practical Op-Amp
Although modern integrated circuit (IC) op-amps approach parameter values that can be treated as ideal in many cases, no practical op-amp can be ideal
Any device has limitations, and the IC op-amp is no exception
Op-amps have both voltage and current limitations
For example, its peak-to-peak output voltage is usually limited to slightly less than the difference between the two supply voltages
Output current is also limited by internal restrictions such as power dissipation and component ratings
Characteristics of a practical op-amp are high voltage gain, high input resistance and low output resistance
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Some of these characteristics are illustrated in Figure 16.5
Figure 16.5 – Characteristics of a practical op-amp
Op-Amp Parameters
Op-amp parameters are used to specify performance and provide for comparison of different op-amps
Three important parameters of an op-amp are o Open-loop voltage gain o Common-mode rejection ratio (CMRR) o Slew rate
Other parameters include o Input offset voltage o Input bias current o Input resistance o Output resistance o Common-mode input voltage range
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Input Offset Voltage
The ideal op-amp produces zero volts out for zero volts in
However, in practical op-amp a small dc voltage VOUT(error) appears at the output when no differential input voltage is applied
Its primary cause is a slightly mismatch of the transistors in the differential input stage of an op-amp, as illustrated in Figure 16.6
(a) (b)
Figure 16.6 – Illustration of input offset voltage
As specified on an op-amp data sheet, the input offset voltage (Vos) is the differential dc voltage required between the inputs to force the output to zero volts
Vos is demonstrated in Figure 16.6(b)
Typical values of input offset voltage are in the range of 2 mV or less; in ideal case, it is zero
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Input Bias Current
The input terminals of a bipolar differential amplifier are the transistor bases and, therefore, the input currents are the base current
The input bias current is the dc current required by the inputs of the amplifier to properly operate the first stage
By definition, the input bias current is the average of both input currents
The input bias current is so small in most practical applications that it can be considered to be zero
The concept of input bias current is illustrated in Figure 16.7
Figure 16.7 – Input bias current is the average of the two op-amp input currents
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Input Resistance
Two basic ways of specifying the input resistance of an op-amp are the differential and the common-mode
The differential input resistance is the total resistance between the inverting and the non-inverting inputs, as illustrated in Figure 16.8(a)
(a) (b)
Figure 16.8 – Op-amp input resistance (a) Differential input resistance (b) Common-mode input resistance
Differential input impedance is measured by determining the change in bias current for a given change in differential input voltage
The common-mode input resistance is the resistance between each input and ground and is measured by determining the change in bias current for a given change in common-mode input voltage, as illustrated in Figure 16.8(b)
The input resistance is always very high
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Output Resistance
Output resistance is the resistance viewed from the output terminal of the op-amp, as indicated in Figure 16.9
Figure 16.9 – Op-amp output resistance
The output resistance is always very small Common-Mode Input Voltage Range
All op-amps have limitations on the range of voltages over which they will operate
The common-mode input voltage range is the range is the range of input voltages which, when applied to both inputs, will not cause clipping or other output distortion
Many op-amps have common-mode ranges of no more
than 10 V with dc supply voltages of 15 V, while in others the output can go as high as the supply voltages (this is called rail-to-rail)
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Open-Loop Voltage Gain
The open-loop voltage gain, Aol, of an op-amp is the internal voltage gain of the device measured in the differential mode
It represent the ratio of output voltage to input voltage when there is no external components, as shown in Figure 16.10
Figure 16.10 – Open-loop op-amp
The open-loop voltage gain is set entirely by the internal design
Open-loop voltage gain can range up to 200,000 or more and is not a well-controlled parameter
Data sheets often refer to the open-loop voltage gain as the large-signal voltage gain
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Common-Mode Rejection Ratio
The common-mode rejection ratio (CMRR) for an op-amp is a measure of an op-amp’s ability to reject common-mode signals
An infinite value of CMRR means that the output is zero when the same signal is applied to both inputs (common-mode)
An infinite CMRR is never achieve in practice, but a good op-amp does have a very high value of CMRR.
Common-mode signals are undesired interference voltages such as 50 Hz power supply ripple and noise voltages due to pick-up of radiated energy
A high CMRR enables the op-amp to virtually eliminate these interference signals from the output
The accepted definition of CMRR for an op-amp is the open-loop gain (Aol) divided by the common-mode gain
cm
ol
A
ACMRR
This is equivalent to the CMRR for a differential amplifier
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Slew Rate
The slew rate of an op-amp is the maximum rate of change of the output voltage in response to a step input voltage
The slew rate is dependent upon the high frequency response of the amplifier stages within the op-amp
Slew rate is measured with an op-amp connected as shown in Figure 16.11
Figure 16.11 – Slew rate measurement
This particular op-amp connection is a unity-gain non-inverting configuration, which gives a worst case (slowest) slew rate
The high-frequency components of a voltage step are contained in the rising edge, and the upper critical frequency of an amplifier limits its response to a step input
The lower the upper critical frequency is, the more gradual the slope on the output for a step input
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A pulse is applied to the input as shown in Figure 11.12, and the ideal output voltage is measured as indicated
Figure 16.12 – Step input voltage and the resulting output voltage
The width of the input pulse must be sufficient to allow the output to “slew” from its lower limit to its upper limit, as shown
It can be seen that a certain time interval, t, is required for the output voltage to go from its lower limit –Vmax to its upper limit +Vmax, once the input step is applied
The slew rate is expressed as
s)(V/ dsmicroseconper voltsrate Slew t
Vout
where )( maxmax VVVout
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Op-Amp Configurations
An op-amp can be connected in three basic ways using negative feedback to stabilize and reduce the gain and increase frequency response
The extremely high open-loop gain of an op-amp creates an unstable condition in which an op-amp can be driven out of its linear region or it can oscillate
In addition, the open-loop gain parameter of an op-amp can vary greatly from one device to the next
Closed-Loop Voltage Gain
The closed-loop gain, Acl is the voltage gain of an op-amp with negative feedback
The amplifier configuration consists of the op-amp and an external feedback circuit that connects the output to the inverting input
The closed-loop voltage gain is then determined by the component values in the feedback circuit and can be precisely controlled by them
Noninverting Amplifier
A non inverting amplifier is an op-amp connected in a closed-loop configuration in which the input signal is applied to the noninverting input (+), as shown in Figure 17.1
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Figure 17.1 – Noninverting amplifier
A proportion of the output is applied back to the inverting input (-) through the feedback circuit, which constitutes negative feedback
The differential voltage, Vdiff, between the op-amp’s input terminals is illustrated in Figure 17.2 and can be expressed as
findiff VVV
Figure 17.2 – Differential input
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This input differential voltage is forced to be very small as a result of the negative feedback and the high open-loop gain, Aol
Therefore, a close approximation is V0diffV
It can be assumed that fin VV
Resistor Ri and Rf form a voltage-divider network
The fraction of the output voltage, Vout, that is returned to the inverting input is found by applying the voltage-divider rule to the feedback circuit
out
fi
if V
RR
RV
The closed-loop voltage gain is inout VV
Since fin VV , the previous equation can be written as
i
f
i
fi
in
outv
R
R
R
RR
V
VA
1
This equation shows that the closed-loop voltage gain of the noninverting amplifier is not dependent on the op-amp’s open-loop gain but can be set by selecting values of Ri and Rf
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The equation is based on the assumption that the open-loop gain is very high compared to the ratio of the feedback resistors, causing the input differential voltage, Vdiff, to be zero
Voltage-Follower
The voltage-follower is a special case of the noninverting amplifier where all of the output voltage is fed back to the inverting input by a straight connection, as shown in Figure 17.3
Figure 17.3 – Op-amp voltage follower
The straight feedback connection produces a voltage gain of approximately 1, so the closed-loop gain of the voltage-follower is unity
The most important features of the voltage-follower configuration are its very high input resistance and its very low output resistance
These features make it a nearly ideal buffer amplifier for interfacing the high-resistance sources and the low-resistance loads
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Inverting Amplifier
An op-amp connected in a closed-loop configuration in which the input signal is applied through a series resistors to the inverting input (-) is an inverting amplifier, as shown in Figure 17.4
Figure 17.4 – Inverting amplifier
The output is fed back through Rf to the inverting input, and the non inverting input is grounded
The infinite input resistance in an ideal amplifier implies that there is no current in or out of the inverting input
If there is no current through the input resistance, then there must be no voltage drop between the inverting and noninverting inputs
This means that the voltage at the inverting input (-) is zero because the noninverting input (+) is grounded
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This zero-voltage at the inverting input terminal is referred to as virtual ground, as illustrated in Figure 17.5
Figure 17.5 – Virtual ground
Since there is no current at the inverting input, the current through Ri and the current through Rf are equal, as shown in Figure 17.6
Figure 17.6 – Iin = If and current at the inverting input (-) is 0
The voltage across Ri equals Vin because of virtual ground on the other side of the resistor
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Also, the voltage across Rf equals –Vout because of virtual ground
Since If = Iin,
i
in
f
out
R
V
R
V
Rearranging the terms,
i
f
in
out
R
R
V
V
Of course, inout VV is the closed-loop gain of the
inverting amplifier, i.e.
i
f
in
outv
R
R
V
VA
The above equation shows that the closed-loop voltage gain of the inverting amplifier is the ratio of the feedback resistance Rf to the resistance Ri
The closed-loop gain is independent of the op-amp’s internal open-loop gain
Thus, the negative feedback stabilizes the voltage gain
The negative sign indicates inversion
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Effect of Negative Feedback on Bandwidth
Figure 17.7 graphically illustrates the concept of closed-loop frequency response for an op-amp with negative feedback
Figure 17.7 – Closed-loop gain compared to open-loop gain
When the open-loop gain of an op-amp is reduced by negative feedback, the bandwidth is increased
The closed-loop gain in independent of the open-loop gain up to the point of intersection of the two gain curves
This point of intersection is the critical frequency, fc(cl), for the closed-loop response, which equals the closed-loop bandwidth, BWcl
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Notice that beyond the closed-loop critical frequency the closed-loop gain decreases at the same rate (called the roll-off rate) as the open-loop gain
Gain-Bandwidth Product
An increas in closed-loop gain causes a decrease in the bandwidth and vice versa, such that the product of gain and bandwidth is a constant
This is true as long as the roll-off rate is a fixed -20db/decade
If Acl represents the gain of any of the noninverting closed-loop configurations and fc(cl) represents the closed-loop critical frequency (same as the bandwidth), then
ololclcl fAfA
The gain-bandwidth product is always equal to the frequency at which the op-amp’s open-loop gain is unity (unity-gain bandwidth)
bandwidthgain -unityclcl fA
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Basic Op-Amp Circuits
Op-amps are used in such a wide variety of applications
In this lecture, we will discuss only a few of the commonly used circuits, especially in the field of signal processing and instrumentation
Comparators
Operational amplifiers are often used as nonlinear devices to compare the amplitude of one voltage with another
In this application, the op-amp is used in the open-loop configuration, with the input voltage on one input and a reference voltage on the other
Zero-Level Detector
A comparator is a circuit that compares two input voltages and produces an output in either of two states indicating the greater than or less than relationships of the inputs
One application of an op-amp used as a comparator is to determine when an input voltage exceed a certain level
A zero-level detector circuit is shown in Figure 18.1
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Figure 18.1 – The op-amp as a zero-level detector
Notice that the inverting input (-) is grounded to produce a zero level and that the input signal voltage is applied to the noninverting input (+)
Because of the high open-loop voltage gain, a very small difference voltage between the two inputs drives the amplifier into saturation, causing the output voltage to go to its limit
For example, consider an op-amp having Aol = 100,000; a voltage difference of only 0.25 mV between inputs could produce an output of (0.25 mV)(100,000) = 25 V if the op-amp were capable
However, since most op-amps have output voltage
limitations of 15 V or less, the device would be driven into saturation
For many comparison applications, special op-amp comparators are used, such as the LM311 and LM711
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These ICs are generally maximize switching speed
In less stringent applications, a general-purpose op-amp works nicely as a comparator
Figure 18.2 shows the result of a sinusoidal input voltage applied to the noninverting input of the zero-level detector
Figure 18.2 - result of a sinusoidal input voltage applied to the noninverting input of the zero-level detector
When the sine wave is negative, the output is at its maximum negative level
When the sine wave crosses 0, the amplifier is driven to its opposite state and the output goes to its maximum positive level, as shown
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It can be seen that the zero-level detector can be used as a squaring circuit to produce a square wave from a sine wave
Nonzero-Level Detector
The zero-level detector can be modified to detect positive and negative voltages by connecting a fixed reference voltage to the inverting input (-), as shown in Figure 18.3(a)
Figure 18.3 – Nonzero-level detectors
A more practical arrangement is shown in Figure 18.3(b) using a voltage divider to set the reference voltage as follows:
)(21
2 VRR
RVREF
where +V is the positive op-amp supply voltage
The circuit in Figure 18(c) uses a zener diode to set the reference voltage (VREF = VZ)
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As long as the input voltage Vin is less than VREF, the output remains at the maximum negative level
When the input voltage exceeds the reference voltage, the output goes to its maximum positive state, as shown in Figure 18.4 with a sinusoidal input voltage
Figure 18.4 – Nonzero voltage comparator with sinusoidal input
Effects of Input Noise on Comparator Operation
In many practical situations, noise (unwanted voltage or current fluctuations) may appear on the input line
This noise voltage becomes superimposed on the input voltage, as shown in Figure 18.5, and can cause a comparator to erratically switch output states
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Figure 18.5 – Sine wave with superimposed noise
In order to understand the potential effects of noise voltage, consider a low-frequency sinusoidal voltage applied to the noninverting input (+) of an op-amp comparator used as a zero-level detector, as shown in Figure 18.6
Figure 18.6 – Effects of noise on comparator circuit
Figure 18.7 shows the input sine wave plus noise and the resulting output
It can be seen that when the sine wave approaches 0, the fluctuations due to noise cause the total input to vary above and below 0 several times, thus producing an erratic output voltage
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Figure 18.7 – The input sine wave plus noise and the resulting output of a comparator
Reducing Noise Effects with Hysteresis
An erratic output caused by noise on the input occurs because the op-amp comparator switches from its negative output state to its positive output state at the same input voltage level that causes it to switch in the opposite direction, from positive to negative
This unstable condition occurs when the input voltage hovers around the reference voltage, and any small noise fluctuations cause the comparator to switch first one way and then the other
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In order to make the comparator less sensitive to noise, a technique incorporating positive feedback, called hysteresis, can be used
Hysteresis uses two reference levels
The two reference levels are referred to as the upper trigger point (UTP) and the lower trigger point (LTP)
This two-level hysteresis is established with a positive feedback arrangement, as shown in Figure 18.8
Figure 18.8 – Comparator with positive feedback for hysteresis
Notice that the noninverting input (+) is connected to a resistive voltage divider such that a portion of the output voltage is fed back to the input
The input signal is applied to the inverting input (-) in this case
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The basic operation of the comparator with hysteresis is as follows, with reference to Figure 18.7
Assume that the output voltage is at its positive maximum, +Vout(max)
The voltage fed back to the inverting input is VUTP and is expressed as
)( (max)
21
2UTP outV
RR
RV
When the input voltage Vin exceed VUTP, the output voltage drops to its negative maximum, -Vout(max)
Now the voltage fed back to the noninverting input is VLTP and is expressed as
)( (max)
21
2LTP outV
RR
RV
The input voltage must now fall below VLTP before the device will switch back to its other voltage level
This means that a small amount of noise voltage has no effect on the output, as illustrated by Figure 18.9
A comparator with hysteresis is sometimes known as a Schmitt trigger
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The amount of hysteresis is defined by the difference of the two trigger levels
LTPUTPHYS VVV
Figure 18.9 – Operation of a comparator with histeresis. The device triggers only once when the UTP and LTP is reached; thus, there is immunity to noise that is riding on the input signal
A Comparator Application: Over Temperature Sensing Circuit
Figure 18.10 shows an op-amp comparator used in a precision over-temperature sensing circuit to determine when the temperature reaches a certain critical value
The circuit consists of a Wheatstone bridge with the op-amp used to detect when the bridge is balanced
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Figure 18.10 – An over-temperature sensing circuit
One leg of the bridge contains a thermistor (R1), which is a temperature-sensing resistor with a negative temperature coefficient (its resistance decreases as temperature increases and vice versa).
The potentiometer (R2) is set at a value equal to the resistance of the thermistor at the critical temperature
At normal temperatures (below critical), R1 is greater than R2, thus creating an unbalanced condition that drives the op-amp to its low saturated output level and keeps transistor Q1 off
As the temperature increases, the resistance of the thermistor decreases
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When the temperature reaches the critical value, R1 becomes equal to R2, and the bridge becomes balanced (since R3 = R4)
At this point the op-amp switches to its high saturated output level, turning Q1 on
This energizes the relay, which can be used to activate an alarm or initiate an appropriate response to the over-temperature condition
Summing Amplifier
The summing amplifier is a variation of the inverting op-amp configuration
The summing amplifier has two or more inputs, and its output voltage is proportional to the negative of algebraic sum of its input voltages
A two-input summing amplifier is shown in Figure 18.11, but any number of inputs can be used
Figure 18.11 – Two-input inverting summing amplifier
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The operation of the circuit and derivation of the output expression are as follows.
Two stages, VIN1 and VIN2, are applied to the inputs and produce current I1 and I2 as shown
From the concepts of infinite input resistance and virtual ground, the voltage at the inverting input (-) of the op-amp is approximately 0 V, and therefore there is no current at the inverting input
This means that both input currents I1 and I2 combine at this summing point and form the total current, which is through Rf, as indicated (IT = I1 + I2)
Since fT RIV OUT , the following steps apply
ff RR
V
R
VRIIV
2
IN2
1
IN121OUT )(
If all three of the resistors are equal in value
)( 21 RRRR f , then
)( IN2IN1IN2IN1
OUT VVRR
V
R
VV
The previous equation shows that the output voltage has the same magnitude as the sum of the two input voltages but with a negative sign
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A general expression for a summing amplifier shown in Figure 18.12 with n inputs, where all resistors are equal in value is
)...( ININ2IN1OUT nVVVV
Figure 18.12 – Summing amplifier with n inputs
Integrator
An integrator is a circuit that produces an inverted output that approximates the area under the curve of the input function
An ideal integrator is shown in Figure 18.13
Notice that the feedback element is a capacitor that forms an RC circuit with the input resistor
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Figure 18.13 – An ideal op-amp integrator
How a Capacitor Charges
To understand how the integrator works, it is important to review how a capacitor charges
Recall that the charge Q on a capacitor is proportional to the charging current (IC) and the time (t)
tIQ C
Also, in terms of the voltage, the charge on a capacitor is
CVCQ
From these two relationships, the capacitor voltage can be expressed as
tC
IV C
C
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This expression is an equation for a straight line which begins at zero with a constant slope of IC/C
The capacitor voltage in a simple RC circuit is not linear but is exponential
This is because the charging current continuously decreases as the capacitor charges and causes the rate of change of the voltage to continuously decrease
The advantage of using an op-amp with an RC circuit to form an integrator is that the capacitor’s charging current is made constant, thus producing a straight-line (linear) voltage rather than an exponential voltage
In Figure 18.14 the inverting input of the op-amp is at virtual ground (0 V), so the voltage across Ri equals Vin
Figure 18.14 – Currents in an integrator
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Therefore, the input current is
i
inin
R
VI
If Vin is a constant voltage, then Iin is also a constant because the inverting input always remains at 0 V, keeping a constant voltage across Ri
Because of the very high input impedance of the op-amp, there is negligible current at the inverting input
This makes all of the input current charge the capacitor, so
inC II
The Capacitor Voltage
Since Iin is constant, so is IC – The constant IC charges the capacitor linearly and produces a linear voltage across C
The positive side of the capacitor is held at 0 V by the virtual ground of the op-amp
The voltage on the negative side of the capacitor decreases linearly from zero as the capacitor charges, as shown in Figure 18.15
This voltage is called a negative ramp and is the consequence of a constant positive input
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Figure 18.15 – A linear ramp voltage is produced across C by the constant charging current
The Output Voltage
Vout is the same as the voltage on the negative side of the capacitor
When a constant positive input voltage in the form of a step or pulse ( a pulse has a constant amplitude when high) is applied, the output ramp decreases negatively until the op-amp saturates at its maximum negative level, as indicated in Figure 18.16
Figure 18.16 – A constant input voltage produces a ramp on the output of the integrator
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The Rate of Change of the Output
The rate at which the capacitor charges, and therefore the slope of the output ramp, is set by the ratio IC/C.
Since iinC RVI , the rate of change or slope of the
integrator’s output voltage is
CR
V
i
inchange of rateOutput
Integrators are especially useful in triangular-wave generators
Differentiator
A differentiator is a circuit that produces an inverted output that approximates the rate of change of the input function
An ideal differentiator is shown in Figure 18.17, where the capacitor is now the input element of the circuit
Figure 18.17 – An ideal op-amp differentiator
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A differentiator produces an output that is proportional to the rate of change of the input voltage
Although a small-value resistor is normally used in series with the capacitor to limit the gain, it does not affect the basic operation and is not shown for the purpose of this analysis
Consider a positive-going ramp voltage as an input to the differentiator circuit, as shown in Figure 18.18
Figure 18.18 – A differentiator with a ramp input
In this case, IC = Iin and the voltage across the capacitor is equal to Vin at all times (VC = Vin) because of virtual ground on the inverting input
From the basic formula, which is tCIV CC )( ,
Ct
VI C
C
Since the current at the inverting input is negligible,
CR II
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Both currents are constant because the slope of the
capacitor voltage tVC is constant
The output voltage is also constant and equal to the voltage across Rf because one side of the feedback resistor is always 0 V (virtual ground)
fCfRout RIRIV
Substituting CtVC )( for IC
CRt
VV f
Cout
The output is negative when the input is a positive-going ramp and positive when the input is a negative-going ramp, as illustrated in Figure 18.19
Figure 18.19 – Output of a differentiator with a series of positive and negative ramps (triangle wave) on the input
During the positive slope of the input, the capacitor is charging from the input source with constant current through the feedback resistor
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During the negative slope of the input, the constant current is in the opposite direction because the capacitor is discharging
Notice in the above equation that the term tVC is the
slope of the input
If the slope increases, Vout becomes more negative
If the slope decreases, Vout becomes more positive
So, the output voltage is proportional to the negative slope (rate of change) of the input
The constant of the proportionality is the time constant, RfC
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7.8 Combining Logic Gates
• Combinational logic is defined as an interconnection of logic gates to generate a specific logic function where the inputs result in an immediate output; having no memory or storage capabilities
• This is also sometimes called combinatorial logic • Digital circuits that have a memory or storage capability
are called sequential logic circuits 7.8.1 Constructing Circuits from Boolean Expressions
• Boolean expression is used as a guide in building logic circuit
• For example, consider the Boolean expression
YCBA =++
• The expression is read as “A or B or C equals output Y” and is realized using logic gate as shown in Figure 22.1
Figure 22.1 – Logic diagram for Boolean expression YCBA =++
• Next, consider a Boolean expression
YCBBABA =•+•+•
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• The expression is read as “not A and B, or A and not B, or not B and C equals output Y”
• The steps in constructing the Boolean expression is illustrated in Figure 22.2
Figure 22.2 – Steps 1 in constructing the Boolean expression YCBBABA =•+•+•
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Figure 22.3 – Steps 2 in constructing the Boolean expression YCBBABA =•+•+•
• Boolean expression comes in two forms: the sum-of-products (SOP), for example YCBBABA =•+•+• and the product-of-sum (POS), for example
YFEED =+•+ )()(
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• The sum-of-product form is called the minterm form in engineering text
• The product-of-sum is called the maxterm form by engineers, technicians and scientists
7.8.2 Drawing a Circuit from a Maxterm Boolean
Expression • Suppose the maxterm Boolean expression is
YBACBA =+•++ )()(
• The steps in constructing a logic circuit for this Boolean
expression is as follows:
Step 1: (Refer to Figure 22.4)
Figure 22.4 – Step 1 in constructing a product-of sums logic circuit
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Step 2: (Refer to Figure 22.5)
Figure 22.5 – Step 2 in constructing a product-of sums logic circuit
• In summary, we work from right to left (from output to input) when converting a Boolean expression to a logic circuit
• Maxterm and minterm Boolean expression both can be converted to logic circuits
• Minterm expressions create AND-OR logic circuits • Maxterm expressions create OR-AND logic circuits
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7.9 Truth Tables and Boolean Expressions
• Boolean expressions are a convenient method of describing how a logic circuit operates
• The truth table is another precise method of describing how a logic circuit works
• The works in digital electronics involve converting information from truth table form to a Boolean expression
7.9.1 Truth Table to Boolean Expression
• Consider the truth table shown in Figure 22.6
Figure 22.6 – Forming a mintern Boolean expression from a truth table
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• Notice that only two of the eight possible combinations
of inputs A, B, and C generate a logical 1 at the output • The two combinations that generate a 1 output are
ABC •• and ABC •• • The two combinations are ORed together to form the
Boolean expression for the truth table 7.9.1 Boolean Expression to Truth Table
• Consider the Boolean expression in Figure 22.7(a)
Figure 22.7 – Constructing a truth table from a minterm Boolean expression
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• It appears that two combinations of inputs A, B, and C generate a logical 1 at the output
• Figure 22.7(b) shows the correct combinations of A, B, and C that are given in Boolean expression and mark 1 in the output column
• All other outputs in the truth table are 0 • The Boolean expression and the truth table both
accurately describe the operation of the same logic circuit
• The procedure for producing maxterm Boolean expressions from a truth table is quite different
7.10 Simplifying Boolean Expressions
• Consider the Boolean expression, as shown in Figure 22.8(a)
YBABABA =•+•+•
• Constructing a logic circuit for this Boolean expression,
requires three AND gates, two inverters, and one 3-input OR gate, as shown in Figure 22.8(b)
• Figure 22.8(c) details the truth table for the Boolean expression
• The truth table look similiar to the truth table for a 2-input OR gate, with expression YBA =+
• This shows that the Boolean expression YBABABA =•+•+• can be simplified to just the
expression YBA =+ • This saves a lot in terms of the number of gates to be
used to realize the circuit
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Figure 22.8 – Simplifying Boolean expression (a) Unsimplified Boolean expression (b) Complex logic diagram (c) Truth table (d) Simplified Boolean expression: 2-input OR by inspection (e) Simple logic diagram
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7.11 De Morgan’s Theorems
• Boolean algebra, the algebra of logic circuits, has many laws or theorems
• One of the very useful theorem is De Morgan’s theorems
• The theorems allow us to convert back and forth minterm to maxterm forms of Boolean expressions
• The theorems also allow us to eliminate long overbars that cover several variables
• De Morgan’s theorems can be stated in the form shown in Figure 22.9
Figure 22.9 – De Morgan’s theorems and practical examples
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7.12 Minterms-to-Maxterms or Maxterms-to-Minterms
• Four steps are need to convert a maxterm to minterm Boolean expression or from minterm to maxterm form
• The four steps, which are based on De Morgan’s theorems, are as follows:
Step 1. Change all ORs to ANDs and all ANDs to Ors Step 2. Complement each individual variable (add short overbars to each) Step 3. Complement the entire function (add long overbar to entire function) Step 4. Eliminate all groups of double overbars
• Examples of the steps in the conversion are shown in
Figure 22.10 and Figure 22.11
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Figure 22.10 – Four-step process using De Morgan’s second theorem to convert conventional NAND to alternative NAND. Note that the long overbar is eliminated
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Figure 22.11 – Four-step process using De Morgan’s theorems to convert from maxterm-to-minterm form. Note that the long overbar is eliminated
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7.13 Karnaugh Maps
• In 1953 Maurice Karnaugh publish an article about his system of mapping and thus simplifying Boolean expressions
• Figure 23.1 illustrate a Karnaugh map
Figure 23.1 – The meaning of squares in a Karnaugh map
• The four squares (1, 2, 3, 4) represent the four possible
combinations of A and B in a two variable truth table • Square 1 in the Karnaugh map, then, stands for BA • ,
square 2 for BA • , and so forth • For an expression YBABABA =•+•+• , the map is
shown in Figure 23.2
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Figure 23.2 – Marking 1s on a Karnaugh map
• The filled-in Karnaugh map is now ready for looping • The looping technique is shown in Figure 23.3
Figure 23.3 – Looping 1s together on a Karnaugh map
• Adjacent 1s are looped together in groups of two, four, or eight
• Looping continues until all 1s are included inside a loop • Each loop represents a new term in the simplified
Boolean expression
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• Since there are two loops in the table, it means that there are two terms ORed together in the new simplified Boolean expression, as shown in Figure 23.4
Figure 23.4 – Simplifying a Boolean expression from a Karnaugh map
• The summary of the steps to apply the Karnaugh map to simplify a Boolean expressions are as follows:
1. Start with a minterm Boolean expression 2. Record 1s on a Karnaugh map 3. Loop adjacent 1s (loops of two, or four, or eight
squares) 4. Simplify by dropping terms that contain a term and
its complement within a loop 5. OR the remaining terms (one term per loop) 6. Write the simplified minterm Boolean expression
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7.14 Grouping techniques on Karnaugh Map
Figure 23.5 – Grouping techniques
• In Figure 23.5(a), there is no adjacent square of 1s that can be grouped together
• Hence the Boolean expression for this Karnaugh map cannot be further simplified
• In Figure 23.5(b), there are two squares that can be grouped
• These two squares can be considered as adjacent squares when the map is folded along x-axis
• Similarly, the squares of 1s in Figure 23.5(c) and Figure 23.5(d)
• The squares in Figure 23.5(e) are also considered adjacent if the map is folded twice, along x-axis and y-axis
• The more squares in a group the more simple the Boolean expression
• However, it should be noted that the number of squares in a group should be 2, 4, or 8 only
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7.15 Karnaugh Maps with Three Variables
• Consider the unsimplified Boolean expression
YCBACBACBACBA =••+••+••+•• shown in Figure 23.6(a)
Figure 23.6 – Simplifying a Boolean expression using a Karnaugh map (a) unsimplified expression (b) mapping 1s (c) Looping 1s and eliminating variables (d) forming simplified minterm expression
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• A three-variable Karnaugh map is illustrated in Figure
23.6(b) • Notice the eight possible combinations of A, B, and C,
which are represented by the eight squares in the map • The Karnaugh map with loops is redrawn in Figure
23.6(c) • Adjacent groups of two is are looped • The bottom loop contains both a B and B terms are
eliminated • The bottom loop still contains the A and C , giving
CA • term • The upper loop contains both a C and a C and these
are eliminated, leaving the BA • term • A minterm Boolean expression is formed by adding the
OR symbol • The simplified Boolean expression is written in Figure
23.6(d) as
YBACA =•+• 7.16 Karnaugh Maps with Four Variables
• The truth table for four variables has 16 (i.e. 24) possible combinations
• Consider the Boolean expression
YDCBADCBADCBADCBADCBADCBA
=•••+•••+•••+
•••+•••+•••
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• The four-variable Karnaugh map in Figure 23.7(b) gives the 16 possible combinations of A, B, C, and D
• Following the same procedure as before, the simplified Boolean expression is written in Figure 23.7(d) as
YDACBA =•+••
Figure 23.7 – Simplifying a four-variable Boolean expression using a Karnaugh map
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7.17 Don’t Cares on Karnough Map
• The following truth tables are for BCD numbers
(a) (b)
Figure 23.8 – Truth table for BCD numbers
• BCD numbers starting from 0 to 9 is represented by binary numbers 0000 to 1001
• Therefore, binary numbers 1010 to 1111 are not used • These unused combination numbers are called “don’t
cares”
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• Let’s say we want to build a circuit for detecting number 9 in BCD
• For example, when number 9 is met then an LED is lighted
• Thus, the truth table for the circuit is as shown in Figure 23.8(b)
• The unsimplified Boolean expression for the circuit is
YDCBA =•••
• The Karnaugh map for the truth table is as shown in Figure 23.9
• Notice that the “don’t cares” value ar marked as “X” on the Karnaugh map
• For the squares which contain “X” we substitute with 0 or 1 so that we can form group with maximum number of squares (2, 4 or 8 only)
Figure 23.9 – Karnaugh map for the BCD 9 truth table
• Hence, the simplified Boolean expression is
YDA =•
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7.18 – Data Selectors
• Manufacturers of ICs have simplified the job of solving many combinational logic problems by producing data selectors
• A data selector is often a one-package solution to a complicated logic problem
• The data selector actually contains a rather large number of gates packaged inside a single IC
• A 1-of-8 data selector is illustrated in Figure 24.1 • The device has eight data inputs, three data selector
inputs labeled A, B, and C, and one output, labeled W
Figure 24.1 – Logic symbol for a 1-of-8 data selector
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• The basic job the data selector performs is transferring data from a given data input (0 to 7) to the output W
• Which data input is selected is determined by which binary number placed on the data selector inputs
• For example, by giving A = 1, B = 1, and C = 0, data input line 3 is selected and is passed to the output
• Data selector can be used to solve logic problems • Consider the simplified Boolean expression shown in
Figure 24.2(a)
Figure 24.2 – (a) Simplified Boolean expression (b) Logic circuit for Boolean expression
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• A logic circuit for this complicated Boolean expression
is shown in Figure 24.2(b) • Using standard ICs, we probably would have to use
from six to nine IC packages to solve this problem • This would be quite expensive because of the cost of
the ICs and PC board space • A less costly solution to the logic problem is to use a
data selector • The Boolean expression from Figure 24.2(a) is
repeated in truth table form in Figure 24.3
Figure 24.3 – Solving logic problem with a data selector IC
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• A 1-of-16 data selector is added in Figure 24.3 • Notice that logical 0s and 1s are placed at the 16 data
inputs of the data selector corresponding to the truth-table output column Y
• These are permanently connected for this truth table • Data selector inputs (D, C, B, and A) are switched to
the binary numbers on the input side of the truth table • For example, if data selector inputs D, C, B, and A are
at binary 0000, then a logical 1 is transferred to output W of the data selector
• Data selector is used to solve a complicated logic problem
• In this example, we found we needed at least six ICs to solve this logic problem
• Using data selector, we solve this problem by using only one IC
• Data selector seems to be an easy-to-use and efficient way to solve combinational logic problems
• Commonly available data selectors can solve logic problems with three, four, or five variables
• Data selectors are also called multiplexers • The data selector (multiplexer) can be used as a
universal logic element • It is a simple, low-cost solution to many logic problems
with from three to five input variables • Simplified gate circuits and data selector ICs have been
used to implement logic problems • More complex logic problems are created when there
are more variables or when the logic circuit has several outputs
• For these problems, designers can use a programmable array of logic gates within a single IC
• This device is called programmable array logic (PAL)
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• The PAL is based on programmable AND/OR architecture
• These programmable logic devices are available in both TTL and CMOS
• These devices are user programmable • A typical PAL may have 16 inputs and 8 outputs • The generic name for a PAL is programmable logic
device (PLD) 7.19 Programmable Logic Devices (PLDs)
• A programmable logic devices (PLD) is an IC that can be programmed by the user to excecute a complex logic function
• Simple PLDs are used to implement combinational logic • Other more complex PLDs have memory
characteristics (registers) and can be used in the design of sequential logic circuits (such as counters)
• The PLD has many inputs and multiple outputs • The PLD can implement minterm (sum-of-products)
Boolean expressions using AND-OR logic • A simplified version of a programmable logic device is
detailed in Figure 24.4
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Figure 24.4 – Simplified PLD with fuses intact (as from manufacturer)
• The simplified PLD has intact (not blown) fuses used for programming the AND gates
• The OR gate is not programmable in the device • The PLD needs to be programmed by burning open
selected fuses to implement the Boolean expression, e.g. as shown in Figure 24.5
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Figure 24.5 – Simplified PLD with selected fuses burned open to solve logic problem
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7.20 Integrated Circuit (IC) TTL and CMOS
Digital ICs are grouped into various families
These families are group of devices that can be used together
The ICs in a family are said to be compatible and can be easily connected to one another
One group of families is manufactured using bipolar technology
These ICs contains parts comparable to discrete bipolar transistors, diodes, and resistors
Another group of digital IC families uses metal oxide semiconductor (MOS) technology
The CMOS family is a very low power and widely used family using MOS technology
The CMOS ICs contains parts comparable to insulated-gate field-effect transistors (IGFETs)
A traditional type of IC is illustrated in Figure 25.1(a)
This case style is referred to as a dual-in-line package (DIP) by IC manufacturers
This particular IC is called a 14-pin DIP IC
Just counterclockwise from the notch on the IC in Figure 25.1(a) is pin 1
The pins are numbered counterclockwise from 1 to 14 when viewed from the top of the IC
A dot on the top of the DIP IC as in Figure 25.1(b) is another method used to locate pin 1
The smaller micropackages in Figure 25.1(c) and (d) are commonly called surface-mount technology (SMT) packages
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Figure 25.1 -
Figure 25.2 shows an example of the 7400 series of TTL ICs, indicating its pin diagram
This IC contains four 2-input AND gates, and is called a quadruple two-input AND gate
Figure 25.2 – Pin diagram for 7408 digital IC
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Figure 25.3 is a logic diagram using one of the gate in the 7408 IC
Figure 25.3 – Logic diagram for 2-input AND gate circuit
The wiring diagram to implement the 2-input AND function is shown in Figure 25.4
Figure 25.4 - Wiring diagram to implement the 2-input AND function is shown in Figure 25.3
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7.21 Understanding the Marking on Digital TTL ICs
The top of a typical TTL digital IC is shown in Figure 25.5(a)
The block form of the letters “NS” on the top of the IC shows the manufacturer as National Semiconductor
The DM7408N part number can be divided into sections as shown in Figure 25.5(b)
The prefix “DM” is the manufacturer’s code (National Semiconductor uses the letters “DM” as a prefix
The core part number is 7408, which is a quadruple 2-input AND gate TTL IC
This core part number is the same from manufacturer to manufacturer
The trailing letter “N” (the suffix) is a code used by several manufacturers to designate the DIP
Figure 25.5 – (a) Marking on a typical digital IC. (b) Decoding the part number on a typical IC
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The top of another digital IC is shown in Figure 25.6(a)
The letters “SN” on this IC stand for the manufacturer, Texas Instruments
Figure 25.6 – (a) Markings on a Texas Instruments digital IC (b) Decoding the part number of a typical low-power Schottky IC
On this unit, the suffix “J” stands for a ceramic DIP packaging, typically referred to as the commercial grade
The core part number of the IC in Figure 25.6 is 74LS08
This is similar to the 7408 quadruple 2-input AND gate IC manufactured by the National Semiconductor
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The letters “LS” in the center of the core number designate the type of TTL circuitry used in the IC – in this case “LS” stands for low-power Schottky
The internal letter(s) in a core part number of a 7400 series IC tell something about the logic family or subfamily
Typical internal letters used are: AC = FACT Fairchild Advanced CMOS Technology
logic ( a newer advanced family of CMOS) ACT = FACT Fairchild Advanced CMOS Technology
logic ( a newer advanced family of CMOS with TTL logic levels)
ALS = advanced low-power Schottky TTL logic (a sub-family of TTL)
AS = advanced Schottky TTL logic (a sub-family of TTL)
C = CMOS logic (an early family of CMOS) F = FAST Fairchild Advanced Schottky TTL logic
( a new sub-family of TTL) FCT = FACT Fairchild Advanced CMOS Technology
logic (a family of CMOS with TTL logic levels) H = high-speed TTL logic (a sub-family of TTL) HC = high-speed CMOS logic (a family of CMOS) HCT = high-speed CMOS logic (a family of CMOS
with TTL inputs) L = low-power TTL logic (a sub-family of TTL) LS = low-power Schottky TTL logic (a sub-family of
TTL) S = Schottky TTL logic (a sub-family of TTL)
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7.22 Practical CMOS Logic Gates
The older 7400 series of TTL logic devices has been extremely popular for many decades
One of its disadvantages is its higher power consumption
In late 1960s, manufacturers developed CMOS digital ICs which consume little power and were perfect for battery operated electronic devices
CMOS stands for complementary metal oxide semiconductor
Several families of compatible CMOS ICs have been developed
The first was the 4000 series
Next came the 74C00 series and more recently the 74HC00 series of CMOS digital ICs
In 1985, the FACT (Fairchild Advanced CMOS Technology) 74AC00 series, 74ACT00 series, and 74FCT00 series of extremely fast, low-power CMOS digital ICs were introduced by Fairchild
Many large-scale integrated (LSI) circuits such as digital wristwatch and calculator chips are also manufactured using the CMOS technology
7.23 Understanding the Marking on Digital CMOS ICs
A typical 4000 series CMOS IC is shown in Figure 25.7(a)
Note that pin 1 is marked as such on the top of the IC immediately counterclockwise from the notch
The CD4081BE part number can be divided into sections as shown in Figure 25.7(b)
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Figure 25.7 - (a) Marking on a typical CMOS digital IC (b) Decoding the part number on a typical CMOS digital IC
The prefix “CD” is the manufacturer’s code for CMOS digital ICs
The core part number is 4081B, which stands for a CMOS quadruple 2-input AND gate IC
The trailing letter “E” is the manufacturer’s packaging code for plastic DIP IC
The letter “B” is a “buffered version” of the original 4000A series
The buffering provides the 4000B series devices with greater output drive and some protection from static electricity
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Figure 25.8 shows pin diagram for the CD4081BE CMOS quad 2-input AND gate IC
Figure 25.8 – Pin diagram for the 4081B CMOS IC
Figure 25.9 shows an example of logic diagram for a 2-input AND gate circuit
Figure 25.9 – An example of logic diagram for a 2-input AND gate circuit
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Figure 25.10 shows the wiring diagram using the 4081B CMOS IC
Figure 25.10 - Wiring diagram using the 4081B CMOS IC
A 5 V dc power supply is shown but the 4000 series CMOS IC can use voltages from 3 to 18V dc
Care is taken in removing the 4081 from its conductive foam storage because CMOS ICs can be damaged by static charges
Do not touch the pins when inserting the 4081 CMOS IC in a socket or mounting board
VDD and VSS power connection should be made with the power off
When using CMOS, all unused inputs are tied to GND or VDD
In this example, unused inputs (C, D, E, F, H, G) are grounded
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7.24 Integrated Circuit (IC) Specifications
Integrated circuits within a logic family are designed to interface easily with one another
For example, in the TTL logic family, an output of a TTL device can be connected directly to the input of several other TTL inputs with no extra parts
ICs from the same logic family will interface properly
Interfacing between logic families and between digital ICs and the outside world is a bit more complicated
Interfacing can be defined as the design of the interconnections between circuits that shift the levels of voltage and current to make them compatible
7.24.1 TTL Logic Levels
Figure 26.1 defines the input and output voltage levels for a typical TTL inverter
Figure 26.1 – Defining TTL input and output voltage levels
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For TTL ICs, a LOW input must range from GND to 0.8V
Also a HIGH input must be in the range from 2.0 to 5.5V
The unshaded section from 0.8V to 2.0V on the input side is the undefined area, or undeterminate region
Inputs in the undefined region yield unpredictable results at the output
An output in the range of GND and 0.4V is defined as LOW, while in the range 2.4V to 5.5V is HIGH
The HIGH output depends on the the resistance value of the load placed at the output
The greater the load current, the lower the HIGH output voltage
The unshaded section of the output voltage side in Figure 26.1 is the undefined region
Suspect trouble if the output voltage is in the undefined region (0.4V to 2.4V)
7.24.2 CMOS Logic Levels
The 4000 and 74C00 series CMOS logic families of ICs operate on a wide range of power supply voltages (from +3V to +15V)
The definition of a HIGH and LOW logic level for a typical CMOS inverter from the 4000 and 74C00 series is illustrated in Figure 26.2(a)
A 10-V power supply is being used in this voltage profile diagram
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Figure 26.2 – Defining CMOS input and output voltage levels (a) 4000 and 74C00 series with voltage profile (b) 74HC00, 74AC00 and 74ACQ00 series voltage profile (c) 74HCT00, 74ACT00, 74ACTQ00, 74FCT00, 74FCTA00 series voltage profile
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The CMOS inverter shown in Figure 26.2(a) will respond to any input voltage within 70 – 100 percent of VDD (+10V in this example) as a HIGH
Likewise, any voltage within 0 to 30 percent of VDD is regarded as a LOW input to ICs in the 4000 and 74C00 series
Output voltages are normally almost at the voltage rails of the power supply
In this example, a HIGH output would be about +10V while a LOW output would be about 0V and GND
The 74HC00 series and the newer 74AC00 and 74ACQ00 series operate on a lower voltage power supply (from +2V to +6V) than the older 4000 and 74C00 series CMOS ICs
The input and output voltage characteristics are summarized in the voltage profile diagram in Figure 26.2(b)
The definition of HIGH and LOW for both input and output on the 74HC00, 74AC00, and 74ACQ00 series is approximately the same as for the 4000 and 74C00 series CMOS ICs
The 74HCT00 series and the newer 74ACT00, 74ACTQ00, 74FCT00 and 74FCTA00 series of CMOS ICs are designed to operate on a 5-V power supply like TTL ICs.
The function of the 74HCT00, 74ACT00, 74ACTQ00, 74FCT00 and 74FCTA00 series of CMOS ICs is to interface between TTL and CMOS devices
These CMOS ICs with a “T” designator can serve as direct replacements for many TTL ICs
The voltage profile diagram for the 74HCT00, 74ACT00, 74ACTQ00, 74FCT00 and 74FCTA00 series of CMOS ICs is shown in Figure 26.2(c)
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7.24.3 Noise Margin
Noise immunity is a circuit’s insensitivity or resistance to undesired voltages or noise
In digital circuits it is called noise margin
The noise margins for typical TTL and CMOS families are compared in Figure 26.3
Figure 26.3 – Defining and comparing TTL and CMOS noise margin
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The noise margin is much better for the CMOS than for the TTL family
Noise in a digital system is unwanted voltages induced in the connecting wires and printed circuit board traces that might affect the input logic levels, thereby causing faulty output indications
Figure 26.4 defines the LOW, HIGH, and the undefined regions for TTL inputs
Figure 26.4 – TTL input logic levels showing noise margin
If the actual input voltage is 0.2V, then the margin of safety between it and the undefined region is 0.6V (0.8V – 0.2V = 0.6V), i.e. the noise margin
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In other words, it would take more than +0.6V added to the LOW voltage (0.2V in this example) to move the input into the undefined region
In actual practice, the noise margin is even greater because the voltage must increase to the switching threshold, which is shown as 1.2V in Figure 26.4
With the actual LOW input +0.2V and the switching threshold at about +1.2V, the actual noise margin is 1V (i.e. 1.2V – 0.2V = 1.0V)
7.24.4 Drive Capabilities – Fan-in and Fan-out
A bipolar transistor has its maximum wattage and collector current ratings
These ratings determine its drive capabilities
One indication of output drive capability of a digital IC is called its fan-out
The fan-out of a digital IC is the number of “standard” inputs that can be driven by the gate’s output
If the fan-out for standard TTL gates is 10, this means that the output of a single gate can drive up to 10 inputs of the gates in the same subfamily
A typical fan-out value for standard TTL ICs is 10. The fan-out for low-power Schottky TTL (LS-TTL) is 20 and for the 4000 series CMOS is considered to be about 50
Another way to look at the current characteristics of gates is to examine their output drive and input loading parameters
Figure 26.5 shows a simplified view of the output drive capabilities and input load characteristics of a standard TTL gate
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Figure 26.5 – Standard TTL voltage and current profiles
A standard gate is capable of handling 16 mA when the
output is LOW (IOL) and 400 A when the output is HIGH (IOH)
The input loading (worst-case condition) is only 40 A with the input HIGH (IIH) and 1.6mA when the input is LOW (IIL)
This means that the output of a standard TTL gate can drive 10 inputs (16mA/1.6mA = 10)
A summary of the output drive and input loading characteristics of several popular families of digital ICs is detailed in Figure 26.6
The load represented by a single gate is called the fan-in of that family of ICs
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Figure 26.6 – Output drive and input loading characteristics for selected TTL and CMOS logic families
Suppose it is required to know if the 74LS04 inverter has enough fan-out to drive the four standard TTL NAND gates on the right as shown in Figure 26.7
The voltage and current profiles for LS-TTL and standard TTL gates are sketched in Figure 26.8
The voltage characteristics of all TTL families are compatible
The LS-TTL gate can drive 10 standard TTL gates
when its output is HIGH (400 A/40 A = 10)
However, the LS-TTL gate can drive only five standard TTL gates when it is LOW (8mA/1.6mA = 5)
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Thus, the fan-out of LS-TTL gates is only 5 when driving standard TTL gates
It is true that the LS-TTL inverter can drive four standard TTL inputs in Figure 26.7
Figure 26.7 – Interfacing LS-TTL to standard TTL problem. Logic diagram of interfacing problem
Figure 26.8 – Voltage and current profiles for LS-TTL and standard TTL gates
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7.24.5 Propagation Delay
Speed, or quickness of response to a change at the inputs, is an important consideration in high-speed applications of digital ICs
Consider the waveforms in Figure 26.9
Figure 26.9 – Propagation delays for a standard TTL inverter
The top waveform shows the input to an inverter going from LOW to HIGH and then from HIGH to LOW
The bottom waveform shows the output response to the changes at the input
The slight delay between the time the input changes and the time the output changes is called the propagation delay of the inverter (measured in seconds)
The propagation delay delay for the LOW-to-HIGH transition of the input to the inverter is different from the HIGH-to-LOW delay
Propagation delays for selected TTL and CMOS families are shown in Figure 26.10
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Figure 26.10 – Graph of propagation delays for selected TTL and CMOS
7.24.6 Power Dissipation
Generally, as propagation delays decrease (increased speed), the power consumption and related heat generation increase
Historically, a standard TTL IC might have a propagation delay of about 10 ns compared with a propagation delay of about 30 to 50 ns for a 4000 series CMOS IC.
The 4000 CMOS IC, however, would consume only 0.001 mW, while standard TTL gate might consume 10 mW of power
The power consumption of CMOS increases with frequency
At 100 kHz, the 4000 series gate may consume 0.1 mW of power
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Figure 26.11 shows a graph of speed versus power of several modern TTL and CMOS families
Figure 26.11 – Speed versus power for selected TTL and CMOS families
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7.25 Interfacing Digital ICs 7.25.1 Interfacing TTL and CMOS with Switches
One of the most common means of entering information into a digital system is the use of switches or a keyboard
Figure 27.1 shows simple active-LOW switch-to-TTL interfaces
Figure 27.1 - Simple active-LOW switch-to-TTL interfaces
Pressing the push-button switch in this circuit will drop the input of the TTL inverter to ground level or LOW
Releasing the push-button switch opens the switch
The input to the TTL inverter now is allowed to “float”
In TTL, inputs usually float at a HIGH logic level
Floating inputs on TTL are not dependable
Figure 27.2 is a slight refinement of the switch input circuit
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Figure 27.2 – Active-LOW switch interface using pull-up resistor
The 10 k resistor, called pull-up resistor, has been added to make sure the input to the TTL inverter goes HIGH when the switch is open
Its purpose is to pull the input voltage up to +5V
Circuits in Figure 27.1 and Figure 27.2 illustrate active-LOW switches
They are called active-LOW switches because the inputs go LOW only when the switch is activated
Figure 27.3 illustrate an active-HIGH input switch
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Figure 27.3 – Active-HIGH switch interface using pull-down resistor
In the active-HIGH switch circuit, when the input switch is activated, the +5V is connected directly to the input of the TTL inverter
When the switch is released (opened) the input is pulled LOW by the pull-down resistor
The value of the pull-down resistor is relatively low because the input current required by a standard TTL gate may be as high as 1.6 mA
Figure 27.4 illustrates an active-LOW input switch-to-CMOS interface circuit
The 100 k pull-up resistor pulls the voltage to +5V when the input switch is open
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Figure 27.4 – An active-LOW switch-to-CMOS interface with pull-up resistor
Figure 27.5 illustrates an active-HIGH switch feeding a CMOS inverter
The 100 k pull-down resistor makes sure the input to the CMOS inverter is near ground when the input switch is open
Figure 27.5 – An active-HIGH switch-to-CMOS interface with pull-down resistor
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The resistance value of the pull-up and pull-down resistors is much greater than those in TTL interface circuits because the input loading currents are much greater in TTL than in CMOS
7.25.2 Switch Debouncing
When a switch is pressed, it will bounce several times
If the switch is interfaced to a decimal counter system, as shown in Figure 27.6, each press of the input switch should cause the decade counter to increase by 1
Figure 27.6 – Switch without debouncing circuit being interfaced to a decimal counter system
However, in practice each press of the switch increases the count by 1, 2, 3, or sometimes more
This means that several pulses are being fed into the clock (CLK) input of the counter each time the switch is pressed
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Figure 27.7 shows the switch that has been added with a debouncing circuit to make the decimal counter work properly
Figure 27.7 – Adding a debouncing circuit to make the decimal counter work properly
The decade counter will now count each HIGH-LOW cycle of the input switch
The cross-coupled NAND gates in the debouncing circuit are sometimes called the RS flip-flop or latch
Several other switch debouncing circuits are illustrated in Figure 27.8 to Figure 27.10
Figure 27.8 – A 4000 series switch debouncing circuit
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The simple debouncing circuit in Figure 27.8 will work on the slower 4000 series CMOS IC
The 40106 CMOS IC is a special inverter called Schmitt trigger inverter, which means it has a “snap action” when changing to either HIGH or LOW
A Schmitt trigger can also change a slow-rising signal (such as a sine wave) into a square wave
The switch debouncing circuit in Figure 27.9 will drive 4000, 74HC00, or FACT series CMOS or TTL ICs
Figure 27.9 – General purpose switch debouncing circuit that will drive CMOS or TTL inputs
Another general purpose switch debouncing circuit is illustrated in Figure 27.10
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Figure 27.10 – Another general purpose switch debouncing circuit that will drive CMOS or TTL inputs
This debouncing circuit can drive either CMOS or TTL inputs
The 7403 is an open-collector NAND TTL IC and needs pull-up resistors as shown in Figure 27.10
The external pull-up resistors make it possible to have an output voltage of just about +5V for HIGH
Open-collector TTL gates with external pull-up resistors are useful when driving CMOS with TTL
7.25.3 Interfacing TTL and CMOS with LEDs
LED can be used as an input indicator because it operates at low currents and voltages
The maximum current required by many LEDs is about 20 to 30 mA with about 2V applied
An LED will light dimly on only 1.7V to 1.8V and 2 mA
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CMOS-to-LED Interfacing
Interfacing 4000 series CMOS devices with simple LED indicator lamps is easy
Figure 27.11(a) and (b) show the CMOS supply voltage at +5V, and thus no limiting resistors are needed in series with the LEDs
Figure 27.11 – Simple CMOS-to-LED interfacing (a) CMOS active-HIGH (b) CMOS active-LOW
In Figure 27.11(a), when the output of the CMOS inverter goes HIGH, the LED output indicator lights
The opposite is true in Figure 27.11(b): when the CMOS output goes LOW, the LED indicator lights
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Figure 22.12(a) and (b) show the 4000 series CMOS ICs being operated on a higher supply voltage (+10V to +15V)
Figure 27.12 – Simple CMOS-to-LED interfacing (a) CMOS active-HIGH, supply voltage = 10V to 15V (b) CMOS active-LOW, supply voltage = 10V to 15V
Because of the higher voltage, a 1 k limiting resistor is placed in series with the LED output indicator lights
When the output of the CMOS inverter in Figure 27.12(a) goes HIGH, the LED output indicator lights
In Figure 27.12(b), however, the LED indicator is activated by a LOW at the CMOS output
Figure 27.13(a) and (b) show CMOS buffers being used to drive LED indicators
The circuit may operate on voltages from +5V to +15V
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Figure 27.13 – Simple CMOS-to-LED interfacing (a) CMOS inverting buffer to LED interfacing (b) CMOS non-inverting buffer to LED interfacing
Figure 27.13(a) shows the use of an inverting CMOS buffer (like the 4049 IC), while Figure 27.13(b) uses the non-inverting buffer (like the 4050 IC)
In both cases, a 1 k limiting resistor must be placed in series with the LED output indicator
TTL-to-LED Interfacing
Standard TTL gates are sometimes used to drive LEDs directly, as shown in Figure 27.14(a) and (b)
Figure 27.14 – Simple TTL-to-LED interfacing (a) TTL active-HIGH (b) TTL active-LOW
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When the output of the inverter in Figure 27.14(a) goes HIGH, current will flow through the LED causing it to light
The indicator light in Figure 27.14(b) only lights when the output of the 7404 inverter goes LOW
Circuits in Figure 27.11 to Figure 27.14 are not recommended for critical uses because they exceed the output current ratings of the ICs
However, the circuits have been tested and work properly as simple output indicators
Current Sourcing and Current Sinking
The idea of current sourcing and current sinking can be illustrated by using the circuits shown in Figure 27.15
Figure 27.15 (a) Current sourcing (b) Current sinking
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In Figure 27.15(a) the output of the TTL AND gate is HIGH and lights the LED
In this case the IC is said to be the source of current (conventional current flow from + to -)
The sourcing current is sketched on the schematic diagram in Figure 27.15(a)
The source current appears to “flow from the IC” through the external circuit (LED and limiting resistor) to ground
In Figure 27.15(b) the output of the TTL NAND gate is LOW
This LOW at the output of the NAND gate lights the LED
In this case, the IC is referred to as sinking the current
The sinking current is sketched on the schematic diagram in Figure 27.15(b)
The sinking current appears to start with +5V above the external circuit (limiting resistor and LED) and “sink to ground” through the external circuit (limiting resistor and LED) and the output pin of the NAND IC
Interfacing to LED Using Transistor Drive Circuit
The LED output indicator circuits can be improved by using transistor drivers
The improved circuit can be used with either CMOS or TTL
The LED in Figure 27.16 lights when the output of the inverter goes HIGH because this will turn on the transistor and the collector current flows from the supply through LED and the limiting resistor
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Figure 27.16 – Interfacing to LED using a transistor driver circuit. Active-HIGH output using a NPN transistor driver
The LED in Figure 27.17 lights when the output of the inverter goes LOW because this will turn on the transistor and the emitter current flows from the supply through LED and the limiting resistor
Figure 27.17 – Interfacing to LED using a transistor driver circuit. Active-LOW output using a PNP transistor driver
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Figure 27.18 is a combination of the active-HIGH and active-LOW LED indicator circuits
Figure 27.18 – Interfacing to LED using a transistor driver circuit. HIGH-LOW indicator circuit
The red LED will light when the inverter’s output is HIGH (during this time the green LED will be off)
When the output of the inverter goes LOW, transistor Q1 turns off while transistor Q2 turns on
This causes the green LED light up and the red LED goes off
This circuit is a very basic logic probe, but the accuracy is less than most logic probes
The indicator light shown in Figure 27.19 uses an incandescent lamp
When the output of the inverter goes HIGH, the transistor is turned on and the lamp lights
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When the inverter’s output is LOW, the lamp does not light
Figure 27.19 – Interfacing to an incandescent lamp using a transistor driver circuit
7.25.4 Interfacing with Buzzers, Relays, Motors and
Solenoids
The objective of many electromechanical systems is to control a simple output device
This device might be as simple as a light, buzzer, relay, electric motor, stepper motor, or solenoid
Interfacing with Buzzers
The piezo buzzer is a modern signaling device drawing much less current than older buzzers and bells
A standard TTL or FACT CMOS inverter is shown in Figure 27.20 driving a piezo buzzer directly
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Figure 27.20 – Logic device to buzzer interfacing. Standard TTL or FACT CMOS inverter driving a piezo buzzer directly
Standard TTL output can sink up to 16 mA while a FACT output has 24 mA of drive current
The piezo buzzer draws about 3 to 5 mA when sounding
Notice that the piezo buzzer has polarity markings
The diode across the buzzer is to suppress any transient voltages that might be induced in the system by the buzzer
Most logic families do not have the current capacity to drive a buzzer directly
A transistor has been added to the output of the inverter in Figure 27.21 to drive the piezo buzzer
When the output of the inverter goes HIGH the transistor is turned on and the buzzer sounds
A LOW at the output of the inverter turns the transistor off, switching the buzzer off
The diode protects against transient voltages
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The interface circuit shown in Figure 27.21 will work for both TTL and CMOS
Figure 27.21 – Logic device to buzzer interfacing. TTL or CMOS interfaced with buzzer using a transistor driver
Interfacing Using Relays
A relay is an excellent method of isolating a logic device from a high-voltage circuit
Figure 27.22 shows how a TTL or CMOS inverter could be interfaced with a relay
When the output of the inverter goes HIGH, the transistor is turned on and the relay is activated
When activated, the normally open (NO) contact of the relay close as the armature clicks downward
When the output of the inverter goes LOW, the transistor stops conducting and the relay is deactivated
The armature springs upward to its normally closed (NC) position
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The clamp diode across the relay coil prevents voltage spikes which might be induced in the system
Figure 27.22 – TTL or CMOS interfaced with a relay using a transistor driver circuit
The circuit in Figure 23.24 uses a relay to isolate an electric motor from the logic devices
Notice that the logic circuit and dc motor have separate power supplies
When the output of the inverter goes HIGH, the transistor is turned on and the NO contacts of the relay snap closed, causing the motor to operate
When the output of the inverter goes LOW, the transistor stops conducting and the relay contacts spring back to their NC position, turning the motor off
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Figure 27.23 – Using a relay to isolate higher voltage/current circuits from digital circuits. Interfacing TTL or CMOS with an electric motor
A solenoid is an electrical device that can produce linear motion
Figure 22.24 shows a solenoid being driven by a logic gate
Note the separate power supplies
This circuit works the same as the motor interface in Figure 27.23
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Figure 27.24 – Using a relay to isolate higher voltage/current circuits from digital circuits. Interfacing TTL or CMOS with a solenoid
In summary, voltage and current characteristics of most buzzers, relays, electric motors, and solenoids are radically different from those of logic circuits
Most of these electrical devices need special interfacing circuits to drive and isolate the devices from the logic circuits
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8 SEQUENTIAL LOGIC CIRCUITS 8.0 Introduction
Logic circuits can be classified into two groups, i.e. combinational logic circuits and sequential logic circuits
So far we have learnt combinational logic circuits using AND, OR and NOT gates
The basic building block for combinational logic circuits is the logic gates
Sequential logic circuits involved timing and memory devices
The basic building block for sequential logic circuits is the flip-flop (FF)
There are several types of FF, i.e. RS flip-flops, D flip-flop-flops and JK flip-flops
Flip-flops can be wired to form counters, shift registers and various memory devices
8.1 The RS Flip-Flop
The logic symbol for RS FF is shown in Figure 28.1
Figure 28.1 – Logic symbol for an RS FF
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Notice that the RS FF has two inputs, labeled S and R
The two output are labeled Q and Q
In FF the outputs are always opposite, or complementary
In other words, if 1Q , then 0Q , and so on
The two letters “S” and “R” at the inputs of the RS FF are often reffered to as the set and reset inputs
Figure 28.2 is the truth table that details the operation of the RS FF
Figure 28.2 – Truth table for RS FF
Notice that when the S and R inputs are both 0, both outputs go to a logical 1
This is called a prohibited state for FF and is not used
The second line of the truth table shows that when input S is 0 and R is 1, the Q output is set to logical 1 – this is called the set condition
The third line shows that when R is 0 and S is 1, output Q is reset (cleared) to 0 – this is called the reset condition
Line 4 in the truth table shows both inputs (R and S) at 1
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This is the idle or at rest condition and leaves Q and Q at their previous complementary states – this is called the hold condition
Notice that the FF in Figure 28.1 has invert bubbles at the R and S inputs
This invert bubbles indicate that the set and reset inputs are activated by a logical 0
RS FFs can be purchased in an IC package, or they can be wired from logic gates such as the NAND gates, as shown in Figure 28.3
Figure 28.3 – Wiring the RS FF using NAND gates Timing Diagrams
Timing diagrams or waveforms show the voltage level and timing between inputs and outputs and are similar to what would be observed on an oscilloscope
The horizontal axis of the diagram is time and the vertical axis is voltage
Figure 28.4 shows the input waveforms (R and S) and
the output waveforms (Q and Q ) for the RS FF
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Figure 28.4 – Waveform diagrams for an RS FF 8.2 The Clocked RS Flip-Flop
The logic symbol for a clocked RS FF is shown in Figure 28.5
Figure 28.5 – Logic symbol for a clocked RS FF
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It looks almost like an RS FF except that it has one extra input labelled CLK (for clock)
The timing diagram for the operation of the clocked RS FF is shown in Figure 28.6
Figure 28.6 – Waveform diagram for a clocked SR FF
Notice that the clock pulse (1) has no effect on output Q with input S and R in the 0 position
The flip-flop is in the idle, or hold mode during clock pulse 1
At the preset S position, the S (set) input is moved to 1, but output Q is not yet set to 1
The rising edge of clock pulse 2 permits Q to go to 1
Pulse 3 and 4 have no effect on output Q
During pulse 3 the flip-flop is in its set mode, while during pulse 4 it is in its hold mode
Next, input R is preset to 1
On the rising edge of clock pulse 5 the Q output is reset (or cleared) to 0
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The flip-flop is in the reset mode during both clock pulses 5 and 6
The flip-flop is in its hold mode during clock pulse 7; therefore, the normal output (Q) remains at Q
Notice that the outputs of the clocked RS FF change only on a clock pulse
The flip-flop is said to operate synchronously; it operates in step with the clock
Synchronous operation is very important in most digital circuits, where each step must happen in an exact order
Another characteristics of the clocked RS FF is that once it is set or reset it stays that way even if some inputs is changed
This is a memory characteristic, which is extremely valuable in many digital circuits
In waveform diagram in Figure 28.6, this flip-flop is in the hold mode during clock pulses 1, 4, and 7
Figure 28.7 shows a truth table for the clocked RS FF
Figure 28.7 – Truth table for a clocked RS FF
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Notice that only the top three lines of the truth table are usable; the bottom line is prohibited and not used
Observe that the R and S inputs to the clocked RS FF are active HIGH inputs – it takes a HIGH on input S while R = 0 to cause output Q to be set to 1
Figure 28.8 shows a wiring diagram of a clocked RS FF
Notice that two NAND gates have been added to the inputs of the RS FF to add the clocked feature
Figure 28.8 – Wiring a clocked RS FF using NAND gates
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8.3 The D Flip-Flop
Figure 28.9(a) shows the logical symbol for a D FF
It has only one data input (D) and a clock input (CLK)
The outputs are labeled Q and Q
Figure 28.9 – D FF (a) Logic symbol (b) Simplified truth table
The D FF is often called a delay flip-flop
The word “delay” describes what happens to the data, or information, at input D
The data (a 0 or 1) at input D is delayed one clock pulse from getting to output Q
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A simplified truth table for the D FF is shown in Figure 28.9(b)
Notice that the output Q follows input D after one clock pulse (see Qn+1 column)
A D FF may be formed from a clocked RS FF by adding an inverter, as shown in Figure 28.10
Figure 28.10 – Wiring a D flip-flop
Figure 28.11 shows a typical commercial D FF
Two extra inputs preset, (PS) and clear (CLR) have been added to the D FF
Figure 28.11 – Logic symbol for commercial D FF
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The PS input sets output Q to 1 when enabled by a logical 0
The CLR input clears output Q to 0 when enabled by a logical 0
The PS and CLR inputs will override the D and CLK inputs
Note the addition of the triangle on the CLK input in Figure 28.11
A more detailed truth table for the commercial 7474 TTL D FF isshown in Figure 28.12
Figure 28.12 – The truth table for 7474 D FF
The asynchronous (not synchronous) inputs (PS and CLR) override the synchronous inputs
The asynchronous inputs are in control of the D FF in the first three lines of the truth table
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The synchronous inputs D and CLK are irrelevant as shown by the “X”s on the truth table
The prohibited condition, line 3 on the truth table should be avoided
With both asynchronous inputs disabled (PS = 1 and CLR = 1), the D FF can be set and reset using the D and CLK inputs
The last two lines of the truth table use a clock pulse to transfer data from input D to output Q of the flip-flop
Being in step with the clock, this is called synchronous operation
Note that this flip-flop uses the LOW-to-HIGH transition of the clock pulse to transfer data from input D to output Q
D FF are sequential logic devices which are widely used temporary memory devices
D FF are wired together to form shift registers and storage registers
Since the D FF delays data from reaching the output Q one clock pulse, it is called a delay flip-flop
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8.4 The JK Flip-Flop
The JK FF has the features of all the other types of flip-flops
The logic symbol for the JK FF is illustrated in Figure 28.13
Figure 28.13 – Logic symbol for JK flip-flop
The inputs lebelled J and K are the data inputs
The input labeled CLK is the clock input
Outputs Q and Q are the usual normal and complementary outputs on a flip-flop
A truth table for the JK FF is shown in Figure 28.14
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Figure 28.14 – Truth table for JK FF
When the J and K inputs are both 0, the flip-flop is in the hold mode
In the hold mode the data inputs have no effect on the outputs – the outputs “hold” the last data present
Line 2 and 3 of the truth table show the reset and set conditions for the Q output
Line 4 illustrates the useful toggle position of the JK FF
When both data inputs J and K are at 1, repeated clock pulses cause the output to turn off-on-off-on-off-on, and so on
This off-on action is like a toggle switch and is called toggling
Figure 28.15 shows the logic symbol for the commercial 7476 TTL JK FF
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Figure 28.15 – Logic symbol for commercial JK FF
Added to the symbol are two asynchronous inputs, preset (PS) and clear (CLR)
The synchronous inputs are the J and K data and clock inputs
A detailed truth table for the commercial 7476 JK FF is shown in Figure 28.16
Recall that asynchronous inputs, such as preset (PS) and clear (CLR) override synchronous inputs
The asynchronous inputs are activated in the first three lines of the truth table
The asynchronous inputs are activated in the first three lines of the truth table
The synchronous inputs are irrelevant (overriden) in the first three lines in Figure 28.16; therefore an “X” is placed under the J, K, and CLK inputsfor these rows
The prohibited state occurs when both asynchronous inputs are activated at the same time
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Figure 28.16 – Truth table for commercial 7476 JK FF
The prohibited state is not useful and should be avoided
When both asynchronous inputs (PS and CLR) are disabled with a 1, the synchronous inputs can be activated
The bottom four lines of the truth table in Figure 28.16 detail the hold, reset, set, and toggle modes of operation for the 7476 JK FF
Note that the 7476 JK FF uses the entire pulse to
transfer data from the J and K inputs to the Q and Q outputs
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8.5 Latches
There are three types of multivibrators – monostable multivibrators, astable multivibrators, and bistable multivibrators
The RS FF is one of several bistable multivibrators
The RS FF is most commonly known as a latch
A latch is a fundamental binary memory device for holding data
Latches are commonly used at the output of a digital device to hold the data until the next device is ready to receive the input
Latches are commonly organized into groups of 4-bits, 8-bits or more into registers
An 8-bit register would be a group of eight latches holding a byte of information
An example of commercial RS flip-flop IC is 74LS279 Quad SR Latch IC
8.5.1 IC Latches
Figure 29.1 shows an electronic encoder/decoder system without buffer memory
Figure 29.1 - An electronic encoder/decoder system without buffer memory
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In this system, when the decimal 7 on the keyboard is pressed and hold, a 7 will be observed on the seven-segment display
If the 7 on the keyboard is released, the 7 on the display will disappear
It is obvious that a memory device is needed to hold the BCD code for 7 at the inputs to the decoder
A device that serves as a temporary buffer memory is called a latch
Figure 29.2 shows a 4-bit latch has been added to the system
Figure 29.2 - An electronic encoder/decoder system with buffer memory (latch) added
In this modified system, when the decimal 7 on the keyboard is pressed and released, the seven-segnent display continues to show a 7
The term “latch” refers toa digital storage device
The D FF is a good example of device used to latch data
However, other types of flip-flops are also used for latching function
An example of commercial IC latches is the 7475 TTL 4-bit transparent latch, as shown in Figure 29.3
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Figure 29.3 – Logic symbol for commercial 7475 4-bit transparent latch
This unit has four D FF enclosed in a single IC package
The enable input (E0-1) is similar to the clock input on the D FF
When E0-1 is enabled, both D0 and D1 are transferred to their outputs
A simplified truth table for the 7475 latch IC is shown in Figure 29.4
Figure 29.4 – Truth table for 7475 D latch
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If the enable input is at a logical 1, data is transferred, without a separate clock pulse, from D input to the Q
and Q outputs
As an example, if E0-1 = 1 and D1 =1, then without a
clock pulse output Q1 will be set to 1 while 1Q would be
reset to 0
In the data-enabled mode of operation the Q outputs follow their respective D inputs on the 7475 latch
When the enable input drops to 0, the 7475 IC enters the data-latched mode
In this mode, the data that was at Q remains the same even if the D inputs change – the data is said to be latched
The 7475 IC is called a transparent latch because when enable input is HIGH, the normal outputs follow the data at the D inputs
Note that the D0 and D1 flip-flops in the 7475 IC are controlled by the E0-1 enable input whereas the E2-3 controls the D2 and D3 pairs of flip-flops
Other than its use as a latch, flip-flops can also be used as counters, shift registers, delay units, and frequency dividers
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8.6 Triggering Flip-Flops
Flip-flops can be classified as synchronous or asynchronous in their operation
Synchronous flip-flops are those that have a clock input
The clocked RS, the D, and the JK flip-flop operate in step with the clock
Synchronous flip-flops are also classified as either edge-triggered or master/slave
Figure 29.5 shows two edge-triggered flip-flops in the toggle position
Figure 29.5 – Waveforms for positive- and negative-triggered flip-flops
On clock pulse 1 the positive edge (positive-going edge) of the pulse is identified
The second waveform shows how the positive-edge triggered flip-flop toggles each time a positive-going pulse comes along (see pulses 1 to 4)
On pulse 1 in Figure 29.5 the negative edge(negative-going edge) of the pulse is also labeled
The bottom waveform shows how the negative-edge-triggered flip-flop toggles
Notice that it changes state, or toggles, each time a negative-going pulse comes along (see pulses 1 to 4)
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Especially notice the difference in timing between the positive- and negative-edge triggered flip-flops
Figure 29.6(a) shows the logic symbol of a D FF with positive-edge triggering
The symbol uses the small > inside the flip-flop near the clock input
This > symbol says data is transferred to the output on the edge of the pulse
Figure 29.6 – (a) Logic symbol for positive-edge triggered D FF (b) Logic symbol for negative-edge triggered D FF (c) Logic symbol for D latch
A logic symbol for a D FF using negative-edge triggering is shown in Figure 29.6(b)
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The added invert bubble at the clock input shows that triggering occurs on the negative-going edge of the clock pulse
A typical D latch symbol is shown in Figure 29.6(c)
The lack of a > symbol next to the enable (similar to a clock) input means that this unit is not considered an edge-triggered unit
Like the RS FF, the D latch is considered asynchronous
The JK master/slave flip-flop uses the entire pulse (positive edge and negative edge) to trigger the flip-flop
Figure 29.7 shows the triggering of a master/slave flip-flop
Figure 29.7 – Triggering the JK master/slave FF
Pulse 1 shows four positions (a to d) on the waveform
The following sequences of operation takes place in the master/slave flip-flop at each point on the clock pulse: o Point a: leading edge – isolate input from output o Point b: leading edge – enter information from J
and K inputs o Point c: trailing edge – disable J and K inputs o Point d: trailing edge – transfer information from
input to output
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8.7 Schmitt Trigger
Digital circuits prefer waveforms with fast rise and fall times
Schmitt trigger can be used to reshape or condition the input signal and make the rise and fall times of the signal very fast (almost instantaneous)
Figure 29.8 shows a Schmitt trigger inverter is being used to “square up” the input signal and make it more useful
Figure 29.8 – Schmitt trigger used for wave shaping
A voltage profile of a typical TTL inverter (7404 IC) is shown in Figure 29.9
Of special interest is the switching threshold of the 7404 IC
Figure 29.9 – TTL voltage profiles with switching threshold
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The switching threshold may vary from chip to chip, but it is always in the undefined region
Figure 29.9 shows that a typical 7404 IC has a switching threshold of +1.2 V
In other words, when the voltage rises to +1.2 V, the output changes from HIGH to LOW
However, if the voltage drops below +1.2 V, the output switches from LOW to HIGH
Most regular gates have a single switching threshold voltage whether the input voltage is rising (L to H) or falling (H to L)
A voltage profile for a 7414 Schmitt trigger inverter TTL IC is shown in Figure 20.10
Figure 29.10 – Voltage profiles for 7414 TTL Schmitt trigger IC showing switching thresholds
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Note that the switching threshold is different for positive-going (V +) and negative-going (V -) voltages
The voltage profile for the 7414 IC shows that the switching threshold is 1.7 V for a positive-going (V +) input voltage.
However, the switching threshold is 0.9 V for a negative-going (V -) input voltage
The difference between these swiching thresholds (1.7 V and 0.9 V) is called hysteresis
Hysteresis provides for excellent noise immunity and helps the Schmitt trigger square up wave form with slow rise and fall time
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9.0 Counters
Almost any complex digital system contains several counters
A counter’s job is the obvious one of counting events or periods of time or putting events into sequence
Other application of counters include dividing frequency, addressing, and serving as memory units
Flip-flops can be wired together to form circuits that counts
Because of the wide use of counters, manufacturers also make self-contained counters in IC form
Many counters are available in all TTL and CMOS families
Some counter ICs contain other devices such as signal conditioning circuitry, latches and display multiplexers
9.1 Ripple Counters
Figure 30.1 illustrate the counting in binary and decimal
With four binary places (D, C, B, and A) the count is from 0000 to 1111 (0 to 15 in decimal)
If it is required to design a counter to count from binary 0000 to 1111, a device that has 16 different output states: a modulo (mod)-16 counter is needed
The modulus of a counter is the number of different states the counter must go through to complete its counting cycle
A mod-16 counter using four JK FF is diagramed in Figure 30.2
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Figure 30.1 – Counting sequence for a 4-bit electronic counter
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(a)
(b)
Figure 30.2 – Mod-16 counter (a) Logic diagram (b) Waveform diagram
Each JK FF is in its toggle position (J and K both at 1)
Assume the outputs are cleared to 0000
As clock pulse 1 arrives at the clock (CLK) input of FF1, it toggles (on the negative edge) and the display shows 0001
Clock pulse 2 causes FF1 to toggle again, returning output Q to 0, which causes FF2 to toggle to 1
The count on the display now reads 0010
The counting continuous, with each flip-flop output triggering the next flip-flop on its negative going pulse
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Notice that FF1 must toggle for each pulse, while FF2 must toggle half as often as FF1
Each more significant bit toggles less often
FF1 triggers FF2, FF2 triggers FF3, and so on
Because one flip-flop affect the next one, it takes some time to toggle all flip-flops
The changing of states is a chain reaction that ripples through the counter
For this reason this counter is called a ripple counter
The counter in Figure 30.2 could be described as a ripple counter, a mod-16 counter, a 4-bit counter, or an asynchronous counter
The ripple and asynchronous labels mean that all the flip-flops do not trigger at one time
9.2 Mod-10 Ripple Counters
The counting sequence for mod-10 counter is from 0000 to 1001 (0 to 9 in decimal)
The mod-10 counter has four place values; 8s, 4s, 2s, and 1s
This takes four flip-flops connected as a ripple counter in Figure 30.3
Figure 30.3 – Logic diagram for a mod-10 ripple counter
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A NAND gate must be added to the ripple counter to clear all the flip-flops back to zero immediately after the 1001 (decimal 9) count
The trick is to look at Figure 30.1 and determine what the next count will be after 1001
Since the next count after 1001 is 1010 (decimal 10), the two 1s in the 1010 must be fed into a NAND gate to clear the flip-flop back to 0000
This type of counter might also be called a decade (meaning 10) counter
Ripple counters can be constructed from individual flip-flops
Manufacturers also produce ICs with all four flip-flops inside a single package
9.3 Synchronous Counters
Ripple counters are asynchronous counters because each flip-flops does not trigger exactly in step with the clock pulse
For some high-frequency operations it is necessary to have all stages of the counter trigger together
There is such a counter: a synchronous counter
Logic diagram for a synchronous counter is shown in Figure 30.4
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Figure 30.4 – A 3-bit synchronous counter
This logic diagram is for a 3-bit (mod-8) counter
Notice that the clock is connected directly to the CLK input of each flip-flop
The CLK inputs are connected in parallel
Figure 30.5 shows the counting sequence of this counter
Figure 30.5 – The counting sequence of a 3-bit synchronous counters
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The counting sequence of this counter is as follows: o Pulse 1 (row 2 in truth table)
Circuit action : Each flip-flop is pulsed by the clock Only FF1 can toggle because it is the only
one with 1s applied to both J and K input FF1 goes from 0 to 1 Output result: 001 (decimal 1)
o Pulse 2 (row 3 in truth table) Circuit action : Each flip-flop is pulsed by the clock Two flip-flops toggle because they have 1s
applied to both J and K inputs FF1 and FF2 both toggle FF1 goes from 1 to 0 FF2 goes from 0 to 1 Output result: 011 (decimal 3)
o Pulse 3 (row 4 in truth table) Circuit action : Each flip-flop is pulsed by the clock Only flip-flop toggles FF1 goes from 0 to 1 Output result: 011 (decimal 3)
o Pulse 4 (row 5 in truth table) Circuit action : Each flip-flop is pulsed by the clock All flip-flops toggle to opposite state FF1 goes from 1 to 0 FF2 goes from 1 to 0 FF3 goes from 0 to 1 Output result: 100 (decimal 4)
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o Pulse 5 (row 6 in truth table)
Circuit action : Each flip-flop is pulsed by the clock Only one flip-flop toggles FF1 goes from 0 to 1 Output result: 101 (decimal 5)
o Pulse 6 (row 7 in truth table) Circuit action : Each flip-flop is pulsed by the clock Two flip-flops toggle FF1 goes from 1 to 0 FF2 goes from 0 to 1 Output result: 110 (decimal 6)
o Pulse 7 (row 8 in truth table) Circuit action : Each flip-flop is pulsed by the clock Only one flip-flop toggles FF1 goes from 0 to 1 Output result: 111 (decimal 7)
o Pulse 8 (row 9 in truth table) Circuit action : Each flip-flop is pulsed by the clock All three flip-flops toggle All flip-flops change from 1 to 0 Output result: 000 (decimal 0)
Notice that the JK FF are used in their toggle mode (J and K at 1) or hold mode (J and K at 0)
Synchronous counters are most often purchased in IC form.
Synchronous counters are available in both TTL and CMOS
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9.4 Down Counters
A counter that counts from higher to lower numbers is called a down counter
Figure 30.6 shows a logic diagram of a mod-8 asynchronous down counter
Figure 30.6 – A 3-bit ripple down counter
Note how much the down counter in Figure 30.6 looks like the up counter in Figure 30.2
The only difference is in the “carry” from FF1 to FF2 and the carry from FF2 to FF3
The up counter carries from Q to the CLK input of the next flip-flop
The down counter carries from Q to the CLK input of
the next flip-flop
Notice that the down counter has a preset (PS) control to preset the counter to 111 (decimal 7) to start the downward count
The counting sequence for this counter is shown in Figure 30.7
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Figure 30.7 – The counting sequence of a 3-bit ripple down counter
9.5 Self-Stopping Counters
The down counter shown in Figure 30.6 recirculates
That is, when it gets to 000 it starts at 111, then 110, and so forth
However, sometimes it desired that a counter stop when a sequence is finished
Figure 30.7 shows a 3-bit down counter with selfstopping feature
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Figure 30.7 – A 3-bit down counter with self-stopping feature
An OR gate is added to place a logical 0 on the J and K inputs of FF1 when the count at outputs C, B, and A reaches 000
The preset must be enabled (PS to 0) again to start the sequence at 111 (decimal 7)
Up ordown counters can be stopped after any sequence of counts by using a logic gate or combination of gates
The output of the gate is fed back to the J and K inputs of the first flip-flop in a ripple counter
The logical 0s fed back to the J and K inputs of FF1 in Figure 30.7 place it in the hold mode
This stopsa FF1 from toggling, thereby stopping the count at 000
9.6 Counters as Frequency Dividers
An interesting and common use of counters is for frequency division
As an example of a simple system using a frequency divider is shown in Figure 30.8, which forms the basis for a digital clock
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Figure 30.8 – A 1-second timer system
The 60 Hz input frequency of sinusoidal signal formed into a square wave, is fed to a divide-by 60 circuit.
The divide-by-60 circuit can be formed by using a modulo-6 counter in series with a modulo-10 (a decade counter), as shown in Figure 30.9
Figure 30.9 – Practical divide-by-60 circuit used as a 1-second timer
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9.7 TTL IC Counters
Figure 31.1 shows the block diagram of a 7493 TTL 4-bit binary counter and Figure 31.2 shows its pin
Figure 31.1 - Block diagram of a 7493 TTL 4-bit binary counter
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Figure 30.2 – Pin configuration of 7493 IC
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The block diagram shows that the 7493 IC houses four JK FFs wired as a ripple counter
Notice that the bottom three JK FFs are prewired internally as a 3-bit ripple counter with output QB connected to the clock input of the next lower JK FF and output QC connected internally to the clock input of the bottom JK FF
Importantly, the top JK FF does not have its QA output internally connected to the next lower flip-flop
To use the 7493 IC as a 4-bit ripple counter (mod-16), the QA output has to be connected to input B which is the CLK input of the second flip-flop
A counting sequence for the 7493 IC wired as a 4-bit ripple counter is shown in figure 31.3
Figure 31.3 – Counting sequence
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The set/reset function table in Figure 31.4 shows that the 7493 counter will be reset (0000) when both R0(1) and R0(2) are HIGH
When either or both reset inputs are LOW, the 7493 IC will count
Figure 31.4 – Reset/Count function table
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9.8 CMOS IC Counters
Manufacturers of CMOS chips offer a variety of counters in IC form
Only one type of such counters, as shown in Figure 31.5, will be discussed in this section
Figure 31.5 – CMOS dual 4-bit binary counter IC (74HC393). (a) Function diagram (b) pin configuration (c) Detailed logic diagram (d) Pin diagram
Note that the IC contains two 4-bit binary ripple counters
The table in Figure 31.5(b) gives the names and functions of each input and output pins on the 74HC393 IC
Note that the clock inputs are labeled with the letters
CP instead of CLK, as used ealier
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9.9 A 3-Digit BCD Counter
Figure 31.6 shows the functional block diagram of a 4553 (MC14553) CMOS 3-Digit BCD Counter
Figure 31.6 – The functional block diagram of 4553 3-Digit BCD Counter
This IC contains three cascaded decade counters
Cascading counters means that the 1s BCD counter triggers the 10s counter as it recirculates from 1001BCD to 0000BCD
In like manner, the 10s counter triggers the 100s counter as it recirculates from 1001BCD to 0000BCD
A truth table drawn in Figure 31.7 for the 4553 3-digit BCD counter IC shows a few of the modes of operation
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Figure 31.7 – Partial truth table for 4553 3-Digit BCD counter
The BCD output from the three counters are fed through the the three 4-bit transparent latches
The BCD data is then transferred to a display multiplexer circuit
The display multiplexing circuit will drive three 7-segment displays
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Figure 31.8 shows a 3-Digit U
Figure 31.8 – A 3-Digit Up Counter circuit
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10.0 Shift Registers
A shift register is a group of memory cells grouped together and considered a single unit
The register can be used to simply store information for later use or the register can be designed to act on the data as is the case of a shift register
A shift register usually modifies the contents by shifting data right or left
The term latch may be used to describe the register used to store data
A buffer register is a specific use of a storage device that holds data that is waiting to be transferred
Shift registers are constructed by wiring flip-flops together
Shift registers in IC form are also available
Registers often are used to store data momentarily
Figure 32.1 shows a typical example of where registers might be used in a digital system, e.g. a calculator
Figure 32.1 – A digital system using registers
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Notice the use of registers to hold information from the encoder for the processing unit
A register is also being employed for temporary storage between the processing unit and the decoder
Registers are also used at other locations within a digital system
One method of describing shift register characteristics is by how data is loaded into and read from the storage units
Four categories of shift registers (in this example, each storage device is an 8-bit register) are illustrated in Figure 32.2
The registers are classified as: 1. Serial in – serial out 2. Serial in – parallel out 3. Parallel in – serial out 4. Parallel in – parallel out
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Figure 32.2 – Shift register characteristics (a) serial in – serial out (b) Serial in – parallel out (c) Parallel in – serial out (d) Parallel in – parallel out
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10.1 Serial Load Shift Registers
Figure 32.3 shows a basic shift register, constructed from four D FF
Figure 32.3 – A 4-bit serial load shift register using D FFs
This register is called a 4-bit shift register because it has four places to store data: A, B, C, and D
The table in Figure 32.4 shows the operation the shift register
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Figure 32.4
First, clear (CLR input to 0) all the outputs (A, B, C, and D) to 0000 (see line 1 in the table)
The output remain 0000 while they await a clock pulse
Pulse the CLK input once; the output now shows 1000 because the 1 from the D input of FF A has been transferred to the Q output on the clock pulse
Now, enter 1s on the data input (clock pulse 2 and 3); these 1s shift across the display to the right
Next, enter 0s on the data input (clock pulses 4 to 8); it can be seen that the 0s being shifted across the display
On clock pulse 9 enter a 1 at the data input
On pulse 10 the data input is returned to 0
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Pulses 9 to 13 show the single 1 on display being shifted to the right
Line 15 shows the 1 being shifted out the right end of the shift register and being lost
The circuit is referred to as a serial load shift register because only one bit of data at a time can be entered in the register
For example, to enter 0001 in this serial load shift register needs four steps (line 11 to line 14 in Figure 32.4)
10.2 Parallel Load Shift Register
Figure 32.5 illustrates a system that permits parallel loading of four bits at once
Figure 32.5 – Block diagram of a 4-bit parallel load recirculating shift register
These inputs are the data inputs A, B, C, and D
This system couldalso incorporate a recirculating feature that would put the output data back into the input so that it is not lost
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A wiring diagram of the 4-bit parallel load recirculating shift register is shown in Figure 32.6
Figure 32.6 – Wiring diagram of a 4-bit parallel load recirculating shift register
In this register, the recirculating lines leading from the Q
and Q outputs of FF D back to the J and K inputs of FF
A
These feedback lines cause the data that would normally be lost out of FF D to recirculate through the shift register
The CLR input clears the outputs to 0000 when enabled by a logical 0
The parallel load data inputs A, B, C, and D are connected to the preset (PS) inputs of the flip-flops to set 1s at any output position (A, B, C, D)
If the switches attached to the parallel load data inputs are even temporarily switched to a 0, that output will be preset to a logical 1
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The clock pulsing the CLK inputs of the JK FF will cause data to be shifted to the right
The data from FF D will be recirculated back to FF A
Figure 32.7 illustrates the operation of the parallel load shift register
Figure 32.7 – Operation of a 4-bit parallel load recirculating shift register
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11. Binary arithmetic and arithmetic circuits
11.1 Binary Addition
0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 Carry 1 or 102 The symbol + indicates added (Add) not OR.
Example 1 1 1
1 0 02 = 410 1 0 1 510 +0 1 02 = 210 0 1 1 310
1 1 0 610 1 0 0 0 810 Truth table for add operations is as follows: - The output consists of two parts: Sum (total) and Carry out.
Input Output
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
A + B Co
Block form Logic Form
Half Adder
From the truth table, we get = A B and Co = A B
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Input Output
A B Cin Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
A + B + Cin Sum Cout
Input Output
A B D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
A - B Di Bo
• This operation is called Half Adder, which can only be used for adding the first column only. • But for the next column, the Full Adder (FA) circuit’s is used to take into account the result of the addition of Carry on previous column.
Truth Table for Full Adder is as follows: -
= A + B + Cin
We use two HA, for making two additions. First operation is between A and B, both for (A + B) and Cin. Cout from FA values taken from one of the HA Cout (by OR operation).
Binary Subtraction. 0 - 0 = 0 0 - 1 = 1 Borrow 1 1 - 0 = 1 1 - 1 = 0 Example 0 10
1 0 210 - 0 1 110
0 1 110
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Input Output
A B Bin Di Bo
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
A - B - Bin Di Bout
From the truth table, the difference, Di = A B and borrow is
Bo = BA Logic circuit for HS binary subtraction is as follows: -
Similar to the case of additions, HS can only be used in the first column, while the next column we use Full Substractor (FS) Truth table for FS is
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Here is a logic circuit for FS built from two HSs and an OR gate.
Examples of the use of HS and FS 64s 32s 16s 8s 4s 2s 1s A 1 1 1 0 1 0 1 11710
-B 0 0 1 1 1 0 0 2810 Di 1 0 1 1 0 0 1 8910 (0) (1) (1) (0) (0) (0) Bin Bin Bin Bin Bin Bin Bin
Bo Bo Bo Bo Bo Bo Bo Bo (0) (0) (1) (1) (0) (0) (0)
• In the first column, the operation of HS was used. Di = A - B = 1 - 0 = 1 and Bo = 0
• In the second column Di = A - B - Bin = 0 - 0 - 0 = 0 and Bo = 0. Bin is Bo from HS operations in the first column
• All operations of FS were used for the next column.
Parallel Addition and Subtraction
Usually the addition and subtraction operations carried out in parallel in which only the first column only using HA or HS, whereas all subsequent column using FA or FS.
To perform the FA / FS in the second column and the next, the
value of Cin / Bin taken from Cout / Bout from operations in the
previous column.
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Use FA only for the addition • If we want to use FA only for the addition, we can do by making Cin
= 0 for the first column. Results are the same with HA operation Circuit is as follows: -
Use the adder for subtraction. • With a little modification to the circuit in parallel addition it can be used for parallel subtraction. Di = A - B = A + (-B).
• (-B) here is the negative value of a signed number or 2's
complement number of (-B) = B + 1. So Di = A – B = A +
(-B) = A + B + 1
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• We use all FA circuit where Cin = 1 for FA in the first row • Circuit for 4 bits subtraction is as follows: -
Comparing subtraction circuit using the FA with addition circuits using FA alone, there is little difference. In the first column, the addition with Cin = 0 whereas in subtraction, Cin = 1
Then in the subtraction the values of Bin is inverted but not in the addition
So the addition and subtraction circuits can share the FA but we need some extra circuitry, so that the use of FA during addition and subtraction can be done correctly
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Circuit is as follows: -
• for add operation, the Control Mode is set to 0. Then Cin = 0 in FA1
and B = Bi • But when the subtraction to be done, the Control Mode is set to 1,
so Cin = 1 in FA1 and B = iB
• Actually, this circuit can be used for addition and subtraction of unsigned binary (2's complement).
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13 1101
x10 x1010
00 0000
13 1101
130 0000
1101
10000010
Binary Multiplication 0 0 1 1 x0 x1 x0 x1 0 0 0 1 The traditional method is used for the multiplication of binary numbers and decimal • This method is used in the logic circuit for multiplying two binary numbers • The method used is as follows: -.
• Rows 1 and 2 are two values to be multiplied. Line 3 is the first partial product (0 x 1101 = 0000) • Line 4 shows a shift to the left of the second digit of the product of (1 x 1101 = 1101) in the fifth row • Line 6 is the sum of the product of the first and the second (which is shifted to the left), is 11010 • Shift left in 7th line, for the third partial product (0 x 1101 = 0000) in 8th row • 9th Line for the total product of 011010. Displacements in the 10th row for the fourth partial product (1 x 1101 = 1101) in the 11th row • 12th Line is the final product of the total, which is also the actual product. • Multiplication method is called add and shift method.
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There are three important facts in add and shift method.
1) the product = 0000 if bits in the multiplier is 0, and the product
= multiplicand, if bits in the multiplier is 1
2) The end product can be twice the size of the multiplicand.
3) The product of the first digit is shifted rightward compared by
the product of a second.
From the above observations, the binary multiplier circuit can be
constructed.
• binary multiplier is 5-bit parallel adder with control circuit either
added / not add
• The multiplicand and multipler filled with values from the previous
example
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Operation of a binary multiplier circuit is as follows: - • Step 1 for clear (accumulator = 0) and load the data on the Multiplier • 2nd step for add operations if control = 1. • the product of Step 3 to shift rightward. • 4th step for add operations if control = 1. Add to accumulator by the multiplicand. • Step 5 for the product of rightward shift • Step 6 for add operations if control = 1. • Step 7 for the product of rightward shift • Step 8 for add operations if control = 1. • Step 9 for shift rightward product of the actual result. There are 4 times ADD operation and 4 times SHIFT operation • This method is used in the computer when doing multiplication.