IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY VOL 9 No 2 JUNE 1999

RSFQ-Based DA Converter for AC Voltage Standard

H Sasaki S Kiryu F Hirayama T Kikuchi M Maezawa and A Shoji Electrotechnical Laboratory 1 - 1-4 Umezono Tsukuba Ibaraki 305-8568 Japan

S V Polonsky State University of New York Stony Brook NY 11794 USA

3561

Akh-act-Digital to analog converters based on the Joseph- son effect are promising for voltage standards because they pro- duce voltage steps with ultimate precision and stability In this paper we describe a project to develop a Josephson DA con- verter designed for synthesizing a sinusoidal waveform with metrological accuracy The DA converter is based on RSFQ (Rapid Single Flux Quantum) logic circuits and consists of a fre- quency multiplier (FM) a pulse distributor (PD) and a number of voltage multipliers (VMs) Each VM circuit corresponding to the n-th bit digital code multiplies the number of SFQ pulses by a factor of 2n By gating the input SFQ pulses from the FM to the VMs using the PD circuits a programmable output voltage is obtained Possible sources of uncertainties in the measure- ment of the rms value of the synthesized sine wave are discussed

I INTRODUCTION

Present dc voltage standard is established using the Joseph- son effect The precise voltage is generated by irradiating a large array of Josephson junctions with microwave of fre- quency f and biasing the array to the constant voltage steps The voltage is derived from the Josephson relationship V=NjKj where KJ = 4835979 GHzJV is the Josephson con- stant and N is the total number of voltage steps

The Josephson effect may be applied to a synthesis of ac waveform with metrological accuracy aiming at the ac vol- tage standard or precision ac measurements However pres- ent dc voltage standards cannot change the voltage with the speed fast enough to generate an ac waveform even at fre- quency as low as a few Hz The first successful approach to realize a rapidly programmable dc voltage standard is the Binary-type Josephson DA converters proposed by NIST[l] In this approach the array is divided into sections containing binary number of junctions (12 2n) By chang- ing the bias currents for each of the blocks an arbitrary number of voltage steps N can be selected However the bi- nary-type DA converter suffers from large uncertainty as a result of switching transients and jitters This is due to the fact that the transitions from one voltage level to another are con- trolled by external semiconductor circuits

In order to overcome the effect of transients the binary- type DA has been modified to the pulse-driven DA converter[2] in which the output voltage is controlled not by

Manuscript received September 15 1998

ut

Fig 1 Schematic Diagram of a 4-bit DA converter consisting of a frequency multiplier (FM) a pulse distributor (PD) and a number of voltage multipliers (VMs)

changing the total voltage steps N but by changing the driv- ing frequency f using a microwave digital pulse generator Using this method a synthesis of sine wave with +18 mV am- plitude at 5 kHz has been demonstrated[3]

Another type of Josephson DA converter based on pro- cessing of single flux quantum (SFQ) pulses[4] has been pro- posed by SUNY[5] and NIST[6] The main components of the DA converter are voltage multipliers (VMs) which am- plify the voltage by multiplying the number of SFQ pulses We hereafter call this type of DA converter as RSFQ-DA The advantages of the RSFQ-DAs compared to the pulse-dri- ven DA converters are that the RSFQ-DAs do not require ex- ternal microwave pulse generators and that the output circuit can be floated from the rest of the circuit

In this paper we describe a project to develop an RSFQ- DA in ETL The design and the simulation of the RSFQ-DA and some results from the prototype VM circuit are presented The possible sources of uncertainty for the application in the ac voltage standard are also discussed

11 DESIGN AND SIMULATION

A four-bit prototype RSFQ-DA is under development at ETL The schematic diagram of the DA converter circuit is shown in Fig 1 The DA converter consists of a frequency multiplier (FM) a pulse distributor (PD) and a number of

1051-822399$1000 0 1999 IEEE

3562

voltage multipliers (VMs) The FM consists of m stages of a binary counter with shift registers and generate successive 2m pulses (Train) and an End-Of-Pulse ( E O P ) signal syn- chronized with the external reference clock (Rin) Using ten stages of the binary counters the FM generates 1024 GHz SFQ pulses synchronized to an external reference clock (Rin) of 10 MHz The SFQ pulses (Train) are then distributed to the VM via the PD according to the digital code (Code) from an external waveform ROM Each PD circuit gates the pulse Train according to the status of the Code latched by the trig- ger pulse EOP Each of the four x2n VM corresponds to the n-th bit digital code and multiplies the number of SFQ pulses (Pout-n) by a factor of 2n-1 By connecting the four VMs in series the digital Code generated by the ROM is reproduced at the output (Vout) as the analog voltage output

The numerical simulation and optimization of the main cir- cuit components (FM PD VM) have been carried out using the PSCANICADENCE and the COWBOY programs devel- oped at SUNY at Stony Brook[7] The process parameters are assumed to be Jc = 14 kAcm2 C = 52 pFcm2 BC = 10 and Zmin = 125 pA in the simulation The detailed explanation for the circuits and the result of the numerical simulations are described in the following subsections

A Voltage Multiplier

The newly designed voltage multiplier (VM) circuit con- sists of a magnetically coupled Josephson Transmission Line (JTL) and dc SQUIDS The schematic diagram of a four- stage (x4) VM circuit is shown in Fig 2 Similar types of VMs using magnetic coupling have been reported [6][8] The main drawback of these circuits is the small operating margins due to intrinsically small magnetic coupling between the JTL and the dc SQUID In the new design the basic building block of the VM is composed of two units of JTLs coupled with a dc SQUID This structure enhances the mag- netic coupling between the JTL and the SQUID resulting in wide operating margins in spite of the small coupling con- stant (k = 04 - 05) Also the use of the lightly- and heavily- damped junctions (J4 and J5 respectively) for the SQUID secures the correct switching sequence of the SQUID and in- creases the operating margins By simulation critical mar- gins larger than 30 and the maximum operating frequency up to 50 GHz are expected

Ihias - r i n -

R I J I R 2 J2 R 3 1 3 RO

Fig 2 Schematic diagram of a four-stage (x4) Voltage Multiplier (VM) circuit

F1

j 132 R32 L33

j 133 - L32 J34 J35 A

D-FF i

FO

Fig 3 Schematic diagram of a BCSR (dual-rail binary counter with shift registers) circuit

B Frequency Multiplier

A Frequency Multiplier (FM) circuit consists of m stages of a dual-rail binary counter with shift registers (BCSR) Fig 3 shows the equivalent circuit for the BCSR circuit An input pulse from terminal [C] flashes D-FFs to the dual-rail output terminals [FO] and [Fl] The output terminals are connected to [A] and [B] of the next-stage BCSR circuit The T-FF with a confluence buffer block works as a dual-rail binary counter The timing requirement for the correct operation of the FM is that the input from [C] should flash D-FFs before the inpul pulse to [A] or [B] from the following BCSR changes the state of the D-FFs through the T-FF This race condition is satisfied independent of the number of stages m and hence the high frequency operation of the circuit is expected

Results of the numerical simulation for the FM circuit are shown in Fig 4 The five-stage FM generates 32 successive pulses following the Rin trigger signal Regardless of the undetermined initial states of the storage loops in the circuit this circuit works correctly after N+1 initialization pulses By simulation the operating margins have been estimated to be as large as +25

2 $ 02 - 00 0 4 ~ [ I I ~ I

E 04

00

g 02

00 10 20 30 40 50 Time (ns)

Fig 4 Results of a simulation for a 5-stage Frequency Multiplier (FM) circuit The FM generates 32 successive (Truin) pulses and the End-Of-Pulse (EOP) signal following the trigger signal (Rin)

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Fig 5 Schematic Diagram of one branch of the Pulse Distributor (PD) circuit

C Pulse Distributor

The Pulse Distributor (PD) circuit consists of a pulse switch (PLSW) and a Non-Destructive Read Out (NDRO) circuit as shown in Fig 5 The input SFQ pulses (Train) and End-Of-Pulse (EOP) are applied to the input terminals [RD] and [SRI respectively The Code signals from the waveform ROM are applied to the pair of input terminals D+ and D- as a balanced current input to reduce coupling bet- ween the input and output cables

The PLSW circuit switches the trigger-pulse EOP to either Set- or Reset-input of the NDRO according to the po- larity of the control signal Code The junctions 523 J24 and the inductors L1 and L2 form a storage loop of the NDRO circuit[4] A clockwise circulating current in the storage loop represents state 1 of the NDRO An SFQ pulse coming from the PLSW circuit via the junction J31 switches the junctions 523 and set the state to 1 When the NDRO state is l the SFQ pulse Train to terminal [RD] switches J25 and J27 and the SFQ pulse is reproduced at the terminal [Q] (Pout) When the state is IO the junction J26 is switched and the SFQ pulses does not appear at the output

Results of a simulation for the circuit is shown in Fig 6 When a pulse EOP arrives while the control line Code is 1 (positive) the succeeding SFQ-pulses Train from the FM will be reproduced at the output Pout If the EOP ar- rives while the control line Code is 0 (negative) the SUC-

ceeding SFQ pulse-train do not appear at the output By simu- lation the operating margins of the global parameters have been estimated to be approximately f30

111 UNCERTAINTY ANALYSIS

Since the output voltage of the RSFQ-DA is derived from the Josephson relationship the sine wave generated by the RSFQ-DA may achieve a precision in the output amplitude equivalent to the precision of dc voltage standard Further- more the transition between the different output levels is con- trolled by the ultra-fast RSFQ digital circuit Hence the errors due to switching transients and jitters are expected to be much smaller than one part in 106 Thus the rms value of the sine wave may exceed the accuracy of the conventional ac voltage

S $ 04

00 p 04

00

z g 02

8 g 02

0 02 04 06 08 1 12 14 16

Time (ns)

Fig 6 Results of a simulation for one branch of the PD circuit The input-pulse trains (Truin) are gated according to the polarity of the control line (Code) sampled by (EOP) pulses

standard derived from the thermal ac-dc transfer standard In this section possible sources of uncertainty in the meas-

urement of the rms value of the synthesized sine wave are de- scribed Contributions from the high-frequency components due to quantization and the pulse-train are evaluated The in- fluence from the room-temperature rms detection circuit and the output cable are also discussed A more detailed analysis on the possible sources of uncertainty is given in [9]

A EfSect of High-frequency Components

The rms-power of the quantization noise of the n-bit quasi- sine waveform is given by APnojSE=(2(~21+)3)P~ where P o represents the power of the fundamental frequency In the case of a 10-bit DA converter the contribution of quantiza- tion noise is estimated to be ltlo-7 The resolution in the time axis is 104 if we take 1 kHz and 10 MHz for fundamental and sampling frequency respectively Thus the contribution from sampling noise is much smaller than the quantization noise

On the other hand a dead-time of -10 ns is inserted bet- ween the pulse trains at every 100 ns During the dead-time no voltage appears at the output The rms noise power due to the periodic dead-time is in the order of 10-4 which can be re- duced to ltlo-8 by a second-order low-pass filter with cut-off frequency of 1 MHz The loss of power of the fundamental 1 kHz components due to the filter is in the order of 10-12

B Influence of Room Temperature Johnson noise

When the output voltage from the RSFQ-DA is measured by a room-temperature detection circuit the signal to noise (SN) ratio of the voltage measurement is determined by the equivalent noise resistance Rlocrci and noise temperature T of the detection circuit The rms noise voltage is given as Vnoise=d(4kTBRloud) Here B is the equivalent bandwidth of the measurement and k is the Boltzmann constant

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Also the thermal noise current (Znoise) from the room-tem- perature detector may upset the measurement if the noise cur- rent exceeds the width of the voltage step (Zyep-I00 PA) of the RSFQ-DA The peak-to-peak value of the noise-current is given as Zise=1(32kTBRload) Thus the optimum values for the equivalent input resistance Rload are within a range from 100 52 to 10 k52 in which both the SN ratio of gtIO7 and the noise margin of gt 104 are realized

C Effect of the Output Cable

When the output voltage from the RSFQ-DA is measured by a detector at room temperature the length of the output ca- ble becomes of the order of 1 meter If the input impedance Rbad of the detector is relatively low (=I kn) the lead-resist- ance of the output cable (=O 1 Qm) can contribute to a error of IO-Ym due to the voltage drop by the load current

Similarly when the output of the RSFQ-DA is compared to a standard voltage source (Vx at room temperature the voltage drop AVmeas due to the cable is calculated as AVmeus=(RdR~d)AVX Here Rp is the resistance of the cable and AVx is the in-phase component of the voltage difference between the RSFQ-DA and the voltage source Hence by ad- justing the voltage difference AVx to lt01 the error due to the resistance in the output cable may be reduced to ltIO-7 Contribution from the parasitic inductance L and capacitance C of the cable is calculated as d L C which is of the order of 10-9 at the test frequency of 1 kHz Thus all the sources of error in measuring the rms value of the sinusoidal waveform generated by RSFQ-DA can be reduced to less than one part in 107

Iv RESULTS AND DISCUSSION

A four-stage (x4) VM has been fabricated using HYPRES standard technology in order to examine the effectiveness of the new design The measured I-V characteristic of the VM circuit is shown in Fig 7 The data V shows the depend- ence of the output voltage on the SQUID-bias current [bias The region where V coincides with 4Vi corresponds to the operating region where the SQUIDs are phase-locked to the JTL From the measured operating region the margins of Zhjay are measured to be +20 at the input frequency of 16 GHz (corresponding to V =O 14 mV) The operation of the four-stage VM has been verified at higher frequencies up to 45 GHz

The prototype four-bit RSFQ-DA is under fabrication at ETL using the standard process-technology of ETL which features NbAIOxNb junction Si02 insulation and Pd resis- tor The design values of the critical current density of the junction J and the sheet resistance R are 14 kNcm2 and 12 R respectively

The practical application of the ac voltage standard re- quires generation of 1 kHz 100 mV sine wave with more than IO-bit resolution At a 10 GHz internal clock frequency

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v

c

01

00 015 020 025 030 035 040

Bias Current Ihjcrs (mA)

Fig 7 Dependence of input voltage Vin and output voltage V on bias cur- rent [bias The region where V coincides with 4Vin corresponds to the phase-locking region between the JTL and the SQUIDS

a 12-bit DA converter can generate an output amplitude up to 85 mV From the results of the simulation and the experi- ment it should be possible to implement a 12-bit RSFQ-DA on a single chip using the present process-technology

The RSFQ-DA is more complex compared to the binary- type DA converter and the pulse-driven DA converter but do not require complex and expensive semiconductor microwavt circuits We believe that the RSFQ-DA provides another practical approach to realize the ac voltage standard with Josephson accuracy

REFERENCES

[ l ] C A Hamilton C J Burroughs and R L Kautz Josephson DA converter with fundamental accuracy IEEE Trans Instrum Meas vol IM-44 pp 223-225 1995

[2] S P Benz and C A Hamilton Pulse-driven programmable Jo- sephson voltage standard Appl Phys Lett vol 68 pp 3171- 3173 1996

[3] S P Benz C A Hamilton C J Burroughs and T E Harvey Ac and dc bipolar voltage source using quantized Pulses IEEE Trans Instrum Meas Vol 48 No 2 1999 (to be published)

[4] K K Likharev and V K Semenov RSFQ logichemory fami- ly a new Josephson-junction technology for sub-teraherz-clock- frequency digital systems I IEEE Trans Appl Supercond vol 1 pp 3-28 March 1991

[5] V K Semenov Digital to analog conversion based on process- ing of the SFQ pulses IEEE Trans Appl Superconductivity

[6] C A Hamilton Josephson voltage standard base on Single- Flux-Quantum voltage multipliers IEEE Trans Instrum Meas

vol 3 pp 2637-2640 1993

vol 2 pp 139- 142 1992 [7] PSCANKOWBOY httpllpavelphysicssunysbedulRFSQl [8] D L Meier J H Kang D L Miller J X Przybysz and A H

Worsham Single flux quantum pulse amplifier in Extended Ab- stracts of ISEC93 Boulder Colorado 1993 pp 100-101

[9] H Sasaki S Kiryu and A Shoji Uncertainties in ac voltage measurements using Josephson DA converters Bulletin of the Electrotechnical Laboratory vol 62 pp 1-1 I 1398 (in Ja-

3562

voltage multipliers (VMs) The FM consists of m stages of a binary counter with shift registers and generate successive 2m pulses (Train) and an End-Of-Pulse ( E O P ) signal syn- chronized with the external reference clock (Rin) Using ten stages of the binary counters the FM generates 1024 GHz SFQ pulses synchronized to an external reference clock (Rin) of 10 MHz The SFQ pulses (Train) are then distributed to the VM via the PD according to the digital code (Code) from an external waveform ROM Each PD circuit gates the pulse Train according to the status of the Code latched by the trig- ger pulse EOP Each of the four x2n VM corresponds to the n-th bit digital code and multiplies the number of SFQ pulses (Pout-n) by a factor of 2n-1 By connecting the four VMs in series the digital Code generated by the ROM is reproduced at the output (Vout) as the analog voltage output

The numerical simulation and optimization of the main cir- cuit components (FM PD VM) have been carried out using the PSCANICADENCE and the COWBOY programs devel- oped at SUNY at Stony Brook[7] The process parameters are assumed to be Jc = 14 kAcm2 C = 52 pFcm2 BC = 10 and Zmin = 125 pA in the simulation The detailed explanation for the circuits and the result of the numerical simulations are described in the following subsections

A Voltage Multiplier

The newly designed voltage multiplier (VM) circuit con- sists of a magnetically coupled Josephson Transmission Line (JTL) and dc SQUIDS The schematic diagram of a four- stage (x4) VM circuit is shown in Fig 2 Similar types of VMs using magnetic coupling have been reported [6][8] The main drawback of these circuits is the small operating margins due to intrinsically small magnetic coupling between the JTL and the dc SQUID In the new design the basic building block of the VM is composed of two units of JTLs coupled with a dc SQUID This structure enhances the mag- netic coupling between the JTL and the SQUID resulting in wide operating margins in spite of the small coupling con- stant (k = 04 - 05) Also the use of the lightly- and heavily- damped junctions (J4 and J5 respectively) for the SQUID secures the correct switching sequence of the SQUID and in- creases the operating margins By simulation critical mar- gins larger than 30 and the maximum operating frequency up to 50 GHz are expected

Ihias - r i n -

R I J I R 2 J2 R 3 1 3 RO

Fig 2 Schematic diagram of a four-stage (x4) Voltage Multiplier (VM) circuit

F1

j 132 R32 L33

j 133 - L32 J34 J35 A

D-FF i

FO

Fig 3 Schematic diagram of a BCSR (dual-rail binary counter with shift registers) circuit

B Frequency Multiplier

A Frequency Multiplier (FM) circuit consists of m stages of a dual-rail binary counter with shift registers (BCSR) Fig 3 shows the equivalent circuit for the BCSR circuit An input pulse from terminal [C] flashes D-FFs to the dual-rail output terminals [FO] and [Fl] The output terminals are connected to [A] and [B] of the next-stage BCSR circuit The T-FF with a confluence buffer block works as a dual-rail binary counter The timing requirement for the correct operation of the FM is that the input from [C] should flash D-FFs before the inpul pulse to [A] or [B] from the following BCSR changes the state of the D-FFs through the T-FF This race condition is satisfied independent of the number of stages m and hence the high frequency operation of the circuit is expected

Results of the numerical simulation for the FM circuit are shown in Fig 4 The five-stage FM generates 32 successive pulses following the Rin trigger signal Regardless of the undetermined initial states of the storage loops in the circuit this circuit works correctly after N+1 initialization pulses By simulation the operating margins have been estimated to be as large as +25

2 $ 02 - 00 0 4 ~ [ I I ~ I

E 04

00

g 02

00 10 20 30 40 50 Time (ns)

Fig 4 Results of a simulation for a 5-stage Frequency Multiplier (FM) circuit The FM generates 32 successive (Truin) pulses and the End-Of-Pulse (EOP) signal following the trigger signal (Rin)

3563

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Fig 5 Schematic Diagram of one branch of the Pulse Distributor (PD) circuit

C Pulse Distributor

The Pulse Distributor (PD) circuit consists of a pulse switch (PLSW) and a Non-Destructive Read Out (NDRO) circuit as shown in Fig 5 The input SFQ pulses (Train) and End-Of-Pulse (EOP) are applied to the input terminals [RD] and [SRI respectively The Code signals from the waveform ROM are applied to the pair of input terminals D+ and D- as a balanced current input to reduce coupling bet- ween the input and output cables

The PLSW circuit switches the trigger-pulse EOP to either Set- or Reset-input of the NDRO according to the po- larity of the control signal Code The junctions 523 J24 and the inductors L1 and L2 form a storage loop of the NDRO circuit[4] A clockwise circulating current in the storage loop represents state 1 of the NDRO An SFQ pulse coming from the PLSW circuit via the junction J31 switches the junctions 523 and set the state to 1 When the NDRO state is l the SFQ pulse Train to terminal [RD] switches J25 and J27 and the SFQ pulse is reproduced at the terminal [Q] (Pout) When the state is IO the junction J26 is switched and the SFQ pulses does not appear at the output

Results of a simulation for the circuit is shown in Fig 6 When a pulse EOP arrives while the control line Code is 1 (positive) the succeeding SFQ-pulses Train from the FM will be reproduced at the output Pout If the EOP ar- rives while the control line Code is 0 (negative) the SUC-

ceeding SFQ pulse-train do not appear at the output By simu- lation the operating margins of the global parameters have been estimated to be approximately f30

111 UNCERTAINTY ANALYSIS

Since the output voltage of the RSFQ-DA is derived from the Josephson relationship the sine wave generated by the RSFQ-DA may achieve a precision in the output amplitude equivalent to the precision of dc voltage standard Further- more the transition between the different output levels is con- trolled by the ultra-fast RSFQ digital circuit Hence the errors due to switching transients and jitters are expected to be much smaller than one part in 106 Thus the rms value of the sine wave may exceed the accuracy of the conventional ac voltage

S $ 04

00 p 04

00

z g 02

8 g 02

0 02 04 06 08 1 12 14 16

Time (ns)

Fig 6 Results of a simulation for one branch of the PD circuit The input-pulse trains (Truin) are gated according to the polarity of the control line (Code) sampled by (EOP) pulses

standard derived from the thermal ac-dc transfer standard In this section possible sources of uncertainty in the meas-

urement of the rms value of the synthesized sine wave are de- scribed Contributions from the high-frequency components due to quantization and the pulse-train are evaluated The in- fluence from the room-temperature rms detection circuit and the output cable are also discussed A more detailed analysis on the possible sources of uncertainty is given in [9]

A EfSect of High-frequency Components

The rms-power of the quantization noise of the n-bit quasi- sine waveform is given by APnojSE=(2(~21+)3)P~ where P o represents the power of the fundamental frequency In the case of a 10-bit DA converter the contribution of quantiza- tion noise is estimated to be ltlo-7 The resolution in the time axis is 104 if we take 1 kHz and 10 MHz for fundamental and sampling frequency respectively Thus the contribution from sampling noise is much smaller than the quantization noise

On the other hand a dead-time of -10 ns is inserted bet- ween the pulse trains at every 100 ns During the dead-time no voltage appears at the output The rms noise power due to the periodic dead-time is in the order of 10-4 which can be re- duced to ltlo-8 by a second-order low-pass filter with cut-off frequency of 1 MHz The loss of power of the fundamental 1 kHz components due to the filter is in the order of 10-12

B Influence of Room Temperature Johnson noise

When the output voltage from the RSFQ-DA is measured by a room-temperature detection circuit the signal to noise (SN) ratio of the voltage measurement is determined by the equivalent noise resistance Rlocrci and noise temperature T of the detection circuit The rms noise voltage is given as Vnoise=d(4kTBRloud) Here B is the equivalent bandwidth of the measurement and k is the Boltzmann constant

3564

Also the thermal noise current (Znoise) from the room-tem- perature detector may upset the measurement if the noise cur- rent exceeds the width of the voltage step (Zyep-I00 PA) of the RSFQ-DA The peak-to-peak value of the noise-current is given as Zise=1(32kTBRload) Thus the optimum values for the equivalent input resistance Rload are within a range from 100 52 to 10 k52 in which both the SN ratio of gtIO7 and the noise margin of gt 104 are realized

C Effect of the Output Cable

When the output voltage from the RSFQ-DA is measured by a detector at room temperature the length of the output ca- ble becomes of the order of 1 meter If the input impedance Rbad of the detector is relatively low (=I kn) the lead-resist- ance of the output cable (=O 1 Qm) can contribute to a error of IO-Ym due to the voltage drop by the load current

Similarly when the output of the RSFQ-DA is compared to a standard voltage source (Vx at room temperature the voltage drop AVmeas due to the cable is calculated as AVmeus=(RdR~d)AVX Here Rp is the resistance of the cable and AVx is the in-phase component of the voltage difference between the RSFQ-DA and the voltage source Hence by ad- justing the voltage difference AVx to lt01 the error due to the resistance in the output cable may be reduced to ltIO-7 Contribution from the parasitic inductance L and capacitance C of the cable is calculated as d L C which is of the order of 10-9 at the test frequency of 1 kHz Thus all the sources of error in measuring the rms value of the sinusoidal waveform generated by RSFQ-DA can be reduced to less than one part in 107

Iv RESULTS AND DISCUSSION

A four-stage (x4) VM has been fabricated using HYPRES standard technology in order to examine the effectiveness of the new design The measured I-V characteristic of the VM circuit is shown in Fig 7 The data V shows the depend- ence of the output voltage on the SQUID-bias current [bias The region where V coincides with 4Vi corresponds to the operating region where the SQUIDs are phase-locked to the JTL From the measured operating region the margins of Zhjay are measured to be +20 at the input frequency of 16 GHz (corresponding to V =O 14 mV) The operation of the four-stage VM has been verified at higher frequencies up to 45 GHz

The prototype four-bit RSFQ-DA is under fabrication at ETL using the standard process-technology of ETL which features NbAIOxNb junction Si02 insulation and Pd resis- tor The design values of the critical current density of the junction J and the sheet resistance R are 14 kNcm2 and 12 R respectively

The practical application of the ac voltage standard re- quires generation of 1 kHz 100 mV sine wave with more than IO-bit resolution At a 10 GHz internal clock frequency

~

panese)

03 $ lamp 02 E

3

v

c

01

00 015 020 025 030 035 040

Bias Current Ihjcrs (mA)

Fig 7 Dependence of input voltage Vin and output voltage V on bias cur- rent [bias The region where V coincides with 4Vin corresponds to the phase-locking region between the JTL and the SQUIDS

a 12-bit DA converter can generate an output amplitude up to 85 mV From the results of the simulation and the experi- ment it should be possible to implement a 12-bit RSFQ-DA on a single chip using the present process-technology

The RSFQ-DA is more complex compared to the binary- type DA converter and the pulse-driven DA converter but do not require complex and expensive semiconductor microwavt circuits We believe that the RSFQ-DA provides another practical approach to realize the ac voltage standard with Josephson accuracy

REFERENCES

[ l ] C A Hamilton C J Burroughs and R L Kautz Josephson DA converter with fundamental accuracy IEEE Trans Instrum Meas vol IM-44 pp 223-225 1995

[2] S P Benz and C A Hamilton Pulse-driven programmable Jo- sephson voltage standard Appl Phys Lett vol 68 pp 3171- 3173 1996

[3] S P Benz C A Hamilton C J Burroughs and T E Harvey Ac and dc bipolar voltage source using quantized Pulses IEEE Trans Instrum Meas Vol 48 No 2 1999 (to be published)

[4] K K Likharev and V K Semenov RSFQ logichemory fami- ly a new Josephson-junction technology for sub-teraherz-clock- frequency digital systems I IEEE Trans Appl Supercond vol 1 pp 3-28 March 1991

[5] V K Semenov Digital to analog conversion based on process- ing of the SFQ pulses IEEE Trans Appl Superconductivity

[6] C A Hamilton Josephson voltage standard base on Single- Flux-Quantum voltage multipliers IEEE Trans Instrum Meas

vol 3 pp 2637-2640 1993

vol 2 pp 139- 142 1992 [7] PSCANKOWBOY httpllpavelphysicssunysbedulRFSQl [8] D L Meier J H Kang D L Miller J X Przybysz and A H

Worsham Single flux quantum pulse amplifier in Extended Ab- stracts of ISEC93 Boulder Colorado 1993 pp 100-101

[9] H Sasaki S Kiryu and A Shoji Uncertainties in ac voltage measurements using Josephson DA converters Bulletin of the Electrotechnical Laboratory vol 62 pp 1-1 I 1398 (in Ja-

3563

~

Fig 5 Schematic Diagram of one branch of the Pulse Distributor (PD) circuit

C Pulse Distributor

The Pulse Distributor (PD) circuit consists of a pulse switch (PLSW) and a Non-Destructive Read Out (NDRO) circuit as shown in Fig 5 The input SFQ pulses (Train) and End-Of-Pulse (EOP) are applied to the input terminals [RD] and [SRI respectively The Code signals from the waveform ROM are applied to the pair of input terminals D+ and D- as a balanced current input to reduce coupling bet- ween the input and output cables

The PLSW circuit switches the trigger-pulse EOP to either Set- or Reset-input of the NDRO according to the po- larity of the control signal Code The junctions 523 J24 and the inductors L1 and L2 form a storage loop of the NDRO circuit[4] A clockwise circulating current in the storage loop represents state 1 of the NDRO An SFQ pulse coming from the PLSW circuit via the junction J31 switches the junctions 523 and set the state to 1 When the NDRO state is l the SFQ pulse Train to terminal [RD] switches J25 and J27 and the SFQ pulse is reproduced at the terminal [Q] (Pout) When the state is IO the junction J26 is switched and the SFQ pulses does not appear at the output

Results of a simulation for the circuit is shown in Fig 6 When a pulse EOP arrives while the control line Code is 1 (positive) the succeeding SFQ-pulses Train from the FM will be reproduced at the output Pout If the EOP ar- rives while the control line Code is 0 (negative) the SUC-

ceeding SFQ pulse-train do not appear at the output By simu- lation the operating margins of the global parameters have been estimated to be approximately f30

111 UNCERTAINTY ANALYSIS

Since the output voltage of the RSFQ-DA is derived from the Josephson relationship the sine wave generated by the RSFQ-DA may achieve a precision in the output amplitude equivalent to the precision of dc voltage standard Further- more the transition between the different output levels is con- trolled by the ultra-fast RSFQ digital circuit Hence the errors due to switching transients and jitters are expected to be much smaller than one part in 106 Thus the rms value of the sine wave may exceed the accuracy of the conventional ac voltage

S $ 04

00 p 04

00

z g 02

8 g 02

0 02 04 06 08 1 12 14 16

Time (ns)

Fig 6 Results of a simulation for one branch of the PD circuit The input-pulse trains (Truin) are gated according to the polarity of the control line (Code) sampled by (EOP) pulses

standard derived from the thermal ac-dc transfer standard In this section possible sources of uncertainty in the meas-

urement of the rms value of the synthesized sine wave are de- scribed Contributions from the high-frequency components due to quantization and the pulse-train are evaluated The in- fluence from the room-temperature rms detection circuit and the output cable are also discussed A more detailed analysis on the possible sources of uncertainty is given in [9]

A EfSect of High-frequency Components

The rms-power of the quantization noise of the n-bit quasi- sine waveform is given by APnojSE=(2(~21+)3)P~ where P o represents the power of the fundamental frequency In the case of a 10-bit DA converter the contribution of quantiza- tion noise is estimated to be ltlo-7 The resolution in the time axis is 104 if we take 1 kHz and 10 MHz for fundamental and sampling frequency respectively Thus the contribution from sampling noise is much smaller than the quantization noise

On the other hand a dead-time of -10 ns is inserted bet- ween the pulse trains at every 100 ns During the dead-time no voltage appears at the output The rms noise power due to the periodic dead-time is in the order of 10-4 which can be re- duced to ltlo-8 by a second-order low-pass filter with cut-off frequency of 1 MHz The loss of power of the fundamental 1 kHz components due to the filter is in the order of 10-12

B Influence of Room Temperature Johnson noise

When the output voltage from the RSFQ-DA is measured by a room-temperature detection circuit the signal to noise (SN) ratio of the voltage measurement is determined by the equivalent noise resistance Rlocrci and noise temperature T of the detection circuit The rms noise voltage is given as Vnoise=d(4kTBRloud) Here B is the equivalent bandwidth of the measurement and k is the Boltzmann constant

3564

Also the thermal noise current (Znoise) from the room-tem- perature detector may upset the measurement if the noise cur- rent exceeds the width of the voltage step (Zyep-I00 PA) of the RSFQ-DA The peak-to-peak value of the noise-current is given as Zise=1(32kTBRload) Thus the optimum values for the equivalent input resistance Rload are within a range from 100 52 to 10 k52 in which both the SN ratio of gtIO7 and the noise margin of gt 104 are realized

C Effect of the Output Cable

When the output voltage from the RSFQ-DA is measured by a detector at room temperature the length of the output ca- ble becomes of the order of 1 meter If the input impedance Rbad of the detector is relatively low (=I kn) the lead-resist- ance of the output cable (=O 1 Qm) can contribute to a error of IO-Ym due to the voltage drop by the load current

Similarly when the output of the RSFQ-DA is compared to a standard voltage source (Vx at room temperature the voltage drop AVmeas due to the cable is calculated as AVmeus=(RdR~d)AVX Here Rp is the resistance of the cable and AVx is the in-phase component of the voltage difference between the RSFQ-DA and the voltage source Hence by ad- justing the voltage difference AVx to lt01 the error due to the resistance in the output cable may be reduced to ltIO-7 Contribution from the parasitic inductance L and capacitance C of the cable is calculated as d L C which is of the order of 10-9 at the test frequency of 1 kHz Thus all the sources of error in measuring the rms value of the sinusoidal waveform generated by RSFQ-DA can be reduced to less than one part in 107

Iv RESULTS AND DISCUSSION

A four-stage (x4) VM has been fabricated using HYPRES standard technology in order to examine the effectiveness of the new design The measured I-V characteristic of the VM circuit is shown in Fig 7 The data V shows the depend- ence of the output voltage on the SQUID-bias current [bias The region where V coincides with 4Vi corresponds to the operating region where the SQUIDs are phase-locked to the JTL From the measured operating region the margins of Zhjay are measured to be +20 at the input frequency of 16 GHz (corresponding to V =O 14 mV) The operation of the four-stage VM has been verified at higher frequencies up to 45 GHz

The prototype four-bit RSFQ-DA is under fabrication at ETL using the standard process-technology of ETL which features NbAIOxNb junction Si02 insulation and Pd resis- tor The design values of the critical current density of the junction J and the sheet resistance R are 14 kNcm2 and 12 R respectively

The practical application of the ac voltage standard re- quires generation of 1 kHz 100 mV sine wave with more than IO-bit resolution At a 10 GHz internal clock frequency

~

panese)

03 $ lamp 02 E

3

v

c

01

00 015 020 025 030 035 040

Bias Current Ihjcrs (mA)

Fig 7 Dependence of input voltage Vin and output voltage V on bias cur- rent [bias The region where V coincides with 4Vin corresponds to the phase-locking region between the JTL and the SQUIDS

a 12-bit DA converter can generate an output amplitude up to 85 mV From the results of the simulation and the experi- ment it should be possible to implement a 12-bit RSFQ-DA on a single chip using the present process-technology

The RSFQ-DA is more complex compared to the binary- type DA converter and the pulse-driven DA converter but do not require complex and expensive semiconductor microwavt circuits We believe that the RSFQ-DA provides another practical approach to realize the ac voltage standard with Josephson accuracy

REFERENCES

[ l ] C A Hamilton C J Burroughs and R L Kautz Josephson DA converter with fundamental accuracy IEEE Trans Instrum Meas vol IM-44 pp 223-225 1995

[2] S P Benz and C A Hamilton Pulse-driven programmable Jo- sephson voltage standard Appl Phys Lett vol 68 pp 3171- 3173 1996

[3] S P Benz C A Hamilton C J Burroughs and T E Harvey Ac and dc bipolar voltage source using quantized Pulses IEEE Trans Instrum Meas Vol 48 No 2 1999 (to be published)

[4] K K Likharev and V K Semenov RSFQ logichemory fami- ly a new Josephson-junction technology for sub-teraherz-clock- frequency digital systems I IEEE Trans Appl Supercond vol 1 pp 3-28 March 1991

[5] V K Semenov Digital to analog conversion based on process- ing of the SFQ pulses IEEE Trans Appl Superconductivity

[6] C A Hamilton Josephson voltage standard base on Single- Flux-Quantum voltage multipliers IEEE Trans Instrum Meas

vol 3 pp 2637-2640 1993

vol 2 pp 139- 142 1992 [7] PSCANKOWBOY httpllpavelphysicssunysbedulRFSQl [8] D L Meier J H Kang D L Miller J X Przybysz and A H

Worsham Single flux quantum pulse amplifier in Extended Ab- stracts of ISEC93 Boulder Colorado 1993 pp 100-101

[9] H Sasaki S Kiryu and A Shoji Uncertainties in ac voltage measurements using Josephson DA converters Bulletin of the Electrotechnical Laboratory vol 62 pp 1-1 I 1398 (in Ja-

3564

Also the thermal noise current (Znoise) from the room-tem- perature detector may upset the measurement if the noise cur- rent exceeds the width of the voltage step (Zyep-I00 PA) of the RSFQ-DA The peak-to-peak value of the noise-current is given as Zise=1(32kTBRload) Thus the optimum values for the equivalent input resistance Rload are within a range from 100 52 to 10 k52 in which both the SN ratio of gtIO7 and the noise margin of gt 104 are realized

C Effect of the Output Cable

When the output voltage from the RSFQ-DA is measured by a detector at room temperature the length of the output ca- ble becomes of the order of 1 meter If the input impedance Rbad of the detector is relatively low (=I kn) the lead-resist- ance of the output cable (=O 1 Qm) can contribute to a error of IO-Ym due to the voltage drop by the load current

Similarly when the output of the RSFQ-DA is compared to a standard voltage source (Vx at room temperature the voltage drop AVmeas due to the cable is calculated as AVmeus=(RdR~d)AVX Here Rp is the resistance of the cable and AVx is the in-phase component of the voltage difference between the RSFQ-DA and the voltage source Hence by ad- justing the voltage difference AVx to lt01 the error due to the resistance in the output cable may be reduced to ltIO-7 Contribution from the parasitic inductance L and capacitance C of the cable is calculated as d L C which is of the order of 10-9 at the test frequency of 1 kHz Thus all the sources of error in measuring the rms value of the sinusoidal waveform generated by RSFQ-DA can be reduced to less than one part in 107

Iv RESULTS AND DISCUSSION

A four-stage (x4) VM has been fabricated using HYPRES standard technology in order to examine the effectiveness of the new design The measured I-V characteristic of the VM circuit is shown in Fig 7 The data V shows the depend- ence of the output voltage on the SQUID-bias current [bias The region where V coincides with 4Vi corresponds to the operating region where the SQUIDs are phase-locked to the JTL From the measured operating region the margins of Zhjay are measured to be +20 at the input frequency of 16 GHz (corresponding to V =O 14 mV) The operation of the four-stage VM has been verified at higher frequencies up to 45 GHz

The prototype four-bit RSFQ-DA is under fabrication at ETL using the standard process-technology of ETL which features NbAIOxNb junction Si02 insulation and Pd resis- tor The design values of the critical current density of the junction J and the sheet resistance R are 14 kNcm2 and 12 R respectively

The practical application of the ac voltage standard re- quires generation of 1 kHz 100 mV sine wave with more than IO-bit resolution At a 10 GHz internal clock frequency

~

panese)

03 $ lamp 02 E

3

v

c

01

00 015 020 025 030 035 040

Bias Current Ihjcrs (mA)

Fig 7 Dependence of input voltage Vin and output voltage V on bias cur- rent [bias The region where V coincides with 4Vin corresponds to the phase-locking region between the JTL and the SQUIDS

a 12-bit DA converter can generate an output amplitude up to 85 mV From the results of the simulation and the experi- ment it should be possible to implement a 12-bit RSFQ-DA on a single chip using the present process-technology

The RSFQ-DA is more complex compared to the binary- type DA converter and the pulse-driven DA converter but do not require complex and expensive semiconductor microwavt circuits We believe that the RSFQ-DA provides another practical approach to realize the ac voltage standard with Josephson accuracy

REFERENCES

[ l ] C A Hamilton C J Burroughs and R L Kautz Josephson DA converter with fundamental accuracy IEEE Trans Instrum Meas vol IM-44 pp 223-225 1995

[2] S P Benz and C A Hamilton Pulse-driven programmable Jo- sephson voltage standard Appl Phys Lett vol 68 pp 3171- 3173 1996

[3] S P Benz C A Hamilton C J Burroughs and T E Harvey Ac and dc bipolar voltage source using quantized Pulses IEEE Trans Instrum Meas Vol 48 No 2 1999 (to be published)

[4] K K Likharev and V K Semenov RSFQ logichemory fami- ly a new Josephson-junction technology for sub-teraherz-clock- frequency digital systems I IEEE Trans Appl Supercond vol 1 pp 3-28 March 1991

[5] V K Semenov Digital to analog conversion based on process- ing of the SFQ pulses IEEE Trans Appl Superconductivity

[6] C A Hamilton Josephson voltage standard base on Single- Flux-Quantum voltage multipliers IEEE Trans Instrum Meas

vol 3 pp 2637-2640 1993

vol 2 pp 139- 142 1992 [7] PSCANKOWBOY httpllpavelphysicssunysbedulRFSQl [8] D L Meier J H Kang D L Miller J X Przybysz and A H

Worsham Single flux quantum pulse amplifier in Extended Ab- stracts of ISEC93 Boulder Colorado 1993 pp 100-101

[9] H Sasaki S Kiryu and A Shoji Uncertainties in ac voltage measurements using Josephson DA converters Bulletin of the Electrotechnical Laboratory vol 62 pp 1-1 I 1398 (in Ja-