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IEE5687INTRODUCTION TO VLSI/SOCPHYSICAL DESIGN AUTOMATION

Iris Hui-Ru Jiang Spring 2008

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Administrative Matters

Time/location: 4GHY@ED022Instructor: Iris Hui-Ru JiangEmail: hrjiang@faculty.nctu.edu.twOffice: ED540, ext. 31211Office hours: 5X (made by appointment)

Teaching assistants: Email: mcwu@eda.ee.nctu.edu.twLab: ED413, ext. 54226Office hours: 4EF (made by appointment)

URL: http://eda.ee.nctu.edu.tw/hrjiang/courses/pd08/ Prerequisites: data structures (or algorithms) & logic design

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Course Objectives

Study techniques/algorithms for physical designConvert a circuit description into a geometric descriptionStudy nanometer process/electrical effects and their impactson the development of physical design toolsHave fun!

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Intended Audience

VLSI CAD students in particular for physical designCAD: computer-aided designEDA: electronic design automation

Automate VLSI design processCircuit designers to understand how tools work behind the scene,

not just using themProcess engineers to tune process that is more circuit/physicaldesign friendlyMathematical/Computer Science majors to find tough problems

Lots of physical design problems can be formulated intocombinatorial optimization or mathematical programmingproblemsActually, most CAD problems are NP-complete heuristics

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Reading Materials

Required text: Any of the following two books:S. M. Sait and H. Youssef, VLSI Physical Design Automation: Theory and Practice , World Scientific Publishing Co., 1999.N. Sherwani, Algorithms for VLSI Physical Design Automation ,3 rd Ed., Kluwer Academic Publishers, 1999.

References:Selected reading materials from recent publicationsChang, Chen, and Chen, Physical design for modern VLSIdesign, in Essential Issues in SOC Design , Springer, 2006.Chang and Chen, Packing floorplanning representations, to

appear in Physical Design Handbook , CRC Press, 2008.

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Course Outline

IntroductionPhysical design processesPartitioningFloorplanningPlacement

Routing (global, detailed, clock, and power routing)Post-layout optimization

Emerging topicsSignal/power integrity

Timing issuesDesign methodologyDesign for manufacturability & reliability

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Grading Policy

Grading:Homework: 20% + Quizzes (on homework due days): 5%Programming assignments: 30%Final exam (open-book, open-note): 25% ( June 12 )Term project (presentation + demo): 20% ( June 19 )

Class participationHomework & programming assignments:

No late submission (partial solutions may get partial credits)Project: 13 person teamwork (preferably 2 persons)

Default: Problems B1, B2, or B3 of 2008 MOE IC/CAD Contest5% bonus for completion and submission to the contestA 1- or 2-page project proposal is due on May 1

Bonus for class participation: call names and ask questionsNo credits for plagiarism

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