Overview of SINAP Timing System

Overview of SINAP Timing System

Electronics Group

Beam Diagnostics & Control Division

SINAP

束测控制部电子学组

Electronics Group, Beam Instrumentation & Control DivisionElectronics Group, Beam Instrumentation & Control Division

Outline

• v1 timing system structure

• v1 hardware

• v1 performance

• v1 in PLS-II

• v2 timing system structure

• v2 hardware



SINAP v1 timing system structureEVG

FANOUT

FANOUT

EVR EVR EVR EVR

E/O

O/E

TTB E/O

O/E

TTB

BeamDevices

O/E

Device Device Device

OM3 fiber

OM3 fiber

OM3 fiber OM3 fiber OM3 fiber

Plastic fiiber Plastic fiiber Short coaxial cable

Short coaxial cable

EVR

O/E

Device

Multimode fiber

O/E

Device

Short coaxial cable

Short coaxial cable

Short coaxial cable

FANOUT FANOUT

BeamDevices

O/E

O/E

is single mode O/E

is multimode O/E



Hardware List

• SINAP v1 timing system: EVG

EVR

FANOUT

TTL VME Transition Board

Plastic fiber VME Transition Board

Multimode fiber O/E

Plastic fiber O/E



EVG

VME 6U module; A16D32 addressing

Input: 1ch RF clock (0 – 10 dBm)

1ch AC line (3Vp-p typical)

Output: 1ch multi-mode fiber

1ch Sequence RAM trigger

(TTL)



EVR

VME 6U module; A16D32 addressing

Input: 1ch multi-mode fiber

1ch interlock input (TTL)

Output: 3ch TTL trigger/clock

3ch LVPECL trigger/clock

1ch CML RF recovery clock

2ch Multi-mode fiber trigger



FANOUT

VME 6U module

Input : 1ch multimode fiber

Output: 12ch multimode fiber



TTL VME Transition Board

VME transition board

Output: 14ch TTL trigger



Plastic Fiber VME Transition Board

VME transition board;

Output: 14ch optic trigger

(Agilent HFBR-1528)



Multi-mode Fiber O/E

Standalone module


1ch power supply (24V/1A)

Output: 1ch TTL (50ohm)



Plastic Fiber O/E

Standalone module


1ch power supply (24V/1A)

Output: 1ch TTL



Performance Testing

• Stabilitycoding-decoding error

RF clockAC line

EVG outputEVR output

fiberVMEchassis

EVGEVRcounter



Performance Testing

• JitterEVR TTL output

< 6ps



Performance Testing

• JitterMulti-mode O/E output

< 10ps



MRF Jitter Performance

• EVR TTL output > 18ps



Performance Testing

• Phase ShiftPhase shift with temperature changing (35ps/ )℃



v1 in PLS-II

in LINAC control room

in RF station (EVG)



v1 in PLS-II

in Klystron & Modulator

in E-gun



V1 in PLS-II

in Storage Ring

in Kicker station



SINAP v2 timing system structuremaster clock

VME-EVO (EVG)

VME-EVO (FANOUT)

VME-EVO (EVG)

PLC-EVR PLC-EVR

VME-EVO(EVR)

VME-EVO(EVR)

VME-EVO (FANOUT)VME-EVE PLC-EVR

VME-EVE VME-EVE

master clock

STD-OE STD-OE



System Design

• SynchronizationBroadcasting mode

Fiber

parallel toserial

8B10B

master clock

encodingtransistor

Switch

serial toparallel

clockextraction recovery

clockreceiver

decoding

EVR

divider

event

referenceclock

divider

trigger

clock

8B10B



System Design

• Deterministic Data TransferSwitching mode

serial toparallel

8B10B

receiver

decoding

EVR

address &data

parallel toserial

8B10B encoding

tran

sist

or

address &data

EVR

Switc

h



System Design

• Frame Format

1 byte for trigger code

1 byte for data frame

The minimum interval of trigger is 8ns (2.5Gbps).

trigger data frame

data frame

data frame

data frame

data frame

data frame

K28.5

K28.5

K28.5

trigger

K28.5

... ...

1 byte 1 byte



System Design

• Data Frame Format

4 bytes for address; 8 bytes for data; 1 byte for K28.3

The maximum data transfer rate is 76.9MB/s (2.5Gbps)

address data

4 byte 8 byte

K28.3

1 byte



Hardware list

• SINAP v2 timing system: VME-EVO

VME-EVE

PLC-EVR

STD-OE



VME-EVO

Configured to EVG, EVR and FANOUT by software

VME 6U module, A16D32 addressing

Input: 1 RF clock (0 – 10dBm)

1 interlock / AC-line (TTL)

1 fiber (SFP module)

Output: 8 fiber (SFP module)



VME-EVO

• Configure to EVG

GTXSFPuplink

event FIFO data FIFO

EVG logicAC lineRF clock

GTX0

data Switching

SFP0

GTX1

SFP1

GTX7

SFP7

……

……

Recovery clock

downlink



VME-EVO

• Configure to FANOUT

GTXSFPuplink

dataswitching

GTX0

SFP0

GTX1

SFP1

GTX7

SFP7

……

……

Recovery clock

downlink



VME-EVO

• Configure to EVR

GTXSFPuplink

EVR logic data logic

GTX0

SFP0

GTX1

SFP1

GTX7

SFP7

……

……

Recovery clock

STD-OE STD-OE STD-OE……



VME-EVE

Configured to EVR

VME 6U module, A16D32 addressing

Input: 1 interlock (TTL)

1 fiber (SFP module)

Output: 8 outputs (TTL)

1 RF recovery clock



VME-EVE

GTXSFPuplink

EVR logic data logic

GTX0

finedelay

GTX1

finedelay

GTX7

finedelay

……

……

Recovery clock

……TTL TTL TTL

GTX8

RFtransformer

RF



VME-EVE

• RF recovery clock

0x003ff -> event clock

0x03c1f -> 2x event clock

0x18c63 -> 4x event clock

…

20-bi t data

X20

paral l el toseri al

RFtransformer

GTX

event cl ock



VME-EVE

• RF delay

(0,0,0xfffff,0xfffff) -> (0,0x1,0xffffe,0xfffff)

1/20 event clock delay

(Synchronized with RF clock)

00 low X20

parallel toserial

CML to TTL

GTX

event clock

01 falling-edge

10 rising-edge

11 high

SRC & SRC_DOTP(n)

dbus(n)



PLC-EVR

Yokogawa FAM3 series, 1-slot module

Input/Output register mode

external 5V/3A DC power supply is required

Input: 1 fiber (SFP module)




STD-OE

19 inches 1U standard chassis

110/220V 50-60Hz AC power supply

Input: 4 fiber (SFP module)


Overview of SINAP Timing System

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