oral defense ppt

A Neuron Emulator and Headstage Circuit for Patch Clamp Setups

2012/7/30吳彥徵 (Yen-Chen Wu)

Advisor: Prof. Robert Rieger

Outline

• Introduction• Objectives & Features• Circuit Design and Simulated Results• Hardware Implementation• Conclusions and Future Work

Introduction

• Membrane Potential• Hodgkin-Huxley Model• Voltage Clamp & Patch Clamp Techniques

Cell

type

RP

(mV)

AP

increase

(mV)

AP

duratio

n (ms)

Threshold

potential

(mV)

Neuron axon

hillock −70 ~ −90 110 0.75 -55

Membrane Potential

AP of neuron axon hillock

Actively Passively

Positive

Negative

Spike train

Hodgkin-Huxley Model

Voltage Clamp & Patch Clamp Techniques

Outline


Objectives & Features

Outline


Circuit Design and Simulated Results

• Neuron Emulator Specification and Headstage CircuitCell Model with AP Generation Simplified Model for the Neuron Cell Simplified AP Generator

• Headstage AmplifiersNeuron Emulator in C_CNeuron Emulator in V_C

• Comparison with CV-7B HeadstageCV-7B Headstage in C_CCV-7B Headstage in V_C

Neuron Emulator and Headstage Circuit Specification

Membrane model AP model Threshold range Voltage sources Electrode Headstage

Rm Cm τm Rap Cap τap Vth fap Vspike Vrest Re Iclamp

5

MΩ

10

pF

0.05

ms

5

KΩ

1

μF

5

ms

-60~-30

mV

1~10

Hz

20

mV

-90

mV

22

MΩ

6~12

nA

Size τap

Speed

Vp-p

Cell Model with AP Generation (1)

)()1)(()1)((1

2

1

2

43

4

1

2

43

4

RRV

RR

RRRV

RR

RRRVV KrestNaap

KNarest VVV

Na K

adder

4321 RRRR

Na

K

Bigger

Bigger

Simplified Model for the Neuron Cell

Switch phase Time constant Voltage sources

φde φre τNa τK VpK VpNa Vrest

High Low 0.05 ms 0.15 ms32 mV 72 mV 0 V

Low High 0.25 ms 0.45 ms

linear

nonlinear

φde

φre

slower

Simplified AP Generator(1)

Membrane model AP model Voltage sources Electrode

Rm Cm τm Rap Cap τap Vspike Vrest Re

5 MΩ 10 pF 0.05 ms 5 KΩ 1 μF 5 ms 20 mV -90 mV 22 MΩ

SmallerBigger

Simplified AP Generator(2)

ap

t

restspikemclamprestclamp eVVRIVV

)(:apφmclamprestclamp RIVV :rφ

φap

φr

Iclamp = 8 nA

Iclamp = 0 nA

Pre-chargeDischarge

Bigger

Headstage Amplifiers

Current Clamp Amplifier

Voltage Clamp Amplifier

AdderIntegratorHPF

Neuron Emulator circuit for current clamp experimentcurrent clamp experiment.

m

restclamp

e

clampeclamp R

VVRVV

I

mclamprestclamp RIVV

of

ifI R

RA

Shaded areas will be implemented on a microcontroller(see Appendix A)

Neuron Emulator parametric analysis circuit simulation results in C_C

Condition Iclamp = 10 nA, fap = 6.25 Hz, τap = 5 ms

Probe point Vclamp Ve

Vpp

Vm~VM

110 mV

-40~70 mV

110 mV

180~290 mV

Condition Vth = -60 ~ -30 mV → Iclamp = 6 ~12 nA, τap = 5 ms

Iclamp 5 nA 6 nA 12 nA 13 nA

Vclamp

-65 mV-60 mV -30 mV

-25 mVVrest

Vap / Vm~VM -60~50 mV -30~80 mV

Vpp 0 V 110mV 0 V

fap 0 Hz 1 Hz 10 Hz 0 Hz

1Hz10Hz

Neuron Emulator for voltage clamp experimentvoltage clamp experiment.

Shaded areas will be implemented on a microcontroller

(see Appendix A)

apclamp

eap

t

eclampe

QQ

dtRIRIRC

)(1

0int

eapeclampclampe RIRIVV m

eV R

RA

Neuron Emulator parametric analysis circuit simulation result in V_C

Iclamp = 10 nA, fap = 6.67 Hz, τap = 5 ms

Qap

110 pC 2.42 mV

T

apdtV0

Condition τap = 5 ms

Vrest / Vclamp-65 mV -60 mV -30 mV

2.42 mV

Qap110 pC

Iclamp5 nA 6 nA 12 nA

fap0 Hz 1 Hz 10 Hz

T

ap dtV0

apapm

t

restspikeap CR

ReVV

Qap

)(

T

ap dtV0

Comparion with CV-7B Headstage

O C

O

C

Ie = If = Vcmd / Rf.

Vp – Vo = If ·Rf

CV-7B Headstage in C_C

Condition τap = 5 ms, T = 200 ms

Iclamp = If 1 nA 6 nA 12 nA

Vcomd50 mV 300 mV 600 mV

Vp = Ve (Vm~VM) -65~45 mV 70~180 mV 235~345 mV

Vclamp -85~25 mV -60~50 mV -30~80 mV

Vpp 110 mV

CV-7B Headstage in V_C

Condition τap = 5 ms, Vp = -60 mV, Iclamp = 1.2 nA

Ve = Vp -60 mV

Vrest = Vclamp Vpp = 110 mV, spike:-85~25 mV

Iclamp Ipp = 5 nA, 1.1~-3.9 nA

110mV / 22Mohm=5nA

22Mohm

Outline


Hardware Implementation

• Choice of ComponentsMicroprocessor Programming

• Printed Circuit Board Operation• Experimental Results

Results of Current Clamp ModeResults of Voltage Clamp Mode

• Results of Neuron Emulator Mode for CV-7B HeadstageCV-7B Headstage in C_CCV-7B Headstage in V_C

• Comparison

Choice of Components

Oscilloscope function

AP Generator

Headstage

KAI 1

1VVAv /4.4

Microprocessor Programming






• Comparison

Printed Circuit Board Opearation

Mode/Switch C_C V_C

Current clamp mode 1 0

Voltage clamp mode 0 1

Neuron emulator mode 0 0

15 x 10 cm2






• Comparison

Results of Current Clamp ModeVclamp (CH1), Ve (CH2), φap (CH3) as the clamp current Iclamp is varied.

Iclamp = 0 nA

-63mV

-30mV

Vpp,Avg=80~90 mVVpp,Max=102 mV

Results of Voltage Clamp Mode

dtIRVV

R

dtCHCH

ap

t

e

clampe

e

t

)()21(

0

0

tRVV

e

clampe

ap

t

ape

m QdtVR

tftf 0

11)()(

Vpp=330mV / 4.4V/V=75mV

f=2.481Hz

400pC / 5=80pC






• Comparison

CV-7B Headstage in C_C

Voffset=-95.69 mV

Vpp=85 mV→Cp=5 pF

Stop!

Vp=Ve=315.8mV

If=Iclamp=12nA

CV-7B Headstage in V_C

Voffset=-95.69 mV

Ipp=3.6 nA

Ipp X Re=79.2 mV

f=2.5Hz

Close to C_C result, 85mV






• Comparison

Comparison (1)

A Neuron Emulator Headstage Circuit for Patch Clamp Setups A Neuron Emulator for Single-Electrode Settings [21]

Components Power supply voltage (V) Components Power supply voltage (V)

PIC18F4550 0 ～ 3.5 PIC18F2520 -1.5 ～ 1.5

TL082 0 ～ 9 -2.5 ～ 2.5

ADC in PIC 1.55 ～ 3.35 -0.1 ～ 1.5

CD14016BE 0 ～ 3.5 -2.5 ～ 2.5

Battery 0 ～ 9

Hedstage

LF355N 0 ～ 9

LM334 0 ～ V+

LM317 0 ～ 9

Electrode Membrane model Action potential model Low-pass filter

Re Rm Cm τm Rap Cap τap Rlpf Clpf τlpf

A Neuron Emulator

for Single-Electrode Settings [21]22 MΩ 5 MΩ 10 pF 0.05 ms

5 MΩ 1 nF

5ms

26 KΩ 10 μF 260 ms

A Neuron Emulator Headstage Circuit

for Patch Clamp Setups5 KΩ 1 μF

Comparison (2)

Priceless

Portable

Energy

Saving

Functionality

Outline


Conclusions and Future Work

• Provide the passive and active electrical properties passive and active electrical properties of a neuron as seen

from a single electrode.

• Each AP generates a well defined charge 110 mV, 110 mV, ττapap=5ms=5ms. The AP firing

rate from 1 Hz to 10 Hz1 Hz to 10 Hz is dependent on the RP level in the threshold

range from -60 mV to -30 mV-60 mV to -30 mV.

• Measured results confirm the circuit design is in agreement with the

simulation results by Cadence software.

• The headstage circuit is implemented for providing the clamp current to

observe the voltage and current properties of the neuron emulator.

Continue the development of neural oscillator project.

Make the achievements of the thesis realized in a chip (ASIC).

Appendix A. Equivalent circuits representing the function provided by the microcontroller

A1. 2nd - LPF

A2. VCO

A3. Threshold Comparator

2nd - LPF

21212221

2

2121

22

2

1)11(

1

))(()(

lpflpflpflpflpflpflpflpf

lpflpflpflpf

oo

o

CCRRs

RRRRs

CCRR

sQ

s

GsH

)/(062832.01

2121

sradCCRR lpflpflpflpf

o 31.0)( 121

2121

lpflpflpf

lpflpflpflpf

CRR

CCRRQG = 1

0.01

Filter

VCO (1)

Shifting Amplifier VCO

Vrest Vconst. Vf gm Cf Vctrl fap

-60~-30 mV 63.3 mV 3.3~33.3 mV 0.09 μ 100 pF 3 V 1~10 Hz1Ω

.constrestf VVV

ctrlf

mfap VC

gVf

VCO (2)

1Hz10Hz 5Hz

Threshold Comparator

Double Comparator

Input

And Gate

Input

Multiplexer

Control InputVm

Vrest V≧ thH 01 0 Vrest

VthL ＜ Vrest ＜ VthH 11 1 Vclamp

Vrest V≦ thL 10 0 Vrest

A Neuron Emulator and Headstage Circuit for Patch Clamp Setups

Yen-Cheng [email protected]

Electrical Engineering DepartmentNational Sun Yat-Sen University

Taiwan

Thank you for your attention!Thank you for your attention!

mailto:[email protected]

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