Op Amp Design
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Transcript of Op Amp Design
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EECS 170C Lecture Week 1
Spring 2014 EECS 170C
Prof. M. Green / U.C. Irvine
1
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Lowpass Filter Example
R1 =1 k
R2 =1 k
C2 =1 pF
Vin
Voutideal op-amp
Av =R2R1
= 1
f3dB =1
2 C2R2=159 MHz
From standard circuit analysis:
Spring 2014 EECS 170C
2 Prof. M. Green / U.C. Irvine
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R1
R2
C2
Vin
Voutideal op-amp
Lowpass Filter Design
Av = 2
f3dB = 500 MHz
Specifications:
Av =R2R1
= 2
f3dB =1
2 C2R2= 500106
2 equations with 3 unknowns not a unique solution!
Spring 2014 EECS 170C
3 Prof. M. Green / U.C. Irvine
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Capacitors should be no larger than 1 pF:
Set C2 = 1 pF
R2 = 318
R1 = 159
Additional constraint #2: For f > f3dB, magnitude should exhibit -40 dB/decade rolloff:
f
H j( )
f3dB
-20 dB/decade
R1
R2
C2
Vin
Vout
The given circuit topology cannot satisfy this constraint.
Additional constraint #1:
Spring 2014 EECS 170C
4 Prof. M. Green / U.C. Irvine
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R1
R2
C2
Vin
Vout
C1
R3
H s( ) = R2R1 + R3
11+ sC1 R1 || R3( )[ ] 1+ sC2R2( )
Additional constraint #3: Under the condition that Rs and Cs vary randomly within 10%, f3B should vary no more than 5%
This constraint is impossible to meet for any RC filter!
2nd-order filter topology (2 capacitors) needed:
Spring 2014 EECS 170C
5 Prof. M. Green / U.C. Irvine
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Replace resistors with triode-biased MOSFETs with gates controlled by dc voltage VG, realizing electrically controllable resistors. Critical frequencies can be controlled by VG.
Vin Vout
VG
Possible solution #2:
Replace resistors with configuration consisting of capacitor and switches, with switches controlled by clock signal with period Tc. Critical frequencies are determined by Tc and capacitor ratios. Critical frequencies can be controlled by Tc.
Vin Vout
Possible solution #1:
Spring 2014 EECS 170C
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Aspects of Design (Synthesis)
Desired behavior & specifications are given; component values & circuit topology are not.
Solution is usually found iteratively: An initial circuit is proposed and analyzed. If specifications are not met, the circuit is modified and re-analyzed.
There is usually not a unique solution that satisfies the specifications. However, each solution exhibits its own set of tradeoffs (e.g., size, cost, robustness) that must be considered.
It may not be possible to meet all of the specifications simultaneously using a given technique or technology.
Spring 2014 EECS 170C
7 Prof. M. Green / U.C. Irvine
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Analog vs. Digital Signal Representation
Analog representation:
Precision in specifying and measuring voltage signal is determined by random noise generated by circuit components. Dynamic Range is determined by ratio of maximum amplitude (usually determined by supply voltage) and noise level.
Digital representation:
Dynamic Range in specifying and measuring digital signal is determined by number of bits used in representing the signal.
Spring 2014 EECS 170C
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a3 a2 a1a0
16 possible digits Dynamic Range = 16
Prof. M. Green / U.C. Irvine
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Continuous vs. Discrete Methods of Timing
Continuous-time signaling:
Voltage signal is defined at any arbitrary instant of time. There is no limit on the highest frequency that can be generated or measured.
Discrete-time signaling:
Voltage signal is defined only at discrete values of time kT, where k is an integer. The highest frequency that can be observed is 1/2T the Nyquist frequency.
Spring 2014 EECS 170C
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Passive Components
PD = I V = I 2R 0Power dissipation in a resistor:
Components that always dissipate power are said to be passive.
PS =VS2
RS + RLPower supplied by VS:
PL = VS RL
RS + RL#
$ %
&
' (
2
1RL
Power dissipated in RL:
PLPS
=RL
RS + RL< 1Power gain:
Power amplification is impossible if only passive components are present. Spring 2014 EECS 170C
10 Prof. M. Green / U.C. Irvine
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Active Components A component that is not passive is said to be active.
PLPS
= A2 rin
2
RS + rin
RLRL + rout( )
2
A2 rinRL
(assuming rin >> RS , rout
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Discrete Circuit Realized on a Printed Circuit Board (PCB)
Spring 2014 EECS 170C
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Integrated Circuit on a Monolithic Substrate
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Circuit Realization: Discrete vs. Monolithic
Each component takes roughly the same area on the board independent of its value.
Passive components can be chosen to a desired accuracy, subject to cost.
Most circuit nodes can be observed for testing and verification.
Dimensions on order of cm.
The area of a component is directly related to its value.
Individual component values exhibit large variances; however, like components with identical geometries in close proximity exhibit very close matching (
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Example of Matching Design an amplifier with an accurate gain of +10: Assume Av can take values between 10,000 and 50,000.
V+ = Vin
V = Vout R2
R1 + R2
Vout = Av V+ V( )
VoutVin
=1
1Av
+1
1+ R1 R2
Very small depends only on resistor ratio
Let R1 = 9k , R2 = 1k:
Av = 10,000 Vout /Vin = 9.990
Av = 50,000 Vout /Vin = 9.998 independent of individual resistor values
Spring 2014 EECS 170C
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X
X
X
1. Die Size
Manufacturability of ICs
Spring 2014 EECS 170C
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2. Power Dissipation Power dissipated in the IC is converted to heat, raising the temperature of the die & package. Elevated die temperature can degrade circuit performance or even permanently damage the silicon. To accelerate heat removal, a heat sink may need to be used, requiring more space.
Passive heat sinks Active air-cooling heat sink
Spring 2014 EECS 170C
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3. Robust Design IC must operate properly in the presence of variations in: Processing in fabrication technology
Individual component values can vary 15% or more Voltage supply
Supply voltages can vary 10% Temperature
Circuit should operate to spec at 0--70 C ambient temperature
PVT
Spring 2014 EECS 170C
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Prof. M. Green Univ. of California, Irvine
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FIES eVX VT 1( ) IES e VinVout( ) VT 1$ % &
' ( ) = 0
KCL at Vout:
(2F ) eVX VT 1( ) + 1R VX VCC( ) = 0KCL at VX:
Use of Approximation
19 Spring 2014 EECS 170C
Prof. M. Green / U.C. Irvine
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My Research
The operation of real high-speed clock dividers is more complex
Spring 2014 EECS 170C
1. High-speed frequency divider:
Prof. M. Green / U.C. Irvine
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Spring 2014 EECS 170C
21
Clock divider based on CML D flip-flop:
Divider sensitivity curve:
Vmin = minimum input clock amplitude required for correct operation. (function of input frequency)
fso = self-oscillation frequency
Vmax = maximum dc differential voltage that can be applied to the input clock for which the circuit self-oscillates.
DLW
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DLW
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LLW
!"
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LLW
!"
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&
CLW
!"
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&
CLW
!"
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&
CLW
!"
#$%
&
LLW
!"
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&
LLW
!"
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&
DLW
!"
#$%
&
DLW
!"
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&
CLW
!"
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&
Vmax
Prof. M. Green / U.C. Irvine
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Spring 2014 EECS 170C 22
Divider chip photograph
Measured sensitivity curves: a) Conventional (DFF) divider b) Modified regenerative divider c) Ring oscillator divider
Designed at Broadcom using 0.13 m CMOS process; shunt-peaking was used.
Divider test chip measurements
Prof. M. Green / U.C. Irvine
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Normally the equalizer and CDR are designed and implemented as separate blocks. Common elements in each of the two blocks can be iden?ed and combined...
Spring 2014 EECS 170C
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2. Equalization of broadband receivers:
Prof. M. Green / U.C. Irvine
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Circuit Details Shunt-peaking CML summer. 2-stage shunt-peaking CML slicer. Dieren?ally-tuned LC VCO. Re?mer generates low-ISI re?med data.
DFF1 V-I
Recovered clock
DFF3
DFF2 DFF5
DFF4
Input Data+
+
-
a1 a2 a3
--
a0
Retimed DataRetimer
Rp
Cp C2
L1
2mA
R1R1
L1 L2
4mA
R2R2
L2
V1
OUTNR
L L
R
AP OUTP
V2V0 V3
ANBP BN CP CN DP DN
VCO
Summer
Slicer
Alexander PD
FB path
Spring 2014 EECS 170C
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Measurement Setup
Die photo. Implemented in Jazz Semiconductor 0.18m BiCMOS Process (only CMOS transistors used).
Anritsu MP1763B
Pattern Generator
OUT_CLK_N
OUT_CLK_P
Anritsu 69137B
Synthesized Signal
Generator
INDATA_N
INDATA_P
RF Clock
HP 83480A
Oscilloscope
Trigger
Clock
OUTDATA_N
OUTDATA_P
Cable
DFE &
CDR
V_UP
V_DOWN
1.8V
Test board
Test setup
Spring 2014 EECS 170C
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Equalizer + CDR Operation (2)
Recovered clock RJ = 2.15 ps rms
Recovered clock RJ = 1.83 ps rms
Re?mer output eye diagram JiXer = 4.14 ps rms
Re?mer output eye diagram JiXer = 4.96 ps rms
2.4 m cable
3.6 m cable
Cable output eye diagram.
Cable output eye diagram.
Spring 2014 EECS 170C
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Spring 2014 EECS 170C
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Din1
Din2
Dout D-FF D Q
Latch D Q
10 GHz
D-FF
D Q
D-FF
D QLatch
D Q
D-FF
D Q
Select
A B
D-FF
D Q
D-FF
D QLatch
D Q
Select
A B
Din3
Din0
Select A B
10 GHz
10 GHz
20 GHz
20 GHz
re?mer
40 GHz
40 GHz 2 PLL 2
20 GHz
10 GHz
4:1 Multiplexer Tree Structure:
2. Equalization of broadband receivers:
Prof. M. Green / U.C. Irvine
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Spring 2014 EECS 170C
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40GHz Dieren?al Push-Push VCO
Resonates at 20 GHz
Virtual ground node
Resonates at 40 GHz
Prof. M. Green / U.C. Irvine
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Spring 2014 EECS 170C
29
Chip Board and Die Micrograph
20 Gb/s inputs
40 Gb/s output 20 GHz clock
625 MHz Reference
clock
40Gb/s Distributed
buffer
40Gb/s MUX and retimer
Push-push differential
VCO
PLL Clock buffers
20Gb/s inputs
40 Gb/s output
20 GHz clock output
Prof. M. Green / U.C. Irvine
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Spring 2014 EECS 170C
30
Measured 40 Gb/s Output
40Gb/s MUX output (Dieren?al) with 450 mV dieren?al peak-to-peak ver?cal eye opening and 1.14 ps rms jiXer
Prof. M. Green / U.C. Irvine