NMOS Fundamentals
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Transcript of NMOS Fundamentals
MOS-SLIDES-AKM 1
MOS DEVICE FUNDAMENTALS
Professor A. K. MajumdarComputer Science and Engineering
Department Indian Institute of Technology, Kharagpur
MOS-SLIDES-AKM 2
Metal-Oxide Semiconductor (MOS) Field Effect Transistors
NMOS enhancement mode transistor
MOS-SLIDES-AKM 3
Induced Channel in NMOS Transistor
Enhancement mode NMOS transistor with VGS>0 showing induced channel
MOS-SLIDES-AKM 4
Current – Voltage characteristics of NMOS transistors
MOS-SLIDES-AKM 5
NMOS Transistor Analysis
• Induced Channel Charge / Unit AreaQ(x) = - COX [ VGS – V(x) – Vth]
Where COX = εOX/ tOX capacitance per unit area due to gate oxide
Drain current IDS = vn(x) Q(x)Wvn(x) = drift velocity of electron
MOS-SLIDES-AKM 6
NMOS Transistor Analysis Contd
• vn(x) = - μn E(x) = μn dV/dx• μn = Mobility of electrons• Hence IDS = - μn Q(x)W dV/dx• Substituting for Q(x),• IDS dx = μn COX W[VGS– V(x) – Vth] dV
Integrating• IDS= μn COX W/L[(VGS - Vth ) - VDS /2 ] VDS• IDS = ηn [(VGS - Vth ) - VDS /2 ] VDS
MOS-SLIDES-AKM 7
NMOS Transistor Analysis in Linear Region
• kn =μn COX = μn εOX/ tOX is called process transconductance parameter
• ηn = kn(W/L) is called gain factor• For small VDS , VDS
2 /2 can be ignored and IDS depends linearly on VDS
• Rlinear = 1/ (ηn (VGS - Vth))
MOS-SLIDES-AKM 8
NMOS Transistor Analysis in Linear Region
• Transconductance of NMOS transistor• gm = (dIDS/ dVGS)│ VDS = constant
In linear regiongm = ηn VDS
MOS-SLIDES-AKM 9
NMOS Transistor Analysis Saturation Region
• VDS ≥ VGS – Vth• Channel is pinched off• Assuming voltage difference over induced
channel from source to pinch off point fixed at VGS – Vth
• IDS = ηn /2 (VGS – Vth)2
• In saturation region, MOS transistor acts as a constant current source.
• Transconductance in saturation region• gm = ηn (VGS – Vth)
MOS-SLIDES-AKM 10
Current – Voltage Relationship of NMOS Transistor
• The drain-to-source current-voltage dependence for a NMOS transistor is given by the following equations
• IDS = 0 for VDS < Vth (off)
• IDS = ηn/2.(VGS – Vth)2 for 0 < VDS – Vth < VDS (saturation)
• IDS = ηn(VGS – Vth – VDS/2)VDS for VGS > Vth and VGS – Vth≥ VDS (linear)
ηn = (μnεox/tox).W/L
where μn is the mobility of electron, εox is the permittivity of the oxide material, and tox is the thickness of the oxide.
MOS-SLIDES-AKM 11
Channel Length Modulation
• In saturation region, the transistor does not operate as a perfect current source, i.e. IDS is not independent of VDS
• As VDS is increased beyond (VGS– Vth) effective channel length decreases.
• Since IDS α 1/L, reduction in effective channel length increases IDS
• More accurate representation• IDS = ηn/2.(Vgs – Vth)2 ( 1 + λVDS)
MOS-SLIDES-AKM 12
Current – Voltage Relationship of PMOS Transistor
• Cut off VGS > VthIDS = 0
• Linear Region: VGS ≤ Vth and VDS > VGS – VthIDS = ηp(VGS – Vth – VDS/2)VDS
• Saturation region VGS ≤ Vth, and VDS < VGS–VthIDS = ηp/2.(VGS–Vth)2
where the gain factorηp = (μpεox/tox).W/L and μp is mobility of holes
MOS-SLIDES-AKM 13
Velocity Saturation
• Electron mobility cannot be considered to be constant with increasing electric field
• For short channel devices velocity saturates
MOS-SLIDES-AKM 14
Velocity saturation effect
• Let VDSAT : drain-source voltage at which the critical field for velocity saturation is reached
• First order approximation:• For VDS < VDSAT, IDS expression is similar to long
channel model• For VDS ≥ VDSAT IDS =IDSAT =
νSAT Cox W [ VGS – Vth – VDSAT/2 ] • Where νSAT =μ VDSAT / L is the saturation velocity
MOS-SLIDES-AKM 15
MOS Transistor Threshold Voltage
• Depletion region charge density - due to fixed acceptor ions in the p-type substrate:
where, Vdep is the voltage across the depletion layer at the oxide silicon boundary
• Channel inversion occurs when Vdep = 2φF
where the Fermi potential φF = kT/q ln( NA/ ni)
• φF ≈ -0.3 V for nMOS
2dep si A depQ q N V= − ε
MOS-SLIDES-AKM 16
Threshold Voltage
• At strong inversion depletion layer charge density:
Where VSB is the substrate bias
With zero substrate bias, threshold voltage
Vth0 = φGC -2 φF - Qdep / Cox - Qi / Cox
where is φGC the work function difference between the gate and substrate (flat band voltage) and Qi is due to impurities at the interface between the gate oxide and silicon substrate
( )2 | 2 |dep si A F SBQ q N V=− ε − ϕ +
MOS-SLIDES-AKM 17
Threshold Voltage
• Threshold voltage with non-zero substrate bias
where the parameter γ is called body-effect (substrate bias) coefficient.
( )0 | 2 | | 2 |th th F SB FV V V= +γ − ϕ + − − ϕ
MOS-SLIDES-AKM 18
Threshold Variations in Short Channel Devices
• Threshold depends on L, W and VDS• Due to depletion regions of the source and reverse-
biased drain junction.• Drain-induced barrier lowering (DIBL) : Vth0 decreases
with increasing VDS . • Very high drain voltage source and drain depletion
regions may get shorted (punch-through)• Narrow channel effects: Vth0 increases since depletion
regions does not abruptly stops at the edges of the transistors but extends to isolating field oxide regions. Gate voltage must support the extra depletion charge to establish conducting channel.
MOS-SLIDES-AKM 19
Sub-threshold / Weak-Inversion Current
• Channel current when VGS < Vth
• IDS (sub-threshold) has exponential dependence on both gate and drain voltages and can be expressed as
)(/ DSGS BVAVkTqSeI +
Slope factor: S - rate of decline of the current with respect to VGS below Vthin mv/ decade( ≈ 2.3 kT/Aq). With A =1, S evaluates to 60mV/decade (i.e. current drops by a factor of ten for a reduction of VGS by 60mv)
usually A<1 and current falls at a reduced rate e.g 90mV/decade
MOS-SLIDES-AKM 20
ReverseReverse--Biased Diode LeakageBiased Diode Leakage
Np+ p+
Reverse Leakage Current
+
-Vdd
GATE
IDL = JS × A
Reverse leakage Current of a p-n junction Ireverse= A JS(e - 1)qVbias/kT
Reverse saturation current Density JS = 10-100 pA/μm2 at 25 deg C for 0.25μm CMOS, JS doubles for every 9 deg C!
MOS-SLIDES-AKM 21
Lateral diffusion of source and drain regions
Lateral diffusion = Ld
Effective channel length Leff = L -2 Ld
MOS-SLIDES-AKM 22
MOSFET Capacitances
Oxide related (Gate ) capacitances: CGS, CGD, CGB
Junction capacitances : CSB, CDB - due to source / drain diffusion regions in the substrate
MOS-SLIDES-AKM 23
MOS transistor gate capacitances for three operating regions
Capacitance Cutoff Linear Saturation CGB CoxW Leff 0 0 CGS Cox W Ld CoxW Ld + ½ CoxW Leff CoxW Ld + 2/3 CoxW Leff CGD Cox W Ld CoxW Ld + ½ CoxW Leff CoxW Ld
MOS-SLIDES-AKM 24
NMOS Inverter
MOS-SLIDES-AKM 25
Pull Up and Pull Down transistors
• The depletion mode transistor is a pull up device. It is always on (Vgs = 0)
• The enhancement mode transistor is the pull down device.
• With no current drawn from output, current in both pull up and pull down transistors must be same.
MOS-SLIDES-AKM 26
Current Voltage Characteristics of NMOS Inverter
MOS-SLIDES-AKM 27
NMOS Inverter• The points of intersection of the pull up (for Vgs =0 )
and pull down curves give points on the transfer characteristics for the inverter
• As Vin exceeds VTpd (pull down transistor threshold) current will flow and Vout falls. Further increase in Vin will cause pull down transistor to be out of saturation and will behave as resistor
• Pull up device is initially resistive when pull down is turned on
• The point at which Vin = Vout is called Vinv• Vinv can be shifted by variation of ratios of pull up and
down resistances – determined by the length to width ratio of the transistor.
MOS-SLIDES-AKM 28
NMOS Inverter
• With NMOS Depletion Mode transistor• High Dissipation: When VIN is high current
flows through both the devices.• Output switching: occurs when Vin
exceeds Vthpd• During fall 1→ 0 transition, pull up offers
lower resistance to charge capacitive load.• Degrades 0 value : Low output value is
determined by pull down resistance.
MOS-SLIDES-AKM 29
CMOS INVERTER
MOS-SLIDES-AKM 30
CMOS Inverter
Polysilicon
In Out
VDD
GND
PMOS 2λ
Metal 1
NMOS
OutIn
VDD
PMOS
NMOS
Contacts
N Well
MOS-SLIDES-AKM 31
CMOS Fabrication
MOS-SLIDES-AKM 32
CMOS Fabrication
MOS-SLIDES-AKM 33
Current Voltage Characteristics
MOS-SLIDES-AKM 34
CMOS INVERTER –VOLTAGE TRANSFER CHARACTERISTICS
MOS-SLIDES-AKM 35
CMOS INVERTER - CONTD
• Region R1: 0 < Vin < Vthn, NMOS transistor is off, PMOS device operates in the linear region.
• Region R2: Vthn< Vin< VDD - |Vthp| and Vin + |Vthp| < Vout≤ VDD, NMOS transistor in saturation, and PMOS transistor still in the linear region.
• Region R3: Vthn<Vin<VDD - |Vthp| and Vin - Vthn ≤ Vout ≤Vin + |Vthp|, both the transistors are in saturation.
• Region R4: Vthn < Vin< VDD – |Vthp| and Vout < Vin - Vthn, NMOS transistor is in the linear region and PMOS remains in saturation.
• Region R5: VDD – |Vthp| < Vin < VDD, PMOS transistor in cut-off, NMOS in the linear region.
MOS-SLIDES-AKM 36
CMOS Inverter Characteristics
MOS-SLIDES-AKM 37
Static Analysis of CMOS Inverter
Current – Voltage Relationship of NMOS transistor : VGSn = Vin , VDSn = Vout
ηn = (μn ε/tox) (W/L)n
Cut-off (Vin ≤ Vthn) : IDS = 0
Linear (Vin – Vthn ≥ Vout) : IDS = ηn(VGSn – Vthn – VDSn/2)VDSn
Saturation ( Vthn ≤ Vin, Vout > Vin – Vthn): IDS = ηn/2(VGSn – Vthn)2
MOS-SLIDES-AKM 38
Current – Voltage Relationship of PMOS transistor
Cut-off (Vin > VDD - |Vthp|) : IDS = 0
Linear (Vin ≤ VDD - |Vthp|) and (Vout >Vin +|Vthn|) : IDS = ηn(VGSp – |Vthp| –VDSp/2)VDSp
Saturation (Vin ≤ VDD - |Vthp|) and (Vout ≤ Vin +|Vthp|):IDS = ηp/2(VGSn – |Vthp|)2
VGSp = - (VDD – Vin), VDSp = - (VDD – Vout)ηp = (μp ε/tox) (W/L)n
MOS-SLIDES-AKM 39
Static Analysis of CMOS Inverter-Contd
• VOH = VDD
• VOL = 0 • Vinv = [ Vthn + (1/√β)(VDD + Vthp)] / (1 + 1/√β) • β = ηn/ηp
=[μn(εox/tox)n (W/L)n ]/ [μp(εox/tox)p(W/L)p] • for β = 1, • (W/L)n / (W/L)p = μp/μn ≈ 1/2.5• (W/L)p ≈ 2.5 (W/L)n
MOS-SLIDES-AKM 40
Static Analysis of CMOS Inverter-Contd
• VIL = (2Vout + Vthp – VDD + βVthn) / (1 + β) • β = 1, and Vthn = │Vthp│• VIL = 1/8 (3VDD +2 Vthn) • VIH = [VDD + Vthp + β(2 Vout + Vthn)] / (1 + β) • with β = 1, and Vthn = │Vthp│, • VIH = (5VDD – 2Vthn) /8
MOS-SLIDES-AKM 41
NOISE MARGINS
• NML = VIL – VOL = VIL
• NMH = VOH – VIH = VDD – VIH
MOS-SLIDES-AKM 42
Switching Characteristics of a CMOS Inverter
Parasitic capacitances in a cascaded CMOS inverter
MOS-SLIDES-AKM 43
Switch model of a static CMOS inverter
MOS-SLIDES-AKM 44
Propagation delay times and rise and fall times of an inverter
MOS-SLIDES-AKM 45
CMOS inverter equivalent circuit during high-to-low and low-to-high output transitions
MOS-SLIDES-AKM 46
Propagation Delay Estimation• High to Low Transition• τpHL = τpHL1 + τpHL2
• τpHL1 = the period during which Vout drops from VDD to VDD – Vthn.
• τpHL1 = 2 CLVthn / ηn (VDD – Vthn)2
• τpHL2 = the period during which Vout drops from VDD – Vthn to VDD /2.
• τpHL2 = ⎥⎦
⎤⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛−
− DD
thn
thnDDn
L
VV
VVC 43ln
)(η
MOS-SLIDES-AKM 47
Propagation Delay Estimation –Contd.
• Low to High Transition
• τpLH =
• For τpHL = τpLH , (W/L)p ≈ 2.5 (W/L)n
⎥⎥⎦
⎤
⎢⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛−+
−− DD
thp
thpDD
thp
thpDDp
L
VV
VVV
VVC ||4
3ln|)|(
||2|)|(η
MOS-SLIDES-AKM 48
Typical input - output and load capacitor current waveforms in a
CMOS inverter
MOS-SLIDES-AKM 49
Power Dissipation in CMOS Inverter
• Dynamic Power Consumption
• Short Circuit Currents
• Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors
MOS-SLIDES-AKM
E-charge = CL VDD2
E-discharge = ½ CL VDD2
Average Power dissipation
PAvg= 1/T CL VDD2 = CL VDD
2 f
50
Dynamic Power Consumption
MOS-SLIDES-AKM 51
Switching Power Dissipation in CMOS Inverter
• fmax = 1/2τp• Power Delay Product, • PDP = Pavg τp• For f = fmax, PDP = CL VDD
2 fmax τp= ½ CL VDD
2
Note: average switching power dissipation of a CMOS inverter is independent of transistor sizes and characteristics provided there is full voltage swing
Analysis is valid when output node of the gate undergoes one transition (0 to VDD) in a clock cycle.
MOS-SLIDES-AKM 52
Switching Power Dissipation - Contd
• When node transition rate is slower than clock rate
• PAvg = CL VDD2 f
• where is the node transition factor (effective number of power consuming transition per cycle)
• Energy Delay Product EDP = PDP τp = ½ CL VDD
2 τp
Tα
Tα
MOS-SLIDES-AKM 53
Short Circuit Current in CMOS InverterShort Circuit Current in CMOS Inverter
MOS-SLIDES-AKM 54
Short Circuit Current
• Short circuit current is large if output load capacitance is low and input rise/fall time is large.
• To reduce short circuit power dissipationinput/output rise and fall times should be of same order =
PAvg(short-circuit) = 1/12[k f (VDD- Vthn -|Vthp|)3]τ
τ
MOS-SLIDES-AKM 55
Sub Threshold LeakageSub Threshold Leakage
MOS-SLIDES-AKM 56
Advantages of CMOS Inverter
• The high and low output voltages are equal to Vdd and ground respectively so that the voltage swing is the same as the supply voltage..
• The logic levels are not dependent on the relative device sizes and hence the size of the transistors can be minimized.
• There is always a finite resistance between the output and either Vdd or ground in the steady state. The inverter can, therefore, be designed to have a low input impedance, making it less sensitive to noise.
• The CMOS inverter has a very high input resistance and draws no dc input current as the gate of a MOS transistor is virtually a perfect insulator.
MOS-SLIDES-AKM 57
Technology Scaling
• Full Scaling (Constant Field Scaling)• Constant Voltage Scaling
Parameter Full Scaling Constant-Voltage Scaling
Channel Length (L) L/κ L/ κ Channel Width (W) W/κ W/κ Gate oxide thickness (tox) tox /κ tox /κ Supply voltage VDD VDD /κ VDD Junction depth (Xj) Xj/κ Xj/κ Threshold voltage (Vth) Vth/κ Vth Doping densities – ND (NA) NDκ (NAκ) NDκ2 (NAκ2)
MOS-SLIDES-AKM 58
Effects of scaling on MOS transistor characteristics
Parameter Full Scaling
Constant-Voltage Scaling
Gate Area (A = WL)
A/κ2 A/κ2
Oxide capacitance (Cox) κCox κCox Gate capacitance Cg (= CoxWL) Cg/κ Cg/κ Transconductance/Gain factor (η) ηκ ηκ Electric field (E) E κE Drain current (IDS) IDS/κ IDSκ Power dissipation (P) P/κ2 Pκ Power density ( PD = P/area) PD PDκ3
Gate delay (τ) τ /κ τ /κ2
MOS-SLIDES-AKM 59
Inter-dependence of leakage currents in short channel devices
• Device Geometry (channel length, oxide thickness) and doping profile affects-
• Sub-threshold leakage • Gate leakage• Reverse biased diode (drain/ source –
substrate) leakage
MOS-SLIDES-AKM 60
Factors affecting scaling
• Constant field scaling requires threshold voltage reduction – to improve propagation delay.
• Low threshold affects: noise margins and sub-threshold conduction.
• Gate oxide thickness reduction: Increases gate leakage due to electron tunneling and hot carrier injection from substrate to gate
MOS-SLIDES-AKM 61
Threshold Reduction
• By well engineering : changing doping profile in the channel (e.g halo doping). Aims to minimize leakage currents while maximizing linear and saturated currents.
• Multiple threshold CMOC circuits• Variable threshold circuits
MOS-SLIDES-AKM 62
SPICE SIMULATION
• Active/ passive devices used in the circuit under simulation are represented by suitable models.
• Uses Kirchoff laws for analysis of circuit behavior• Circuit voltage and current signals are represented as
continuous waveforms. • During simulation continuous variables are approximated
by floating point numbers with suitable increment steps specified.
• SPICE supports different modes of analysis of active circuits : DC analysis, transient analysis, small signal analysis, etc.
• Different versions of SPICE: PSPICE, HSPICE, T-SPICE
MOS-SLIDES-AKM 63
MOSFET MODEL
• SPICE syntax for MOSFET device is• .model <name> nmos | pmos level = 1|
2| 3 (parameters)• Some of the parameters are gate oxide
thickness (TOX), channel length (L), channel width (W), drain area (AD), source area (AS), drain resistance (RD), source resistance (RS), etc.
MOS-SLIDES-AKM 64
MODEL FILE• .model nmos nmos Level=1• + Vto=2.0 Kp=3.0E-5 Gamma=0.35 • + Phi=0.65 Lambda=0.002 Tox=0.1u • + Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u • + Tpg=1.00 Uo=700.0 Af=1.2• + Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8• + Pb=0.75 Cj=2.0E-4 Mj=0.5• + Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5• + Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11 • + Rd=10.0 Rs=10.0 Rsh=30.0
• .model pmos pmos Level=1• + Vto=-2.0 Kp=3.0E-5 Gamma=0.35 • + Phi=0.65 Lambda=0.002 Tox=0.1u • + Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u • + Tpg=1.00 Uo=700.0 Af=1.2• + Kf=1.0E-26 Is=1.0E-15 Js=1.0E-8• + Pb=0.75 Cj=2.0E-4 Mj=0.5• + Cjsw=1.00E-9 Mjsw=0.33 Fc=0.5• + Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11 • + Rd=10.0 Rs=10.0 Rsh=30.0
MOS-SLIDES-AKM 65
• * Waveform probing commands• .probe• .options probefilename="INV.dat"• + probesdbfile="C:\Documents and
Settings\smdp\Desktop\inv\INV.sdb"• + probetopmodule="Module0“• .include ml1_1_typ.md (model file included)• vdd vdd 0 5 0• vin vin gnd PULSE (0 5 0 1n 1n 1u 2u) ROUND=0 (input pulse)• .tran .1u 10u start=0 (type of analysis)• .print tran v(vin) v(vout) (probing for the output) • * Main circuit: Module0• M1 vout vin Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u • M2 vout vin Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u• * End of main circuit: Module0
FORMAT FOR WRITING SPICE NETLIST
MOS-SLIDES-AKM 66
DC ANALYSIS RESULT
MOS-SLIDES-AKM 67
AC ANALYSIS RESULT
MOS-SLIDES-AKM 68
EFFECT OF CHANGE IN THE MODEL FILE PARAMETER
Declaration of model file 1
• .model nmos nmos Level=1• + Vto=2.0 Kp=3.0E-5 Gamma=0.35• .model pmos pmos Level=1• + Vto=-2.0 Kp=3.0E-5 Gamma=0.35
Declaration of model file 2
• .model nmos nmos Level=1• + Vto=1.0 Kp=3.0E-5 Gamma=0.35 • .model pmos pmos Level=1• + Vto=-1.0 Kp=3.0E-5 Gamma=0.35
RESULT COMPARISON
MOS-SLIDES-AKM 70
REFERENCES
1. Rabaey J. M.,Chandrakasan A., and Nikolic B., “ Digital Integrated Circuits”, Prentice- Hall of India, 2003.
2. Kang, Sung-Mo and Leblebici, Y.: CMOS Digital Integrated Circuits, McGraw Hill Pub., 2003
3. Weste N.H.E and Eshraghlan, K: Principles of CMOS VLSI Design, Pearson Education, 2004.
MOS-SLIDES-AKM 71