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MSP430 Teaching MaterialsUBI

Lecture 7Digital-to-Analogue Conversion

& Hardware Multiplier& Hardware Multiplier

T I t t I t dTexas Instruments IncorporatedUniversity of Beira Interior (PT)

Pedro Dinis Gaspar, António Espírito Santo, Bruno Ribeiro, Humberto SantosUniversity of Beira Interior, Electromechanical Engineering Department

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Copyright 2009 Texas Instruments All Rights Reserved

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Contents (1/2)UBI

Digital-to-Analogue Converter (DAC) introduction

DAC types

DAC’s characteristic parameters

DAC12 module: DAC12 module: Features Operation Registers

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Contents (2/2)UBI

Introduction

Hardware Multiplier structure: Block diagram Operands

Hardware Multiplier Registers Hardware Multiplier Registers

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Introduction (1/3)UBI

The final stage in digital processing is to convert the digital output value to a signal that can be used by the g p g yreal-world e.g. a voltage or current;

A Digital-to-Analogue converter (DAC) is an electronic device or circuit that converts a digital representation of a quantity to a discrete analogue value;

The inputs to a DAC are the digital value and a reference p gvoltage VREF to set the analogue output level;

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Provides a continuous time output signal, mathematically often treated as discrete Dirac pulses into a zero-order phold and consisting of a series of fixed steps;

Filtering the discrete output signal can be used to approximate a continuous time signal, as well as: Increasing the resolution;g ; Increasing the number of discrete levels and; Reducing the level size (reduces the quantization error).

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Ideal DAC output: A sequence of impulses filtered to construct a continuous A sequence of impulses filtered to construct a continuous

time analogue signal; Precise reproduction of the sampled signal up to the Nyquist

frequency.q y

Real DAC output: Reconstruction is not precise Filter has infinite phase delay;Filter has infinite phase delay; There will be quantization errors.

The digital data sequence is usually converted into an The digital data sequence is usually converted into an analogue voltage at a uniform update rate;

The clock signal latches the actual data of the digital The clock signal latches the actual data of the digital input data sequence and the DAC holds the output analogue voltage until the next clock signal latches new data.

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DAC types (1/4)UBI

Binary Weighted DAC:C t i i t ( t ) f h bit f th Contains one resistor (or current source) for each bit of the DAC connected to a common voltage source VREF;

There are accuracy problems (high precision resistors are y p ( g prequired);

R/2R Ladder DAC: Binary weighted DAC that uses a repeating cascaded Binary weighted DAC that uses a repeating cascaded

structure of resistors of value R and 2R; The MSP430’s DAC12 module uses this architecture.

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DAC types (2/4)UBI

R/2R Ladder DAC:E l R/2R 4 bit DAC hit t Example: R/2R 4 bit DAC architecture:

Switch current to negative input of Op-Amp which is a

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g p p pvirtual ground

DAC types (3/4)UBI

Interpolating DACs:U l d it i t h i d t d b th Use a pulse density conversion technique adopted by the Sigma Delta ADC.

Pulse Width Modulator DAC: A stable voltage (or current) is switched into a low-pass (LP)

filte d ing a time pe iod ep esentati e of the digital inp t filter during a time period representative of the digital input value.

Thermometer coded DAC: One resistor (or current source) for each value of DAC

output;output; High precision and conversion speed; Expensive.

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Expensive.

DAC types (4/4)UBI

Hybrid DAC:C bi ti f th i t h i i i l t Combination of the previous techniques in a single converter;

Segmented DAC: Combination of the thermometer coded principle for the

most significant bits (MSBs) and the binary weighted principle for the least significant bits (LSBs);

Uses the best of both topologies.Uses the best of both topologies.

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DAC characteristic parameters (1/2)UBI

Resolution (n):N b f ibl DAC t t l l 2n ( f bit ) Number of possible DAC output levels, 2n (n: no. of bits);

The Effective Number Of Bits (ENOB) is the actual resolution achieved by the DAC, taking into account errors like y , gnonlinearity, signal-to noise ratio.

Integral Non Linearity (INL): Integral Non-Linearity (INL): Deviation of a DAC's transfer function from a straight line.

Differential Non-Linearity (DNL): Difference between an actual step height and the ideal value

of 1 LSB; DNL < 1 LSB the DAC is monotonic that is no loss of data

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DNL < 1 LSB, the DAC is monotonic, that is, no loss of data.

DAC characteristic parameters (2/2)UBI

Offset error: Analogue output voltage when the digital input is zero.Analogue output voltage when the digital input is zero.

Gain error: Difference between the ideal maximum output voltage and Difference between the ideal maximum output voltage and

the actual maximum value of the transfer function, after subtracting the offset error.

Monotonicity: Ability of the analogue output of the DAC to increase with an

increase in digital code or the converse.increase in digital code or the converse.

Total Harmonic Distortion (THD): Distortion and noise introduced to the signal by the DAC Distortion and noise introduced to the signal by the DAC.

Dynamic range: Difference between the largest and the smallest signals

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Difference between the largest and the smallest signals.

DAC12 moduleUBI

The 12 bit DAC12 module is a voltage output DAC;

All the MSP430 hardware development tools contain this All the MSP430 hardware development tools contain this module;

The MSP430FG4618 device on the Experimenter’s board has two DAC12 modules, allowing them to be grouped has two DAC12 modules, allowing them to be grouped together for synchronous update operation.

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DAC12 moduleUBI

DAC12 block diagram:

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DAC12 featuresUBI

12 bit monotonic output;

8-bit or 12-bit voltage output resolution;

Programmable settling time vs power consumption; Programmable settling time vs. power consumption;

Internal or external reference selection;

Straight binary or Two’s complement data format;

Self-calibration option for offset correction;

Synchronized update capability for multiple DAC12s;

Direct Memory Access (DMA) enable.

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DAC12 operation (1/4)UBI

DAC12 core:D i t ll d b Dynamic range controlled by:• DAC’s resolution: 8 bits or 12 bits (DAC12RES bit);• Full-scale output: 1xVREF or 3xVREF (DAC12IR bit);Full scale output: 1xVREF or 3xVREF (DAC12IR bit);• Input data format: straight binary or two’s complement

(DAC12DF bit).

The output voltage (straight binary data format):Resolution DAC12RES DAC12IR Output voltage Resolution DAC12RES DAC12IR Output voltage

12 bit 0 0 4096

_123

xDATDACVV REFOUT

12 bit 0 1 _12 xDATDACVV

4096VV REFOUT

8 bit 1 0 256

_123

xDATDACVV REFOUT

8 bit 1 1 12 xDATDAC

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8 bit 1 1 256

_12 xDATDACVV REFOUT


DAC12_xDAT Data Format:

The data format modifies the full-scale output voltage:

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Updating the DAC12 voltage output (DAC12_xDAT reg.):C fi bl ith th DAC12LSEL bit Configurable with the DAC12LSELx bits:• DAC12LSELx = 0: Immediate when new data is written;• DAC12LSELx = 1: Grouped (data is latched);DAC12LSELx 1: Grouped (data is latched);• DAC12LSELx = 2: Rising edge from the Timer_A CCR1;• DAC12LSELx = 3: Rising edge from the Timer_B CCR2.

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DAC12 Interrupts:Th DAC12IV i h d ith th DMA t ll The DAC12IV is shared with the DMA controller;

This structure provides:This structure provides:• Increased system flexibility;• No code execution required;• Lower power;• Higher efficiency.

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DAC12 Registers (1/3)UBI

DAC12_xCTL, DAC12 Control Register15 14 13 12 11 10 9 815 14 13 12 11 10 9 8

DAC12OPS DAC12SREFx DAC12RES DAC12LSELx DAC12CALON DAC12IR

7 6 5 4 3 2 1 0

DAC12AMPx DAC12DF DAC12IE DAC12IFG DAC12ENC DAC12GRP

Bit Description

15 DAC12OPS DAC12 output:DAC12OPS = 0 DAC12_0 on P6.6, DAC12_1 on P6.7DAC12OPS = 1 DAC12_0 on VeREF+, DAC12_1 on P5.1

14-13 DAC12REFx DAC12 reference voltage:DAC12REF1 DAC12REF0 = 00 VREF+DAC12REF1 DAC12REF0 = 01 VREF+DAC12REF1 DAC12REF0 = 10 VeREF+DAC12REF1 DAC12REF0 = 11 VeREF+

l12 DAC12RES DAC12 resolution:DAC12RES = 0 12 bit resolutionDAC12RES = 1 8 bit resolution

11-10 DAC12LSELx DAC12 load:DAC12LSEL1 DAC12LSEL0 = 00 DAC12_xDAT writtenDAC12LSEL1 DAC12LSEL0 01 ll d DAC12 DAT iDAC12LSEL1 DAC12LSEL0 = 01 all grouped DAC12_xDAT writtenDAC12LSEL1 DAC12LSEL0 = 10 Rising edge of Timer_A.OUT1 (TA1)DAC12LSEL1 DAC12LSEL0 = 11 Rising edge of Timer_B.OUT2 (TB2)

9 DAC12CALON DAC12 calibration initialized or in progress when DAC12CALON = 1

8 DAC12IR DAC12 input range:

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8 DAC12IR DAC12 input range:DAC12IR = 0 DAC12 full-scale output: 3x reference voltageDAC12IR = 1 DAC12 full-scale output: 1x reference voltage


DAC12_xCTL, DAC12 Control Register15 14 13 12 11 10 9 815 14 13 12 11 10 9 8

DAC12OPS DAC12SREFx DAC12RES DAC12LSELx DAC12CALON DAC12IR

7 6 5 4 3 2 1 0

DAC12AMPx DAC12DF DAC12IE DAC12IFG DAC12ENC DAC12GRP

Bit Description

7-5 DAC12AMPx DAC12 amplifier setting:AMP2 AMP1 AMP0 = 000 AMP2 AMP1 AMP0 = 001

Input buffer:OffOff

Output buffer:DAC12 off (high Z)DAC12 off (0 V)AMP2 AMP1 AMP0 = 001

AMP2 AMP1 AMP0 = 010 AMP2 AMP1 AMP0 = 011 AMP2 AMP1 AMP0 = 100 AMP2 AMP1 AMP0 = 101 AMP2 AMP1 AMP0 = 110

OffLow f / ILow f / ILow f / IMedium f / IMedium f / I

DAC12 off (0 V)Low f / IMedium f / IHigh f / IMedium f / IHigh f / I

AMP2 AMP1 AMP0 = 111 f: frequency (speed)I: current

High f / I High f / I

4 DAC12DF DAC12 data format:DAC12DF = 0 Straight binaryDAC12DF = 1 Two’s complement

3 DAC12IE DAC12 interrupt enable when DAC12IE = 1

2 DAC12IFG DAC12 Interrupt flag DAC12IFG = 1 when interrupt pending

1 DAC12ENC DAC12 enable when DAC12ENC = 1 and DAC12LSELx>0.

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0 DAC12GRP Groups DAC12_x with the next higher DAC12_x when DAC12GRP = 1 (exception for DAC12_1)


DAC12_xDAT, DAC12 Data Register The four most significant bits (bits 15 – 12) are always zero;The four most significant bits (bits 15 12) are always zero;

The twelve least significant bits store the DAC12 data (bi 11 0)(bits 11 – 0);

The DAC12 data is right justified but the MSB depends on:The DAC12 data is right justified, but the MSB depends on:• Resolution:

– 8 bit: Bit 7;– 12 bit: Bit 11.

• Data format:St i ht bi MSB i d t– Straight binary: MSB is data;

– Two’s complement: MSB is sign.

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Several devices in the MSP430 family contain a hardware multiplier peripheral module:multiplier peripheral module:

• 54xx;• FG46xx;;• FE42x(A);• F47xx; F44X; F42x(A);• F261x; F24x(x);• F16x(x).

The MSP430FG4618 (Experimenter’s board) supports multiplications using the Hardware Multiplier module,

i h i f i i h i i iwithout interfering with CPU activities.

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The hardware multiplier supports: Unsigned multiply (MPY); Unsigned multiply (MPY); Signed multiply (MPYS); Unsigned multiply accumulate (MAC); Signed multiply accumulate (MACS).

The multiplication operation can be: 16×16 bits;

b 16×8 bits; 8×16 bits; 8×8 bits.8×8 bits.

• Operands are written to two registers, each one with 8 bits or 16 bits.

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The result of an operation can be accessed by reading two or three registers:two or three registers: Result low 16-bit word (bits 15 .. 0) in register RESLO; Result high 16-bit word (bits 31 .. 16) in register RESHI;

Wh d MAC MACS bit 32 i i t SUMEXT When used MAC or MACS: bit 32 in register SUMEXT.

The result is available three MCLK cycles after the operands have been loaded into the peripheral registers;

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Hardware Multiplier Structure (1/4)UBI

Block diagram:

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Two 16-bit operand registers:Fi t d i t OP1 First operand register, OP1:• Has four addresses used to select the multiply mode:

Register name Multiplication operation OP1 Address Register name Multiplication operation OP1 Address

MPY Unsigned multiply 0130h

MPYS Signed multiply 0132h MPYS Signed multiply 0132h

MAC Unsigned multiply accumulate 0134h

MACS Signed multiply accumulate 0136h

Second operand register, OP2:• Writing to the register initiates the multiply operation.

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Three result registers, RESLO, RESHI, and SUMEXT:RESLO t th l d f th lt RESLO stores the low word of the result;

RESHI stores the high word of the result:• The contents of RESHI depend on the multiply operation:The contents of RESHI depend on the multiply operation:

Multiplication operation RESHI content

Unsigned multiply (MPY) Upper 16-bits of the result

Signed multiply (MPYS) Bit 15 (MSB): sign Bits 14 - 0: upper 15-bits of the result Signed multiply (MPYS) Bits 14 0: upper 15 bits of the result Data format: Two’s complement

Unsigned multiply accumulate (MAC) Upper 16-bits of the result

Upper 16 bits of the result Signed multiply accumulate (MACS)

Upper 16-bits of the result Data format: Two’s complement

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Three result registers, RESLO, RESHI, and SUMEXT:SUMEXT t i i f ti b t th lt SUMEXT contains information about the result:• The contents of SUMEXT depend on the multiply

operation:p

Multiplication operation SUMEXT content

Unsigned multiply (MPY) SUMEXT = 0000h g p y ( )

Signed multiply (MPYS) Extended sign of the result: SUMEXT = 00000h Result was positive or zero SUMEXT = 0FFFFh Result was negative

Unsigned multiply accumulate (MAC) Carry of the result: SUMEXT = 0000h No carry for result SUMEXT = 0001h Result has a carry Extended sign of the result:

Signed multiply accumulate (MACS) Extended sign of the result: SUMEXT = 00000h Result was positive or zero SUMEXT = 0FFFFh Result was negative

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Multiplication Operation (1/2)UBI

Unsigned Multiply (MPY) The two operands are treated as unsigned numbersThe two operands are treated as unsigned numbers

• In the range 00000h (smallest number) to 0FFFFh (largest number)

Th i ibl l i b i d i h i The maximum possible result is obtained with input operands 0FFFFh and 0FFFFh:• 0FFFFh x 0FFFFh = 0FFFE0001h

No carry is possible and the SUMEXT register always contains zero

Signed Multiply (MPYS) The two operands are treated as signed Two’s p g

complement numbers• In the range 08000h (most negative number, –32768

in decimal) to 07FFFh (most positive number

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in decimal) to 07FFFh (most positive number, +32767 in decimal)

30Copyright 2009 Texas Instruments

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Multiplication Operation (2/2)UBI

The SUMEXT register contains the extended sign of the calculated result:• SUMEXT = 00000h: the result is positive• SUMEXT = 0FFFFh: the result is negative

Multiply-and-Accumulate (MAC) The two operands are treated as unsigned numbers (0h p g (

to 0FFFFh) The maximum possible result is obtained with input

operands 0FFFFh and 0FFFFh:operands 0FFFFh and 0FFFFh:• 0FFFFh x 0FFFFh = 0FFFE0001h

This result is added to the previous contents of the two psum registers (SUMLO and SUMHI)• SUMEXT = 00000h: no carry occurred

SUMEXT 00001h d

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• SUMEXT = 00001h: a carry occurred

31Copyright 2009 Texas Instruments

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Hardware Multiplier RegistersUBI

The hardware multiplier registers do not define the type of multiplication operation;

They simply contain the operands and the data result: Register name Description Register name Description

MPY Operand 1 - Unsigned multiply

MPYS Operand 1 - Signed multiply MPYS Operand 1 Signed multiply

MAC Operand 1 - Unsigned multiply accumulate

MACS Operand 1 - Signed multiply accumulate MACS Operand 1 - Signed multiply accumulate

OP2 Operand 2

RESLO Result (low word) RESLO Result (low word)

RESHI Result (high word)

SUMEXT S t i i t

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SUMEXT Sum extension register

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