LTC6244 - Dual 50MHz, Low Noise, Rail-to-Rail, CMOS Op Amp–5V 6244 TA01a – + 1/2 LTC6244HV –5V...
Transcript of LTC6244 - Dual 50MHz, Low Noise, Rail-to-Rail, CMOS Op Amp–5V 6244 TA01a – + 1/2 LTC6244HV –5V...
LTC6244
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Dual 50MHz, Low Noise, Rail-to-Rail, CMOS Op Amp
The LTC®6244 is a dual high speed, unity-gain stable CMOS op amp that features a 50MHz gain bandwidth, 40V/μs slew rate, 1pA of input bias current, low input capacitance and rail-to-rail output swing. The 0.1Hz to 10Hz noise is just 1.5μVP-P and 1kHz noise is guaranteed to be less than 12nV/√Hz. This excellent AC and noise performance is combined with wide supply range operation, a maximum offset voltage of just 100μV and drift of only 2.5μV/°C, making it suitable for use in many fast signal processing applications, such as photodiode amplifi ers.
This op amp has an output stage that swings within 35mV of either supply rail to maximize the signal dynamic range in low supply applications. The input common mode range extends to the negative supply. It is fully specifi ed on 3V and 5V, and an HV version guarantees operation on supplies of ±5V.
The LTC6244 is available in the 8-pin MSOP, and for com-pact designs, it is packaged in the tiny dual fi ne pitch lead free (DFN) package.
n Photodiode Amplifi ersn Charge Coupled Amplifi ersn Low Noise Signal Processingn Active Filtersn Medical Instrumentationn High Impedance Transducer Amplifi er
n Input Bias Current: 1pA (Typ at 25°C)n Low Offset Voltage: 100μV Maxn Low Offset Drift: 2.5μV/°C Maxn 0.1Hz to 10Hz Noise: 1.5μVP-Pn Slew Rate: 40V/μsn Gain Bandwidth Product: 50MHzn Output Swings Rail-to-Railn Supply Operation:
2.8V to 6V LTC6244 2.8V to ±5.25V LTC6244HV
n Low Input Capacitance: 2.1pFn Available in 8-Pin MSOP and Tiny DFN Packages
Very Low Noise Large Area Photodiode VOS Distribution
TYPICAL APPLICATION
DESCRIPTION FEATURES
APPLICATIONS
5V VOUT = 1M • IPDBW = 350kHzNOISE = 291nV AT 10kHz
5V
VBB
IPD
1M
PHILIPSBF862JFET
HAMAMATSU LARGE AREAPHOTODIODE
S1227-1010BQCPD = 3000pF
* CAN BE MICROPHONIC, FILM, X7R, IF NEEDED.
0.25pF
–5V 6244 TA01a
–
+
1/2LTC6244HV
–5V4.99k
4.7μF*
4.99k
VOUT
INPUT OFFSET VOLTAGE (μV)
–60 –40
NU
MB
ER
OF
UN
ITS
60
80
100
120
60
6244 TA01b
40
20
50
70
90
110
30
10
0–20 0 20 40
LTC6244MS8VS = 5V, 0VVCM = 2.5VTA = 25°C
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
LTC6244
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Total Supply Voltage (V+ to V–) LTC6244 ..................................................................7V LTC6244HV ...........................................................12VInput Voltage .......................... (V+ + 0.3V) to (V– – 0.3V)Input Current ........................................................±10mAOutput Short Circuit Duration (Note 2)............. Indefi niteOperating Temperature Range LTC6244C ............................................ –40°C to 85°C LTC6244I.............................................. –40°C to 85°C LTC6244H .......................................... –40°C to 125°C
(Note 1)
Specifi ed Temperature Range (Note 3) LTC6244C ................................................ 0°C to 70°C LTC6244I.............................................. –40°C to 85°C LTC6244H .......................................... –40°C to 125°CJunction Temperature ........................................... 150°CStorage Temperature Range ................... –65°C to 150°CLead Temperature (Soldering, 10 sec) .................. 300°C
ABSOLUTE MAXIMUM RATINGS
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6244CDD#PBF LTC6244CDD#TRPBF LCCF 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC6244HVCDD#PBF LTC6244HVCDD#TRPBF LCGD 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC6244IDD#PBF LTC6244IDD#TRPBF LCCF 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC6244HVIDD#PBF LTC6244HVIDD#TRPBF LCGD 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC6244HDD#PBF LTC6244HDD#TRPBF LCCF 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC6244HVHDD#PBF LTC6244HVHDD#TRPBF LCGD 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC6244CMS8#PBF LTC6244CMS8#TRPBF LTCCM 8-Lead Plastic MSOP 0°C to 70°C
LTC6244HVCMS8#PBF LTC6244HVCMS8#TRPBF LTCGF 8-Lead Plastic MSOP 0°C to 70°C
LTC6244IMS8#PBF LTC6244IMS8#TRPBF LTCCM 8-Lead Plastic MSOP –40°C to 85°C
LTC6244HVIMS8#PBF LTC6244HVIMS8#TRPBF LTCGF 8-Lead Plastic MSOP –40°C to 85°C
LTC6244HMS8#PBF LTC6244HMS8#TRPBF LTCCM 8-Lead Plastic MSOP –40°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ORDER INFORMATION
TOP VIEW
9
DD PACKAGE8-LEAD (3mm × 3mm) PLASTIC DFN
5
6
7
8
4
3
2
1OUT A
–IN A
+IN A
V–
V+
OUT B
–IN B
+IN BB
A
TJMAX = 150°C, θJA = 43°C/WEXPOSED PAD (PIN 9) CONNEECTED TO V–
(PCB CONNECTION OPTIONAL)
1
2
3
4
OUT A
–IN A
+IN A
V–
8
7
6
5
V+
OUT B
–IN B
+IN B
TOP VIEW
MS8 PACKAGE8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 250°C/W
PIN CONFIGURATION
LTC6244
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(LTC6244C/I, LTC6244HVC/I) The l denotes the specifi cations which apply over the specifi ed temperature range, otherwise specifi cations are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 4) MS8 Package0°C to 70°C–40°C to 85°C
l
l
40 100225300
μVμVμV
DD Package0°C to 70°C–40°C to 85°C
l
l
100 650800950
μVμVμV
VOS Match Channel-to-Channel (Note 5) MS8 Package0°C to 70°C–40°C to 85°C
l
l
40 160275325
μVμVμV
DD Package0°C to 70°C–40°C to 85°C
l
l
150 8009001.1
μVμV
mV
TC VOS Input Offset Voltage Drift, MS8 (Note 6) l 0.7 2.5 μV/°C
IB Input Bias Current (Notes 4, 7)l
175
pApA
IOS Input Offset Current (Notes 4, 7)l
0.575
pApA
Input Noise Voltage 0.1Hz to 10Hz 1.5 μVP-P
en Input Noise Voltage Density f = 1kHz 8 12 nV/√Hz
in Input Noise Current Density (Note 8) 0.56 fA/√Hz
RIN Input Resistance Common Mode 1012 Ω
CIN Input Capacitance Differential Mode Common Mode
f = 100kHz3.52.1
pFpF
VCM Input Voltage Range Guaranteed by CMRR l 0 3.5 V
CMRR Common Mode Rejection 0V ≤ VCM ≤ 3.5V l 74 105 dB
CMRR MatchChannel-to-Channel (Note 5) l 72 100 dB
AVOL Large Signal Voltage Gain VO = 1V to 4VRL = 10k to VS/20°C to 70°C–40°C to 85°C
l
l
1000600450
2500 V/mVV/mVV/mV
VO = 1.5V to 3.5VRL = 1k to VS/20°C to 70°C–40°C to 85°C
l
l
300200150
1000 V/mVV/mVV/mV
VOL Output Voltage Swing Low (Note 9) No LoadISINK = 1mAISINK = 5mA
l
l
l
1540150
3575300
mVmVmV
VOH Output Voltage Swing High (Note 9) No LoadISOURCE = 1mAISOURCE = 5mA
l
l
l
1545
175
3575
325
mVmVmV
PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l 75 105 dB
PSRR MatchChannel-to-Channel (Note 5) l 73 100 dB
Minimum Supply Voltage (Note 10) l 2.8 V
ISC Short-Circuit Current l 25 35 mA
IS Supply Current per Amplifi er l 6.25 7.4 mA
ELECTRICAL CHARACTERISTICS
LTC6244
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(LTC6244C/I, LTC6244HVC/I) The l denotes the specifi cations which apply over the specifi ed temperature range, otherwise specifi cations are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
GBW Gain Bandwidth Product Frequency = 100kHz, RL = 1kΩ l 35 50 MHz
SR Slew Rate (Note 11) AV = –2, RL = 1kΩ l 18 35 V/μs
FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1kΩ l 1.9 3.7 MHz
ts Settling Time VSTEP = 2V, AV = –1, RL = 1kΩ, 0.1% 535 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 4) MS8 Package0°C to 70°C–40°C to 85°C
l
l
40 175250325
μVμVμV
DD Package0°C to 70°C–40°C to 85°C
l
l
100 650800950
μVμVμV
VOS Match Channel-to-Channel (Note 5) MS8 Package0°C to 70°C–40°C to 85°C
l
l
40 200300350
μVμVμV
DD Package0°C to 70°C–40°C to 85°C
l
l
150 8009001.1
μVμV
mV
IB Input Bias Current (Notes 4, 7)l
175
pApA
IOS Input Offset Current (Notes 4, 7)l
0.575
pApA
Input Noise Voltage 0.1Hz to 10Hz 1.5 μVP-P
en Input Noise Voltage Density f = 1kHz 8 12 nV/√Hz
in Input Noise Current Density (Note 8) 0.56 fA/√Hz
VCM Input Voltage Range Guaranteed by CMRR l 0 1.5 V
CMRR Common Mode Rejection 0V ≤ VCM ≤ 1.5V l 70 105 dB
CMRR MatchChannel-to-Channel (Note 5) l 68 100 dB
AVOL Large Signal Voltage Gain VO = 1V to 2VRL = 10k to VS/20°C to 70°C–40°C to 85°C
l
l
20010085
800 V/mVV/mVV/mV
VOL Output Voltage Swing Low (Note 9) No LoadISINK = 1mA
l
l
1245
30110
mVmV
VOH Output Voltage Swing High (Note 9) No LoadISOURCE = 1mA
l
l
1250
30110
mVmV
PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l 75 105 dB
PSRR MatchChannel-to-Channel (Note 5) l 73 100 dB
Minimum Supply Voltage (Note 10) l 2.8 V
ISC Short-Circuit Current l 8 15 mA
(LTC6244C/I, LTC6244HVC/I) The l denotes the specifi cations which apply over the specifi ed temperature range, otherwise specifi cations are at TA = 25°C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
LTC6244
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(LTC6244C/I, LTC6244HVC/I) The l denotes the specifi cations which apply over the specifi ed temperature range, otherwise specifi cations are at TA = 25°C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IS Supply Current per Amplifi er l 4.8 5.8 mA
GBW Gain Bandwidth Product Frequency = 100kHz, RL = 1kΩ l 35 50 MHz
(LTC6244HVC/I) The l denotes the specifi cations which apply over the specifi ed temperature range, otherwise specifi cations are at TA = 25°C. VS = ±5V, 0V, VCM = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 4) MS8 Package0°C to 70°C–40°C to 85°C
l
l
50 220275375
μVμVμV
DD Package0°C to 70°C–40°C to 85°C
l
l
100 700800
1050
μVμVμV
VOS Match Channel-to-Channel (Note 5) MS8 Package0°C to 70°C–40°C to 85°C
l
l
50 250325400
μVμVμV
DD Package0°C to 70°C–40°C to 85°C
l
l
150 90010001100
μVμVμV
TC VOS Input Offset Voltage Drift, MS8 (Note 6) l 0.7 2.5 μV/°C
IB Input Bias Current (Notes 4, 7)l
175
pApA
IOS Input Offset Current (Notes 4, 7)l
0.575
pApA
Input Noise Voltage 0.1Hz to 10Hz 1.5 μVP-P
en Input Noise Voltage Density f = 1kHz 8 12 nV/√Hz
in Input Noise Current Density (Note 8) 0.56 fA/√Hz
RIN Input Resistance Common Mode 1012 Ω
CIN Input Capacitance Differential Mode Common Mode
f = 100kHz3.52.1
pFpF
VCM Input Voltage Range Guaranteed by CMRR l –5 3.5 V
CMRR Common Mode Rejection –5V ≤ VCM ≤ 3.5V l 80 105 dB
CMRR MatchChannel-to-Channel (Note 5) l 78 95 dB
AVOL Large Signal Voltage Gain VO = –3.5V to 3.5VRL = 10k0°C to 70°C–40°C to 85°C
l
l
250015001200
6000 V/mVV/mVV/mV
RL = 1k0°C to 70°C–40°C to 85°C
l
l
700400300
3500 V/mVV/mVV/mV
VOL Output Voltage Swing Low (Note 9) No LoadISINK = 1mAISINK = 10mA
l
l
l
1545360
4075550
mVmVmV
VOH Output Voltage Swing High (Note 9) No LoadISOURCE = 1mAISOURCE = 10mA
l
l
l
1545
360
4075
550
mVmVmV
ELECTRICAL CHARACTERISTICS
LTC6244
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 4) MS8 Packagel
40 125400
μVμV
DD8 Packagel
100 650950
μVμV
VOS Match Channel-to-Channel (Note 5) MS8 Packagel
40 160400
μVμV
DD8 Package–40°C to 125°C l
150 8001160
μVμV
TC VOS Input Offset Voltage Drift, MS8 (Note 6) l 0.7 2.5 μV/°C
IB Input Bias Current (Notes 4, 7)l
12
pAnA
IOS Input Offset Current (Notes 4, 7)l
0.5250
pApA
VCM Input Voltage Range Guaranteed by CMRR l 0 3.5 V
CMRR Common Mode Rejection 0V ≤ VCM ≤ 3.5V l 74 dB
CMRR Match Channel-to-Channel (Note 5) l 72 dB
AVOL Large Signal Voltage Gain VO = 1V to 4VRL = 10k to VS/2 l 350 V/mV
VO = 1.5V to 3.5VRL = 1k to VS/2 l 125 V/mV
VOL Output Voltage Swing Low (Note 9) No LoadISINK = 1mAISINK = 5mA
l
l
l
4085
325
mVmVmV
VOH Output Voltage Swing High (Note 9) No LoadISOURCE = 1mAISOURCE = 5mA
l
l
l
4085
325
mVmVmV
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSRR Power Supply Rejection VS = 2.8V to 10.5V, VCM = 0.2V l 75 110 dB
PSRR MatchChannel-to-Channel (Note 5) l 73 106 dB
Minimum Supply Voltage (Note 10) l 2.8 V
ISC Short-Circuit Current l 40 55 mA
IS Supply Current per Amplifi er l 7 8.8 mA
GBW Gain Bandwidth Product Frequency = 100kHz, RL = 1kΩ l 35 50 MHz
SR Slew Rate (Note 11) AV = –2, RL = 1kΩ l 18 40 V/μs
FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1kΩ l 1.9 4.25 MHz
ts Settling Time VSTEP = 2V, AV = –1, RL = 1kΩ, 0.1% 330 ns
(LTC6244HVC/I) The l denotes the specifi cations which apply over the specifi ed temperature range, otherwise specifi cations are at TA = 25°C. VS = ±5V, 0V, VCM = 0V unless otherwise noted.
(LTC6244H) The l denotes the specifi cations which apply from –40°C to 125°C, otherwise specifi cations are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
LTC6244
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(LTC6244H) The l denotes the specifi cations which apply from –40°C to 125°C, otherwise specifi cations are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l 75 dB
PSRR Match Channel-to-Channel (Note 5) l 73 dB
Minimum Supply Voltage (Note 10) l 2.8 V
ISC Short-Circuit Current l 20 mA
IS Supply Current per Amplifi er l 6.25 7.4 mA
GBW Gain Bandwidth Product Frequency = 100kHz, RL = 1kΩ l 30 MHz
SR Slew Rate (Note 11) AV = –2, RL = 1kΩ l 17 V/μs
FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1kΩ l 1.8 MHz
(LTC6244H) The l denotes the specifi cations which apply from –40°C to 125°C, otherwise specifi cations are at TA = 25°C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 4) MS8 Packagel
40 175400
μVμV
DD8 Packagel
100 650950
μVμV
VOS Match Channel-to-Channel (Note 5) MS8 Packagel
40 160400
μVμV
DD8 Packagel
150 8001200
μVμV
IB Input Bias Current (Notes 4, 7)l
12
pAnA
IOS Input Offset Current (Notes 4, 7)l
0.5250
pApA
VCM Input Voltage Range Guaranteed by CMRR l 0 1.5 V
CMRR Common Mode Rejection 0V ≤ VCM ≤ 1.5V l 70 dB
CMRR Match Channel-to-Channel (Note 5) l 68 dB
AVOL Large Signal Voltage Gain VO = 1V to 2VRL = 10k to VS/2 l 75 V/mV
VOL Output Voltage Swing Low (Note 9) No LoadISINK = 1mA
l
l
30110
mVmV
VOH Output Voltage Swing High (Note 9) No LoadISOURCE = 1mA
l
l
30110
mVmV
PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l 75 dB
PSRR Match Channel-to-Channel (Note 5) l 73 dB
Minimum Supply Voltage (Note 10) l 2.8 V
ISC Short-Circuit Current l 5 mA
IS Supply Current per Amplifi er l 4.8 5.8 mA
GBW Gain Bandwidth Product Frequency = 100kHz, RL = 1kΩ l 28 MHz
ELECTRICAL CHARACTERISTICS
LTC6244
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(LTC6244HVH) The l denotes the specifi cations which apply from –40°C to 125°C, otherwise specifi cations are at TA = 25°C. VS = ±5V, VCM = 0V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 4) DD8 Packagel
100 7001050
μVμV
VOS Match Channel-to-Channel (Note 5) DD8 Packagel
150 9001165
μVμV
TC VOS Input Offset Voltage Drift, MS8 (Note 6) l 0.7 2.5 μV/°C
IB Input Bias Current (Notes 4, 7)l
12
pAnA
IOS Input Offset Current (Notes 4, 7)l
0.5250
pAnA
Input Noise Voltage 0.1Hz to 10Hz 1.5 μVP-P
en Input Noise Voltage Density f = 1kHz 8 12 nV/√Hz
in Input Noise Current Density (Note 8) 0.56 fA/√Hz
RIN Input Resistance Common Mode 1012 Ω
CIN Input Capacitance Differential Mode Common Mode
f = 100kHz3.52.1
pFpF
VCM Input Voltage Range Guaranteed by CMRR l –5 3.5 V
CMRR Common Mode Rejection –5V ≤ VCM ≤ 3.5V l 80 105 dB
CMRR Match Channel-to-Channel (Note 5) l 78 95 dB
AVOL Large Signal Voltage Gain VO = –3.5V to 3.5VRL = 10k l
25001000
6000 V/mVV/mV
RL = 1kl
700170
3500 V/mVV/mV
VOL Output Voltage Swing Low (Note 9) No LoadISINK = 1mAISINK = 10mA
l
l
l
1545360
4075550
mVmVmV
VOH Output Voltage Swing High (Note 9) No LoadISOURCE = 1mAISINK = 10mA
l
l
l
1545360
4075550
mVmVmV
PSRR Power Supply Rejection VS = 2.8V to 10.5V, VCM = 0.2V l 75 110 dB
PSRR Match Channel-to-Channel (Note 5) l 73 106 dB
Minimum Supply Voltage (Note 10) l 2.8 V
ISC Short-Circuit Current l 40 55 mA
IS Supply Current per Amplifi er l 9.3 mA
GBW Gain Bandwidth Product Frequency = 100kHz, RL = 1kΩ l 35 50 MHz
SR Slew Rate (Note 11) AV = –2, RL = 1kΩ l 18 40 V/μs
FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1kΩ l 1.9 4.3 MHz
ts Settling Time VOUT = 2V, AV = –1 , RL =1kΩ l 330 ns
LTC6244
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefi nitely.
Note 3: The LTC6244C/LTC6244HVC are guaranteed to meet specifi ed
performance from 0°C to 70°C. They are designed, characterized and
expected to meet specifi ed performance from –40°C to 85°C, but are not
tested or QA sampled at these temperatures. The LTC6244I/LTC6244HVI,
are guaranteed to meet specifi ed performance from –40°C to 85°C. The
LTC6244H is guaranteed to meet specifi ed performance from –40°C to
125°C.
Note 4: ESD (Electrostatic Discharge) sensitive device. ESD protection
devices are used extensively internal to the LTC6244; however, high
electrostatic discharge can damage or degrade the device. Use proper ESD
handling precautions.
Note 5: Matching parameters are the difference between the two amplifi ers
of the LTC6244. CMRR and PSRR match are defi ned as follows: CMRR
and PSRR are measured in μV/V on the amplifi ers. The difference is
calculated between the sides in μV/V. The result is converted to dB.
Note 6: This parameter is not 100% tested.
Note 7: This specifi cation is limited by high speed automated test
capability. See Typical Characteristics curves for actual typical
performance.
Note 8: Current noise is calculated from the formula: in = (2qIB)1/2
where q = 1.6 × 10–19 coulomb. The noise of source resistors up to
50GΩ dominates the contribution of current noise. See also Typical
Characteristics curve Noise Current vs Frequency.
Note 9: Output voltage swings are measured between the output and
power supply rails.
Note 10: Minimum supply voltage is guaranteed by the power supply
rejection ratio test.
Note 11: Slew rate is measured in a gain of –2 with RF = 1k and RG =
500Ω. VIN is ±1V and VOUT slew rate is measured between –1V and +1V.
On the LTC6244HV/LTC6245HV, VIN is ±2V and VOUT slew rate is measured
between –2V and +2V.
Note 12: Full-power bandwidth is calculated from the slew rate:
FPBW = SR/2πVP.
ELECTRICAL CHARACTERISTICS
LTC6244
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VOS Distribution VOS DistributionVOS Temperature Coeffi cient Distribution
Supply Current vs Supply Voltage (Per Amplifi er)
Offset Voltage vs Input Common Mode Voltage
Input Bias Current vs Common Mode Voltage
Input Bias Current vs Common Mode Voltage Input Bias Current vs Temperature
VOS Temperature Coeffi cient Distribution
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE (μV)
–60 –40
NU
MB
ER
OF
UN
ITS
60
80
100
120
60
6244 G01
40
20
50
70
90
110
30
10
0–20 0 20 40
LTC6244MS8VS = 5V, 0VVCM = 2.5VTA = 25°C
INPUT OFFSET VOLTAGE (μV)
0
NU
MB
ER
OF
UN
ITS
20
40
60
10
30
50
6244 G02
–350 –200 –50 100 250 400–500
LTC6244DDVS = 5V, 0VVCM = 2.5VTA = 25°C
DISTRIBUTION (μV/°C)
–2.4 –1.6 –0.8 0 0.8 1.6 2.4
NU
MB
ER
OF
UN
ITS
6
12
13
14
6422 G03
4
3
2
1
10
8
5
11
0
9
7
LTC6244MS8VS = 5V, 0VVCM = 2.5V2 LOTS–55°C TO 125°C
DISTRIBUTION (μV/°C)
–6 6–5 5–4 4–3 3–2 2–1 10
NU
MB
ER
OF
UN
ITS
6
6422 G04
4
3
2
1
10
8
5
11
0
9
7
LTC6244DDVS = 5V, 0VVCM = 2.5V2 LOTS–55°C TO 125°C
TOTAL SUPPLY VOLTAGE (V)
0
SU
PP
LY C
UR
REN
T (
mA
)
3
4
5
6 10
6244 G05
2
1
02 4 8
6
7
8
12
TA = 125°CTA = 25°CTA = –55°C
INPUT COMMON MODE VOLTAGE (V)
–1
OFF
SET V
OLT
AG
E (
μV
)
0
200
500
400
3
6244 G06
–200
–100
100
300
–300
–4000 1 2 4–0.5 3.50.5 1.5 2.5 4.5 5
TA = 125°CTA = 25°CTA = –55°C
VS = 5V, 0VNORMALIZED TO25°C VOS VALUE
COMMON MODE VOLTAGE (V)
0 0.5 1
10
INP
UT B
IAS
CU
RR
EN
T (
pA
)
100
1.5 2 2.5 3 3.5 4 4.5 5
6244 G07
1
0.1
1000
10000
TA = 125°C
TA = 85°C
TA = 25°C
MS8 PACKAGEVS = 5V, 0V
COMMON MODE VOLTAGE (V)
–0.8
INP
UT B
IAS
CU
RR
EN
T (
pA
)
200
400
600
800
0
6244 G08
0
–200
100
300
500
700
–100
–300
–400–0.6 –0.4 –0.2 0.2 0.4 0.6 0.8 1.0
TA = 125°C
TA = 25°C
MS8 PACKAGEVS = 5V, 0V
TA = 85°C
TEMPERATURE (°C)
25 35 45
10
INP
UT B
IAS
CU
RR
EN
T (
pA
)
100
1000
55 65 75 85 95 105 115 125
6244 G09
1
0.1
10000MS8 PACKAGEVCM = VS/2
VS = 10V
VS = 5V
LTC6244
116244fb
Output Saturation Voltage vs Load Current (Output High)
Gain Bandwidth and Phase Margin vs Temperature
Open Loop Gain vs FrequencyGain Bandwidth and Phase Margin vs Supply Voltage Slew Rate vs Temperature
Output Impedance vs FrequencyCommon Mode Rejection Ratio vs Frequency Channel Separation vs Frequency
Output Saturation Voltage vs Load Current (Output Low)
TYPICAL PERFORMANCE CHARACTERISTICS
LOAD CURRENT (mA)
0.10.01
OU
TP
UT L
OW
SA
TU
RA
TIO
N V
OLT
AG
E (
V)
0.1
1
10
1 10 100
6244 G10
TA = 125°CTA = 25°CTA = –55°C
VS = 5V, 0V
LOAD CURRENT (mA)
0.10.01
OU
TP
UT H
IGH
SA
TU
RA
TIO
N V
OLT
AG
E (
V)
0.1
1
10
1 10 100
6244 G11
TA = 125°CTA = 25°CTA = –55°C
VS = 5V, 0V
TEMPERATURE (°C)
–55 –35 –1530
GA
IN B
AN
DW
IDTH
(M
Hz) P
HA
SE M
AR
GIN
(DEG
)
40
60
70
65 85 105
6244 G12
50
0
–20
20
60
80
40
5 25 45 125
VS = ±5V
PHASEMARGIN
GAINBANDWIDTH
VS = ±5V
VS = ±1.5V
VS = ±1.5VCL = 5pFRL = 1k
FREQUENCY (Hz)
0
GA
IN (
dB
)
PH
AS
E (D
EG
)
20
30
40
60
80
10k 1M 10M 100M
6244 G13
–20100k
100
–10
10
50
70
90
–80
–40
–20
0
40
80
–120
120
–100
–60
20
60
100
VS = ±5VVS = ±1.5V
CL = 5pFRL = 1kVCM = VS/2
PHASE
GAIN
TOTAL SUPPLY VOLTAGE (V)
040
GA
IN B
AN
DW
IDTH
(M
Hz) P
HA
SE M
AR
GIN
(DEG
)
50
60
70 30
40
50
60
2 4 6 8
6244 G14
10 12
TA = 25°CCL = 5pFRL = 1k
GAIN BANDWIDTH
PHASE MARGIN
TEMPERATURE (°C)
–50
SLEW
RA
TE (
V/μ
s)
34
46
48
50
0 50 75
6244 G15
30
42
38
32
44
28
40
36
–25 25 100 125
VS = ±5VVS = ±2.5V
AV = –2RF = 1k, RG = 500ΩCONDITIONS: SEE NOTE 11
FALLING
RISING
FREQUENCY (Hz)
0.1
OU
TP
UT I
MP
ED
AN
CE (
Ω)
10
100
0.01
1
10k 1M 10M 100M
6244 G16
0.001100k
1000
AV = 10
AV = 1
AV = 2
TA = 25°CVS = ±2.5V
FREQUENCY (Hz)
10
CO
MM
ON
MO
DE R
EJE
CTIO
N R
ATIO
(dB
)
30
50
70
90
10k 1M 10M 100M
6244 G17
–10100k
110
0
20
40
60
80
100TA = 25°CVS = ±2.5V
FREQUENCY (Hz)
–100
CH
AN
NEL S
EP
AR
ATIO
N (
dB
)
–80
–60
–40
–20
10k 1M 10M 100M
6244 G18
–120100
0
–110
–90
–70
–50
–30
–10TA = 25°CVS = ±2.5VAV = 1
LTC6244
126244fb
Minimum Supply VoltageOutput Short-Circuit Current vs Power Supply Voltage
Open-Loop Gain Open-Loop Gain Open-Loop Gain
Power Supply Rejection Ratio vs Frequency
Offset Voltage vs Output Current Warm-Up Drift vs Time Noise Voltage vs Frequency
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (Hz)
1k
40
PO
WER
SU
PP
LY R
EJE
CTIO
N R
ATIO
(dB
)
50
60
70
80
10k 1M100k 10M 100M
6244 G19
30
20
10
0
–10
90
100TA = 25°CVS = ±2.5V
NEGATIVESUPPLY
POSITIVESUPPLY
TOTAL SUPPLY VOLTAGE (V)
0
CH
AN
GE I
N O
FFS
ET V
OLT
AG
E (
μV
)
0
100
200
300
8
6244 G20
–100
–200
–50
50
150
250
–150
–250
–3002 4 61 93 5 7 10
TA = 125°CTA = 25°CTA = –55°C
VCM = VS/2
POWER SUPPLY VOLTAGE (±V)
1.5–50
OU
TP
UT S
HO
RT-
CIR
CU
IT C
UR
REN
T (
mA
)
–40
–20
–10
0
50
20
2.5 3.5 4
6244 G21
–30
30
40
10
2 3 4.5 5
TA = 125°CTA = 25°CTA = –55°C
SOURCING
SINKING
OUTPUT VOLTAGE (V)
–5–110
INP
UT V
OLT
AG
E (
μV
)
–100
–80
–70
–60
–40
–4 0 2
6244 G22
–90
–50
–1 4 5–3 –2 1 3
TA = 25°CVS = ±5V
RL = 10k
RL = 1k
OUTPUT VOLTAGE (V)
0–110
INP
UT V
OLT
AG
E (
μV
)
–100
–80
–70
–60
–40
0.5 2.5 3.5
6244 G23
–90
–50
2 4.5 51 1.5 3 4
TA = 25°CVS = 5V, 0V
RL = 10k
RL = 1k
OUTPUT VOLTAGE (V)
0
–40
–50
–60
–70
–80
–90
–100
–1101.5 2.5
6244 G24
0.5 1 2 3
INP
UT V
OLT
AG
E (
μV
)
TA = 25°CVS = 3V, 0V
RL = 100k
RL = 10k
OUTPUT CURRENT (mA)
–50
OFF
SET V
OLT
AG
E (
μV
)
200
150
100
50
0
–50
–100
–150
– 20030
6244 G25
–30 –10 10 5020–40 –20 0 40
VS = ±5V
TA = 125°C
TA = 25°C
TA = –55°C
TIME AFTER POWER UP (SEC)
0
CH
AN
GE I
N O
FFS
ET V
OLT
AG
E (
μV
)
–20
–15
–10
60
6244 G26
–30
–4510 20 30 40 505 15 25 35 45 55
–5
–25
–35
–40
TA = 25°C
VS = ±1.5V
VS = ±2.5V
VS = ±5V
FREQUENCY (Hz)
10NO
ISE V
OLT
AG
E (
nV
/√H
z)
20
25
35
40
10 1k 10k 100k
6244 G27
0100
30
15
5
TA = 25°CVS = ±2.5VVCM = 0V
LTC6244
136244fb
Series Output Resistance and Overshoot vs Capacitive Load
Series Output Resistance and Overshoot vs Capacitive Load
Settling Time vs Output Step (Noninverting)
0.1Hz to 10Hz Voltage Noise Noise Current vs Frequency
Settling Time vs Output Step (Inverting) Distortion vs Frequency
Maximum Undistorted Output Signal vs Frequency
Series Output Resistance and Overshoot vs Capacitive Load
TYPICAL PERFORMANCE CHARACTERISTICS
TIME (1s/DIV)
VO
LTA
GE N
OIS
E (
500nV
/DIV
)
6244 G28
VS = 5V, 0V
FREQUENCY (Hz)
100
NO
ISE C
UR
REN
T (
fA/√
Hz) 100
1000
1k 10k 100k
6244 G29
10
1
0.1
TA = 25°CVS = ±2.5VVCM = 0V
CAPACITIVE LOAD (pF)
100
OV
ER
SH
OO
T (
%)
10
20
30
40
60
100 1000
6244 G30
50
RS = 10Ω
RS = 50Ω
VOUT = 100mVVS = ±2.5VAV = –2
+
– RS
1k
30pF
500Ω
CL
CAPACITIVE LOAD (pF)
100
OV
ER
SH
OO
T (
%)
10
20
30
40
60
100 1000
6244 G31
50
RS = 10Ω
RS = 50Ω
VOUT = 100mVVS = ±2.5VAV = –1
+
– RS
1k
30pF
1k
CL
CAPACITIVE LOAD (pF)
100
OV
ER
SH
OO
T (
%)
10
20
30
40
60
100 1000
6244 G32
50
RS = 10Ω
RS = 50Ω
VOUT = 100mVVS = ±2.5VAV = 1
+
– RS
CL
OUTPUT STEP (V)
–4
SETT
LIN
G T
IME (
ns)
500
600
700
4
6244 G33
400
300
0–2 0 2–3 –1 1 3
200
100
900
1mV 1mV
800
VIN
VOUT
1k
+
–
VS = ±5VAV = 1TA = 25°C
NOTE: EXCEEDS INPUTCOMMON MODE RANGE
10mV10mV
OUTPUT STEP (V)
–4
SETT
LIN
G T
IME (
ns)
500
600
700
4
6244 G34
400
300
0–2 0 2–3 –1 1 3
200
100
900
1mV 1mV
800
VS = ±5VAV = –1TA = 25°C
10mV10mV
VINVOUT
1k
1k1k
+
–
FREQUENCY (Hz)
10k
5
OU
TP
UT V
OLT
AG
E S
WIN
G (
VP
-P)
7
10
100k 1M 10M
6244 G35
3
4
6
8
9
2
1
AV = –1
AV = +2
VS = ±5VTA = 25°CHD2, HD3 < –40dBc
FREQUENCY (Hz)
10k
–60
DIS
TO
RTIO
N (
dB
c)
–50
–40
–30
100k 1M 10M
6244 G36
–70
–80
–90
–100
VS = ±2.5VAV = +1VOUT = 2VP-P
RL = 1k, 2ND
RL = 1k, 3RD
LTC6244
146244fb
Distortion vs Frequency Distortion vs FrequencyDistortion vs Frequency
Large-Signal Response
Large-Signal Response Output Overdrive Recovery
Small-Signal Response Small-Signal Response
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (Hz)
10k
–60
DIS
TO
RTIO
N (
dB
c)
–50
–40
–30
100k 1M 10M
6244 G37
–70
–80
–90
–100
VS = ±2.5VAV = +2VOUT = 2VP-P
RL = 1k, 2ND
RL = 1k, 3RD
FREQUENCY (Hz)
10k
–60
DIS
TO
RTIO
N (
dB
c)
–50
–40
–30
100k 1M 10M
6244 G38
–70
–80
–90
–100
VS = ±5VAV = +1VOUT = 2VP-P
RL = 1k, 2ND
RL = 1k, 3RD
FREQUENCY (Hz)
10k
–60
DIS
TO
RTIO
N (
dB
c)
–50
–40
–30
100k 1M 10M
6244 G39
–70
–80
–90
–100
VS = ±5VAV = +2VOUT = 2VP-P
RL = 1k, 2ND
RL = 1k, 3RD
VS = ±2.5VAV = 1RL = ∞
0V
6244 G40200ns/DIV VS = ±2.5VAV = 1RL = ∞CL = 75pF
0V
6244 G41200ns/DIV VS = ±5VAV = 1RL = ∞
0V
6244 G422μs/DIV
VS = ±2.5VAV = –1RL = 1k
0V
6244 G43200ns/DIV VS = ±2.5VAV = 3RL = 3k
0VVIN
1V/DIV
VOUT2V/DIV
0V
6244 G44200ns/DIV
LTC6244
156244fb
Amplifi er Characteristics
Figure 1 is a simplifi ed schematic of the LTC6244, which has a pair of low noise input transistors M1 and M2. A simple folded cascode Q1, Q2 and R1, R2 allow the input stage to swing to the negative rail, while performing level shift to the Differential Drive Generator. Low offset voltage is accomplished by laser trimming the input stage.
Capacitor C1 reduces the unity cross frequency and im-proves the frequency stability without degrading the gain bandwidth of the amplifi er. Capacitor CM sets the overall amplifi er gain bandwidth. The differential drive generator supplies signals to transistors M3 and M4 that swing the output from rail-to-rail.
The photo of Figure 2 shows the output response to an input overdrive with the amplifi er connected as a voltage follower. If the negative going input signal is less than a diode drop below V–, no phase inversion occurs. For input signals greater than a diode drop below V–, limit the current to 3mA with a series resistor RS to avoid phase inversion.
The input common mode voltage range extends from V– to V+ – 1.5V. In unity gain voltage follower applications, exceeding this range by applying a signal that reaches 1V from the positive supply rail can create a low level instability at the output. Loading the amplifi er with several hundred micro-amps will reduce or eliminate the instability.
ESD
The LTC6244 has reverse-biased ESD protection diodes on all input and outputs as shown in Figure 1. These diodes protect the amplifi er for ESD strikes to 4kV. If these pins are forced beyond either supply, unlimited current will fl ow through these diodes. If the current transient is less than 1 second and limited to one hundred milliamps or less, no damage to the device will occur.
The amplifi er input bias current is the leakage current of these ESD diodes. This leakage is a function of the tem-perature and common mode voltage of the amplifi er, as shown in the Typical Performance Chacteristics.
Noise
The LTC6244 exhibits low 1/f noise in the 0.1Hz to 10Hz region. This 1.5μVP-P noise allows these op amps to be used in a wide variety of high impedance low frequency applications, where Zero-Drift amplifi ers might be inap-propriate due to their input sampling characteristic.
In the frequency region above 1kHz the LTC6244 also shows good noise voltage performance. In this frequency region, noise can easily be dominated by the total source
Figure 1. Simplifi ed Schematic Figure 2. Unity Gain Follower Test Circuit
APPLICATIONS INFORMATION
R2
6244 F01
VIN+
ITAIL
VIN–
VO
V+
V+
V–V–
V–
CM
DESD5
DIFFERENTIALDRIVE
GENERATOR
BIAS
DESD6
V+
DESD2
V+
DESD4
V–
DESD1
V–
DESD3
R1
Q1
M2M1
M3
M4
C1
Q2
+2.5V
RS0Ω
–2.5V
6244 F02
+
–1/2
LTC6244
VIN
VOUT
VOUT AND VIN OF FOLLOWER WITH LARGE INPUT OVERDRIVE
V+
2.5V
V–
–2.5V
LTC6244
166244fb
resistance of the particular application. Specifi cally, these amplifi ers exhibit the noise of a 4k resistor, meaning it is desirable to keep the source and feedback resistance at or below this value, i.e., RS + RG||RFB ≤ 4k. Above this total source impedance, the noise voltage is not dominated by the amplifi er.
Noise current can be estimated from the expression in = √2qIB, where q = 1.6 • 10–19 coulombs. Equating √4kTRΔf and RS√2qIBΔf shows that for source resistors below 50GΩ the amplifi er noise is dominated by the source resistance. See the Typical Characteristics curve Noise Current vs Frequency.
Proprietary design techniques are used to obtain simulta-neous low 1/f noise and low input capacitance. Low input capacitance is important when the amplifi er is used with high source and feedback resistors. High frequency noise from the amplifi er tail current source, ITAIL in Figure 1, couples through the input capacitance and appears across these large source and feedback resistors.
Stability
The good noise performance of these op amps can be attributed to large input devices in the differential pair. Above several hundred kilohertz, the input capacitance can cause amplifi er stability problems if left unchecked. When the feedback around the op amp is resistive (RF), a pole will be created with RF, the source resistance, source capacitance (RS, CS), and the amplifi er input capacitance.
In low gain confi gurations and with RF and RS in even the kilohm range (Figure 3), this pole can create excess phase shift and possibly oscillation. A small capacitor CF in parallel with RF eliminates this problem.
Achieving Low Input Bias Current
The DD package is leadless and makes contact to the PCB beneath the package. Solder fl ux used during the attach-ment of the part to the PCB can create leakage current paths and can degrade the input bias current performance of the part. All inputs are susceptible because the backside paddle is connected to V– internally. As the input voltage changes or if V– changes, a leakage path can be formed and alter the observed input bias current. For lowest bias current, use the LTC6244 in the MS8 package.
Photodiode Amplifi ers
Photodiodes can be broken into two categories: large area photodiodes with their attendant high capacitance (30pF to 3000pF) and smaller area photodiodes with relatively low capacitance (10pF or less). For optimal signal-to-noise performance, a transimpedance amplifi er consisting of an inverting op amp and a feedback resistor is most commonly used to convert the photodiode current into voltage. In low noise amplifi er design, large area photodiode amplifi ers require more attention to reducing op amp input voltage noise, while small area photodiode amplifi ers require more attention to reducing op amp input current noise and parasitic capacitances.
Figure 3. Compensating Input Capacitance
APPLICATIONS INFORMATION
+
–
CINCS 6244 F03
RF
RS
OUTPUT
CF
LTC6244
176244fb
Large Area Photodiode Amplifi ers
A simple large area photodiode amplifi er is shown in Figure 4a. The capacitance of the photodiode is 3650pF (nominally 3000pF), and this has a signifi cant effect on the noise performance of the circuit. For example, the photodiode capacitance at 10kHz equates to an impedance of 4.36kΩ, so the op amp circuit with 1MΩ feedback has a noise gain of NG = 1 + 1M/4.36k = 230 at that frequency. Therefore, the LTC6244 input voltage noise gets to the output as NG • 7.8nV/√Hz = 1800nV/√Hz, and this can clearly be seen in the circuit’s output noise spectrum in Figure 4b. Note that we have not yet accounted for the op amp current noise, or for the 130nV/√Hz of the gain resistor, but these are obviously trivial compared to the op
amp voltage noise and the noise gain. For reference, the DC output offset of this circuit is about 100μV, bandwidth is 52kHz, and the total noise was measured at 1.7mVRMS on a 100kHz measurement bandwidth.
An improvement to this circuit is shown in Figure 5a, where the large diode capacitance is bootstrapped by a 1nV/√Hz JFET. This depletion JFET has a VGS of about –0.5V, so that RBIAS forces it to operate at just over 1mA of drain current. Connected as shown, the photodiode has a reverse bias of one VGS, so its capacitance will be slightly lower than in the previous case (measured 2640pF), but the most drastic effects are due to the bootstrapping. Figure 5b shows the output noise of the new circuit. Noise at 10kHz is now 220nV/√Hz, and the 130nV/√Hz noise thermal noise fl oor of the 1M feedback resistor is discernible at low frequencies. What has happened is that the 7.8nV/√Hz of the op amp has been effectively replaced by the 1nV/√Hz of the JFET. This is because the 1M feedback resistor is no longer “looking back” into the large photodiode capacitance. It is instead looking back into a JFET gate capacitance, an op amp input capacitance, and some parasitics, approximately 10pF total. The large photodiode capacitance is across the gate-source volt-age of the low noise JFET. Doing a sample calculation at 10kHz as before, the photodiode capacitance looks like 6kΩ, so the 1nV/√Hz of the JFET creates a current noise of 1nV/6k = 167fA/√Hz. This current noise necessarily fl ows through the 1M feedback resistor, and so appears as 167nV/√Hz at the output. Adding the 130nV/√Hz of the resistor (RMS wise) gives a total calculated noise density of 210nV/√Hz, agreeing well with the measured noise of Figure 5b. Another drastic improvement is in bandwidth, now over 350kHz, as the bootstrap enabled a reduction of the compensating feedback capacitance. Note that the bootstrap does not affect the DC accuracy of the amplifi er, except by adding a few picoamps of gate current.
There is one drawback to this circuit. Most photodiode circuits require the ability to set the amount of applied reverse bias, whether it’s 0V, 5V, or 200V. This circuit has a fi xed reverse bias of about 0.5V, dictated by the JFET.
Figure 4b. Output Noise Spectral Density of the Circuit of Figure 4a. At 10kHz, the 1800nV/√Hz Output Noise is Due Almost Entirely to the 7.8nV Voltage Noise of the LTC6244 and the High Noise Gain of the 1M Feedback Resistor Looking Into the High Photodiode Capacitance
Figure 4a. Large Area Photodiode Transimpedance Amplifi er
APPLICATIONS INFORMATION
5V VOUT = 1M • IPDBW = 52kHzNOISE = 1800nV/√Hz AT 10kHz
IPD
RF1M
HAMAMATSULARGE AREAPHOTODIODE
S1227-1010BQCPD = 3000pF
CF3.9pF
–5V 6244 F04a
–
+
1/2LTC6244HV VOUT
1k 10k
FREQUENCY (Hz) 6244 F04b
100k
OU
TP
UT N
OIS
E (
800nV
/√H
z/D
IV)
LTC6244
186244fb
Figure 5b: Output Noise Spectral Density of Figure 5a. The Simple JFET Bootstrap Improves Noise (and Bandwidth) Drastically. Noise Density at 10kHz is Now 220nV/√Hz, About a 8.2x Reduction. This is Mostly Due to the Bootstrap Effect of Swapping the 1nV/√Hz of the JFET for the 7.8nV/√Hz of the Op Amp
Figure 5a. Large Area Diode Bootstrapping
Figure 6b: Output Spectrum of Circuit of Figure 6a, with Photodiode Bias at 0V. Photodiode Capacitance is Back Up, as in the Original Circuit of Figure 4a. However, it can be Reduced Arbitrarily by Providing Reverse Bias. This Plot Shows that Bootstrapping Alone Reduced the 10kHz Noise Density by a Factor of 6.2, from 1800nV/√Hz to 291nV/√Hz
Figure 6a. The Addition of a Capacitor and Resistor Enable the Benefi t of Bootstrapping While Applying Arbitrary Photodiode Bias Voltage VBB
by providing reverse bias, and the photodiode can also be reversed to support either cathode or anode connections for positive or negative going outputs.
The circuit on the last page of this data sheet shows fur-ther reduction in noise by paralleling four JFETs to attain 152nV/√Hz at 10kHz, a noise of 12 times less than the basic photodiode circuit of Figure 4a.
The solution is as shown in the circuit of Figure 6a, which uses a capacitor-resistor pair to enable the AC benefi ts of bootstrapping while allowing a different reverse DC voltage on the photodiode. The JFET is still running at the same current, but an arbitrary reverse bias may be applied to the photodiode. The output noise spectrum of the circuit with 0V of photodiode reverse bias is shown in Figure 6b. Photodiode capacitance is again 3650pF, as in the original circuit of Figure 4a. This noise plot with 0V bias shows that bootstrapping alone was responsible for a factor of 6.2 noise reduction, from 1800nV/√Hz to 291nV/√Hz at 10kHz, independent of photodiode capacitance. However, photodiode capacitance can now can be reduced arbitrarily
APPLICATIONS INFORMATION
5V VOUT = 1M • IPDBW = 350kHzOUTPUT NOISE = 220nV/√Hz
AT10kHz
IPD
RF1M
PHILIPSBF862JFET
RBIAS4.99k
HAMAMATSULARGE AREAPHOTODIODE
S1227-1010BQCPD = 3000pF
CF0.25pF
–5V
–5V
5V
6244 F04a
–
+
1/2LTC6244HV VOUT
5V VOUT = 1M • IPDBW = 250kHzOUTPUT NOISE = 291nV/√Hz
AT 10kHz
5V
VBB
IPD
RF1M
PHILIPSBF862JFET
HAMAMATSU LARGE AREAPHOTODIODE
S1227-1010BQCPD = 3000pF
CF0.25pF
–5V 6244 F06a
–
+
1/2LTC6244HV
–5V4.99k
4.7μFX7R
4.99k
VOUT
1k 10k
FREQUENCY (Hz) 6244 F05b
100k
OU
TP
UT N
OIS
E (
200nV
/√H
z/D
IV)
1k 10k
FREQUENCY (Hz) 6244 F06b
100k
OU
TP
UT N
OIS
E (
275nV
/√H
z/D
IV)
LTC6244
196244fb
Small Area Photodiode Amplifi ers
Small area photodiodes have very low capacitance, typically under 10pF and some even below 1pF. Their low capaci-tance makes them more approximate current sources to higher frequencies than large area photodiodes. One of the challenges of small area photodiode amplifi er design is to maintain low input capacitance so that voltage noise does not become an issue and current noise dominates. A simple small area photodiode amplifi er using the LTC6244 is shown in Figure 7. The input capacitance of the ampli-fi er consists of CDM and one CCM (because the +input is
Figure 8a: Using Both Op Amps for Higher Bandwidth. A1 Provides a Gain of 3 Within the Loop, Increasing the Gain Bandwidth Product. This Bootstraps the CDM Accross A1’s Inputs, Reducing Amplifi er Input Capacitance. Inversion is Provided by A2, so that the Photodiode Looks Into a Noninverting Input. Pin 5 was Selected Because it is in the Corner, Removing One Lead Capacitance
Figure 7. LTC6244 in a Normal TIA Confi guration
grounded), or about 6pF total. The small photodiode has 1.8pF, so the input capacitance of the amplifi er is dominating the capacitance. The small feedback capacitor is an actual component (AVX Accu-F series), but it is also in parallel with the op amp lead, resistor and parasitic capacitances, so the total real feedback capacitance is probably about 0.4pF. The reason this is important is that this sets the compensation of the circuit and, with op amp gain band-width, the circuit bandwidth. The circuit as shown has a bandwidth of 350kHz, with an output noise of 120μVRMS measured over that bandwidth.
The circuit of Figure 8a makes some slight improvements. Operation is still transimpedance mode, with RF setting the gain to 1MΩ. However, a noninverting input stage A1 with a gain of 3 has been inserted, followed by the usual inverting stage performed by A2. Note what this achieves. The amplifi er input capacitance is bootstrapped by the feedback of R2:R1, eliminating the effect of A1’s input CDM (3.5pF), and leaving only one CCM (2.1pF). The op amp at Pins 5, 6 and 7 was chosen for the input amplifi er to eliminate extra pin-to-pin capacitance on the (+) input. The lead capacitance on the corner of an MSOP package is only about 0.15pF. By using this noninverting confi gura-tion, input capacitance is minimized.
APPLICATIONS INFORMATION
5V
VOUT = 1M • IPDBW = 350kHzNOISE = 120μVRMSMEASURED ON A 350kHz BW
IPD
RF1M
SMALL AREAPHOTODIODE
VISHAYTEMD1000
CPD = 1.8pF
CF0.1pF
–5V
–5V
6244 F07
–
+
1/2LTC6244HV VOUT
5V
–5V
IPD
RF1M
R31k
R21k
R46.98k
R1499Ω
SMALL AREAPHOTODIODE
VISHAYTEMD1000
CPD = 1.8pF
0.07pF(PARASITIC)
C2150pF
C156pF
–5V 6244 F08a–
+ A1 1/2
LTC6244HV
VOUT
8
4
1
7
5
6–
+
A2 1/2LTC6244HV
2
3
VOUT = 1M • IPDBW = 1.6MHzNOISE = 1.2mVRMSMEASURED ON A 2MHz BW
LTC6244
206244fb
Figure 8b: Output Noise Spectrum of the Circuit in Figure 8a. Noise at 1MHz is 782nV/√Hz, Due Mostly to the Input Current Noise Rising with Frequency
Total capacitance at the amplifi er’s input is now one CCM (2.1pF) plus the photodiode capacitance CPD (1.8pF), or about 4pF accounting for parasitics. The shunt impedance at 1MHz, for example, is XC = 1/(2πfC) = 39.8kΩ, and therefore, the noise gain at 1MHz is NG = 1+Rf/XC = 26. The input voltage noise of this amplifi er is about 15nV/√Hz, after accounting for the effects of R1 through R3, the noise of the second stage and the fact that voltage noise does rise with frequency. Multiplying the noise gain by the input voltage noise gives an output noise density due to voltage noise of 26 • 15nV/√Hz = 390nV/√Hz. But the noise spectral density plot of Figure 8b shows an output noise of 782nV/√Hz at 1MHz. The extra output noise is due to input current noise, multiplied by the feedback impedance. So while the circuit of Figure 8a does increase bandwidth, it does not offer a noise advantage. Note, however, that the 1.2mVRMS of noise is now measured in a 2MHz bandwidth, instead of over a 350kHz bandwidth of the previous example.
A Low Noise Fully Differential Buffer/Amplifi er
In differential signal conditioning circuits, there is often a need to monitor a differential source without loading or
adding appreciable noise to the circuit. In addition, add-ing gain to low level signals over appreciable bandwidth is extremely useful. A typical application for a low noise, high impedance, differential amplifi er is in the baseband circuit of an RFID (radio frequency identifi cation) receiver. The baseband signal of a UHF RFID receiver is typically a low level differential signal at the output of a demodulator with differential output impedance in the range of 100Ω to 400Ω. The bandwidth of this signal is 1MHz or less.
The circuit of Figure 9a uses an LTC6244 to make a low noise fully differential amplifi er. The amplifi er’s gain, input impedance and –3dB bandwidth can be specifi ed indepen-dently. Knowing the desired gain, input impedance and –3dB bandwidth, RG, CF and CIN can be calculated from the equations shown in Figure 9b. The common mode gain of this amplifi er is equal to one (VOUTCM = VINCM) and is independent of resistor matching. The component values in the Figure 9a circuit implement a 970kHz, gain = 5, differential amplifi er with 4k input impedance. The output differential DC offset is typically less than 500μV. The differential input referred noise voltage density is shown in Figure 10. The total input referred noise in a 1MHz bandwidth is 16μVRMS.
APPLICATIONS INFORMATION
50k 1M
FREQUENCY (Hz) 6244 F08b
5M
OU
TP
UT N
OIS
E (
150nV
/√H
z/D
IV)
LTC6244
216244fb
A Low Noise AC Difference Amplifi er
In the signal conditioning of wideband sensors and trans-ducers, a low noise amplifi er is often used to provide gain for low level AC difference signals in the frequency range of a few Hertz to hundreds of kilo-Hertz. In addition, the amplifi er must reject common mode AC signals and its input impedance should be higher than the differential source impedance. Typical applications are piezoelectric sensors used in sonar, sound and ultrasound systems and LVDT (linear variable differential transformers) for displacement measurements in process control and robotics.
The Figure 11a circuit is a low noise, single supply AC difference amplifi er. The amplifi er’s low frequency –3dB bandwidth is set with resistor R5 and capacitor C3, while the upper –3dB bandwidth is set with R2 and C1. The input common mode DC voltage can vary from ground to V+ and the output DC voltage is equal to the VREF voltage. The amplifi er’s gain is the ratio of resistors R2 to R1 (R4 = R2 and R3 = R1). The component values in the circuit of Figure 11a implement an 800Hz to 160kHz AC ampli-fi er with a gain equal to 10 and 12nV/√Hz input referred voltage noise density shown in Figure 11b. The total input referred wideband noise is 4.5μVRMS, in the bandwidth of 500Hz to 200kHz.
Input Impedance = 2 • RIN
Gain =VOUT
+ – VOUT–
VIN+ – VIN
–=
RGRIN
Maximum Gain = 5MHzf3dB
CF =1
4398 • f3dB • Gain + 2( )
CIN =Gain+ 2
8.977 • Gain •RIN • f3dB
f3dB =1
4000 • π2 •RG • CF • CIN
Figure 9b. Design Equations for Figure 9a Circuit
Figure 10. Differential Input Referred Noise
Figure 9a. Low Noise Fully Differential Buffer/Amplifi er (f–3dB = 970kHz, Gain = 5, RIN = 4k)
APPLICATIONS INFORMATION
2k2kVIN
+
RG10k
RIN2k
RIN2k
CIN82pF
CIN82pF
CF33pF
CF33pF
–
+1/2
LTC6244 VOUT+
–
+
1/2LTC6244 VOUT
–
2k
6244 F09a
V+
V–
2k
RG10k
VIN–
32
28
24
20
16
12
8
10k 100k
FREQUENCY (Hz) 6244 F10
1M4IN
PU
T R
EFE
RR
ED
NO
ISE (
nV
/√H
z)
f–3dB = 970kHzGAIN = 5RIN = 4k
LTC6244
226244fb
Figure 11b. Input Referred Noise
Figure 11a. Low Noise AC Difference Amplifi er (Bandwidth 800Hz to 160kHz, Gain = 10)
VOUT = GAIN • V2 – V1( ) + VREF
GAIN=R2R1
R3 =R1, R4 =R2, C1= C2
BANDWIDTH= fHI – fLO
fHI =1
2 • π •R2 • C1, fLO =
12 • π •R5 • C3
APPLICATIONS INFORMATION
R5200k
V+
R220k
R420k
C247pF
R32k
V2
V1
VOUT
VREF
6244 F11a
R12k
C147pF
C31000pF
–
+1/2 LTC6244
–
+
1/2 LTC6244
28
24
20
16
12
8
1 10
FREQUENCY (kHz) 6244 F11b
1000
4
0INP
UT R
EFE
RR
ED
NO
ISE (
nV
/√H
z)
BW = 800Hz TO 160kHzGAIN = 10
LTC6244
236244fb
PACKAGE DESCRIPTION
0.25 ± 0.05
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONSAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.65 ±0.05(2 SIDES)2.10 ±0.05
0.50BSC
0.70 ±0.05
3.5 ±0.05
PACKAGEOUTLINE
3.00 ±0.10(4 SIDES)
NOTE:1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10(2 SIDES)
0.75 ±0.05
R = 0.125TYP
2.38 ±0.10
14
85
PIN 1TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 0509 REV C
0.25 ± 0.050.50 BSC
DD Package8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
LTC6244
246244fb
MS8 Package8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
MSOP (MS8) 0307 REV F
0.53 ± 0.152(.021 ± .006)
SEATINGPLANE
NOTE:1. DIMENSIONS IN MILLIMETER/(INCH)2. DRAWING NOT TO SCALE3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18(.007)
0.254(.010)
1.10(.043)MAX
0.22 – 0.38(.009 – .015)
TYP
0.1016 ± 0.0508(.004 ± .002)
0.86(.034)REF
0.65(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 3 4
4.90 ± 0.152(.193 ± .006)
8 7 6 5
3.00 ± 0.102(.118 ± .004)
(NOTE 3)
3.00 ± 0.102(.118 ± .004)
(NOTE 4)
0.52(.0205)
REF
5.23(.206)MIN
3.20 – 3.45(.126 – .136)
0.889 ± 0.127(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038(.0165 ± .0015)
TYP
0.65(.0256)
BSC
LTC6244
256244fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORYREV DATE DESCRIPTION PAGE NUMBER
B 12/09 Change to Figure 2 15
(Revision history begins at Rev B)
LTC6244
266244fb
Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006
LT 1209 REV B • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
LTC1151 ±15V Zero-Drift Op Amp Dual High Voltage Operation ±18V
LT1792 Low Noise Precision JFET Op Amp 6nV/√Hz Noise, ±15V Operation
LTC2050 Zero-Drift Op Amp 2.7 Volt Operation, SOT-23
LTC2051/LTC2052 Dual/Quad Zero-Drift Op Amp Dual/Quad Version of LTC2050 in MS8/GN16 Packages
LTC2054/LTC2055 Single/Dual Zero-Drift Op Amp Micropower Version of the LTC2050/LTC2051 in SOT-23 and DD Packages
LTC6087/LTC6088 Dual/Quad 14MHz CMOS Op Amps Rail-to-Rail, Low Cost
LTC6240/LTC6241/LTC6242
Single/Dual/Quad, 18MHz CMOS Op Amps Low Noise, Rail-to-Rail
TYPICAL APPLICATIONUltralow Noise Large Area Photodiode Amplifi er
Photodiode Amplifi er Output Noise Spectal Density
RELATED PARTS
5V
VOUT = 1M • IPDBW = 400kHzNOISE = 150μVRMSMEASURED ON 100kHzBANDWIDTH
5V
5V
5V
C1
J1
R54.99k
C1 TO C4: 4.7μF X7RJ1 TO J4: PHILIPS BF862 JFETSR1 TO R4: 4.99k
C2 C3 C4 IPD
RF1M
R1
R2
HAMAMATSULARGE AREAPHOTODIODE
S1227-1010BQCPD = 3000pF
CF0.25pF
–5V
6244 TA02a
–
+
1/2LTC6244HV VOUT
J2
J3
R3
5V –5V
–5V
J4
R4
1 10
(kHz) 6244 TA02b
100
OU
TP
UT N
OIS
E (
200nV
/√H
z/D
IV)