Linc Cherix Pa

8/12/2019 Linc Cherix Pa

1/105

Chireixs / LINC Power Amplifierfor Base Station Applications Using GaN Devices

with Load Compensation

by

Jijun Bi

TU-Delft Mentors:

Dr. ing. L.C.N. de Vreede

Jawad Qureshi, Marco Pelk

NXP Mentors:

John Gajadharsing

Mark van der Heijden

Delft University of Technology, September 2008.

A thesis submitted to the Electrical Engineering, Mathematics and Computer

Science Department of Delft University of Technology in partial fulfillment of

the requirements for the degree ofMaster of Science.


2/105


3/105

Approval

Name: Jijun Bi

Degree: Master of Science

Title of Thesis: Chireixs / LINC Power Amplifier for Base Station

Applications Using GaN Devices with Load Compensation

Committee in Charge of Approval:

Chair: ____________________

Department of Electrical Engineering

Committee member: ____________________


____________________


____________________


____________________



4/105


5/105

Abstract

New generations wireless communication systems require linear efficient RF power

amplifiers for higher data transmission rates. However, conventional RF power amplifiers are

normally designed for peak efficiency under maximum output power condition. Consequently,

when the power is backed-off from its maximum point, the amplifier efficiency drops sharply. As

a result, the mean amplifier efficiency is much lower than the efficiency at peak power level.

The Chireix outphasing power amplifier is one of the most promising techniques that can

simultaneously provide high efficiency and high linearity. Such approach was the origin of the

term LINC (LInear amplification using Nonlinear Components), a technique that allows the

power amplifiers to continuously operate at their peak power efficiency while providing an

almost undistorted output signal. In this project, a Chireix outphasing amplifier for 2.14 GHz

with load compensation has been fabricated using GaN HEMTs delivered by CREE. A

considerable efficiency improvement has been achieved. The simulation result shows that the

drain efficiency of 74% is obtained at 49 dBm peak output power, and the efficiency is kept

above 55% over 10 dB power back-off range. The drain efficiency of 70% is measured at 48.5

dBm output power.

To meet an increasing demand for wireless communication terminals to handle multi-band

multi-mode operation, multi-band multi-mode power amplifiers are urgently needed. An

investigation into how to implement multi-band Chireixs outphasing amplifiers has been carried

out. Two proposals for implementing potential dual-band Chireixs amplifiers have been

presented.

In addition, a comparison of the efficiency under the condition of static load modulation has

been made between GaN HEMT devices and LDMOS devices. The result of the comparison is

that GaN HEMT devices conspicuously outperform LDMOS devices in terms of drain efficiency

under static load modulation.


6/105


7/105

Acknowledgements

First, I would like to express my sincere gratitude to my mentor Dr. Leo de Vreede forgranting me such a good opportunity to conduct this interesting research and for his guidance

and encouragement during the project.

Second, I would like to thank the members of HiTeC Group for their assistance,

cooperation, and encouragement. Special thanks are given to Mr. Jawad Qureshi for his

continuous help throughout the whole project, to Mr. Marco Pelk for providing the input

stabilization network, valuable discussions, and timely help in the final phase of my project,

and to Mr. W. C. Edmund Neo for helping me in simulations.

Next, I would also like to thank NXP Semiconductors for offering me a traineeship

opportunity during 2007 and 2008.

Finally, My family and my friends have always given me strong support and

encouragement in my studies and in other aspects of my life in the Netherlands. Without

them, this work would never have been accomplished.


8/105


9/105

Contents

Chapter 1 Introduction ................................................................................................ 1

1.1 Project motives and objectives ............................................................................... 11.2 Thesis structure ........................................................................................................ 2

Chapter 2 Chireixs outphasing amplifier.............................................................. 5

2.1 Outphasing operation.............................................................................................. 52.1.1 A mathematical description of Chireix's outphasing operation ................62.1.2 Theoretical efficiency of Chireix's outphasing amplifier ............................8

2.2 A practical common-mode topology of Chireix's outphasing system ...........152.3 A summary of Chireixs outphasing operation ................................................. 22

Chapter 3 Design of a Chireix's/LINC ampli fier.................................................. 25

3.1 Design strategies and procedure.......................................................................... 253.2 Amplifier and power combiner choices.............................................................. 263.3 Power amplifier cell design .................................................................................. 27

3.3.1 Device characterization and bias points ..................................................... 293.3.2 Device stabilization........................................................................................ 323.3.3 Partially compensating the parasitic effects of the package ....................343.3.4 Load-pulldetermining the optimum load impedance..........................353.3.5 Functionality verification with ideal components ....................................39

3.3.6 Implementation with realistic components................................................ 413.4 Chireix's outphasing system design .................................................................... 44

3.4.1 Power combiner design................................................................................. 443.4.2 Chireixs outphasing system without load compensation.......................483.4.3 Load adjustment for Chireixs/LINC operation .......................................533.4.4 Load compensation........................................................................................ 553.4.5 Ideal implementation of Chireixs outphasing system.............................563.4.6 Practical implementation of Chireixs outphasing system ......................61

3.5 Layout implementation and measured results.................................................. 663.6 Summary ................................................................................................................. 68

Chapter 4 Potential solutions to multi-band Chireix's/LINC amplifier.........69

4.1 A review of several current multi-band PA implementation ..........................694.2 Proposals for implementing multi-band Chireixs amplifiers.........................71

4.2.1 Dual-band Chireixs amplifier based on resonators ..................................714.2.2 Dual-band Chireixs amplifier based on transmission lines.....................74

4.3 Summary ................................................................................................................. 76


10/105

Chapter 5 Efficiency comparison under static load modulation betweenGaN HEMT and LDMOS ..................................................................................................... 77

5.1 Research motivation .............................................................................................. 775.2 Device models......................................................................................................... 785.3 Simulation procedures of static load modulation ............................................. 79

5.4 GaN HEMT 45-watt model................................................................................... 815.4.1 Harmonic termination.................................................................................... 815.4.2 Optimum load ................................................................................................. 835.4.3 Static load modulation ................................................................................... 86

5.5 LDMOS 45-watt model.......................................................................................... 875.5.1 Harmonic termination.................................................................................... 875.5.2 Optimum load ................................................................................................. 885.5.3 Static load modulation ................................................................................... 89

5.6 Comparison and conclusion ................................................................................. 91Chapter 6 Conclusions and suggestions ............................................................. 93

6.1 Conclusions ............................................................................................................. 93

6.2 Suggestions ............................................................................................................. 94References ............................................................................................................................ 95


11/105

Chapter 1. Introduction

1

Chapter 1

Introduction

1.1 Project motives and objectives

The boom of the wireless market, combined with the intense competition of the past two

decades, has stimulated unprecedented interest in the performance of low-cost and physically

compact radio frequency (RF) power amplifiers. Interest in performance was induced by the

significant impacts that power amplifiers have on wireless communication systems. As far as

base station applications are concerned, power amplifiers affect them primarily in two

aspects. Firstly, as the final stage in the transmitter chain, the power amplifier (PA) has a

significant impact on the total power consumption of the base station. Here low power

consumption will result in low operation costs, something that is a substantial market

advantage. Consequently, to achieve low operation costs the PA should have high efficiency,

not only for the peak-power levels but also for signal with varying envelopes yielding high

peak-to-average power ratios. Secondly, PA nonlinearity can cause spectral spreading of the

amplified signal, resulting in channel-to-channel interference. To avoid this, the PA must be

as linearly as possible.

Figure 1.1: Efficiency and linearity trade-off in RF power amplifiers

Therefore, two specificationsefficiency and linearityneed to be dealt with.

Unfortunately, instead of being independent, PA efficiency and linearity are usually


12/105


2

conflicting requirements. For instance, for those systems that employ envelope-varying

modulation schemes, a direct trade-off exists between the linearity and efficiency of the

power amplifier. E.g. conventional PAs that operate in class-A, class-AB, and class-B can be

linear, but are typically inefficient, not only in terms of peak efficiency, but even more in

power back-off when amplifying envelope-varying signals. Switch mode PAs like class-D,

class-E, and class-F can have high efficiency, but they are usually nonlinear in nature

yielding intermodulation distortion (IMD) which results in spectral spreading. Consequently,

the main question is how to achieve high efficient amplification with sufficient linearity for

envelope varying signals. To tackle this problem up to date (Figure 1.1), several methods

have been proposed. An interesting but somewhat neglected concept to solve for the

efficiency-linearity trade-off is Chireix's outphasing amplifier, also referred to as "linear

amplification using nonlinear components" (LINC). Within NXP progress has already been

made with this amplifier concept yielding encouraging results and some patent applications.

Meanwhile, a prior M.Sc. study by R. Liu at the TUDelft for application of this amplifier

concept in handset PAs has yielded new insights and concepts to further improve the original

Chireix's concept. One objective of this project is to combine these existing insights to a new

high power amplifier implementation facilitating high efficiency and linearity for base station

applications. For this purpose use will be made from state-of-the-art Gallium Nitride (GaN)

devices from CREE.

In addition, there is an increasing demand for wireless communication terminals to

handle multi-band multi-mode operation with a single Power Amplifier. Consequently, to

address this need multi-band PAs are needed that do not require extensive filter banks. So

the second objective of the project is to review potential implementations of multi-band PAs

and to evaluate the feasibility of realizing a multi-band Chireix's outphasing amplifier.

As a supplementary topic, the drain efficiencies in class-B mode operation under static

load modulation have been investigated for GaN HEMT devices and LDMOS devices.

Simulation results show that under static load modulation GaN HEMT devices demonstrate

much better drain efficiencies than do LDMOS devices.

1.2 Thesis structure

Chapter 2 describes the concept of Chireix's outphasing amplifier. First, based on a

differential topology, the principle of Chireixs outphasing operation is introduced. Then, for

two types of power combiner topologies, the varying load seen by the PA and the ideal drain

efficiency are derived. These theoretical results convincingly prove the advantage of


13/105


3

Chireixs outphasing amplifier as an efficiency enhancement technique.

Chapter 3 discusses the design procedure of a Chireix's outphasing amplifier in detail.

Section 3.1 and 3.2 outline the methodology and strategies that have been adopted in the

design of Chireix's outphasing amplifier. Section 3.3 gives details related to the design of the

PA cell, including device evaluation, choice of operation class, load-pull simulation, and the

realization of the input and output matching network. Section 3.4 describes the design of the

overall Chireix's outphasing system. Close attention is paid to the compensation of the

parasitic reactance in device package, the realization of the power combiner, and the load

adjustment for outphasing operation. A detailed design process has been described by

presenting circuit schematic and simulation results in every step from concept verification

with ideal devices and components to the real implementation with actual active devices and

practical components. Section 4.5 shows the actual layout implementation of the Chireix

amplifier and its measured results. A summary of Chapter 3 is given in the last section.

Chapter 4 presents the research on potential multi-band amplifiers. This research

comprises two parts. The first part is a review of current multi-band PA implementations. In

the second part several suggestions on how to implement a multi-band Chireix's outphasing

amplifier are proposed.

Chapter 5 describes the comparison of the drain efficiency under static load modulation

between GaN HEMT devices and LDMOS devices.

Chapter 6 concludes the thesis by giving some suggestions on the future work of

Chireixs outphasing amplifier.


14/105


4


15/105

Chapter 2. Chireixs outphasing amplifier

5

Chapter 2

Chireixs outphasing amplifier

2.1 Outphasing operation

Outphasing operation is a technique with a long history that was first proposed by Henri

Chireix in 1935 to improve average efficiency and linearity of AM broadcast transmitters.

This idea has been revived and applied to various wireless applications since it was

reinvented by D. C. Cox, who introduced the term LINC (LInear amplification using

Nonlinear Components) in 1974. LINC was invented to realize a linear amplifier where theintermediate stages of RF power amplification could employ highly nonlinear devices.

Figure 2.1: Simplified block diagram of an outphasing system

Figure 2.1illustrates a simplified diagram of an outphasing system. The concept itself is

very simple. An amplitude modulated (AM) signal is first separated by the signal component

separator (SCS) into two phase modulated (PM) signals that have equal constant envelopes

and opposite modulated phase variations. These two constant-envelope PM signals are then

amplified separately by two independent identical PAs. Finally, these two amplified signals

are combined at the output of the PAs to produce an amplified replica of the original AMsignal.

The key element in a Chireixs outphasing system is the SCS, which converts the input

AM signal into two outphased component PM signals that have constant envelopes. It is

exactly such modulation conversion that brings the possibility of highly efficient and highly


16/105


6

linear amplification. Because the envelopes of the signals to be amplified are now fixed and

the magnitude of the envelopes contains no information (all the amplitude information of the

original AM signal is contained in the phase of the component PM signals), we can employ

PA cells in the branches which have an extremely high peak efficiency. Consequently, the

Chireixs outphasing amplifier system can act as an interesting efficiency enhancement

technique. Meanwhile, also thanks to the fixed envelope in the branch amplifiers, the

nonlinearity of the input-output power characteristic as present in most high-efficiency PA

implementation will have very little influence on the overall input-output transfer function of

the Chireixs outphasing system. As a result, the total system can be highly linear over a wide

range of signal levels, provided the SCS and the power combiner do not introduce nonlinear

signal distortion. In practice, for the branch amplifiers, the most high-efficiency PAs or even

constant-amplitude phase-locked oscillators can be used to realize linear amplification, which

explains the acronym LINC that is typically used for these types of amplifiers.

In summary, theoretically Chireixs outphasing operation provides a clear, simple, and

promising solution for simultaneously achieving high efficiency and high linearity in a power

amplifier system. However, as explained later, practical implementation aspects of a

Chireixs outphasing amplifier can be complicated.

2.1.1 A mathematical description of Chireix's outphasing operation

The whole process of Chireixs outphasing operation consists of three stepssignal

component separation, signal amplification, and signal combination, which are realized

respectively by the SCS, the PAs, and the power combiner. The topology of the power

combiner has an influence on the signal component separation that should be implemented.

The principle of Chireixs outphasing operation will be described for the case of a non-

isolating power combiner with a differential topology, as shown in Figure 2.2.

Figure 2.2: A Chireix outphasing system with a differential-topology power combiner


17/105


7

The input AM signal, which may also include phase modulation, is denoted by

( ) ( ) cos[ ( )]; 0 ( )in mS t E t t t E t E = + (Equation 2.1)

where ( )E t is the real envelope and ( )t represents the original phase modulation in theinput AM signal. This input signal is separated by the SCS into two constant-envelope PM

signals having equal envelopes and opposite modulated phase variations

1

2

( ) sin[ ( ) ( )]2

( ) sin[ ( ) ( )]2

m

m

ES t t t t

ES t t t t

= + +

= +

(Equation 2.2)

wherem

E is the maximum value of ( )E t and the outphasing angle ( )t produced by the

SCS is

( )( ) arcsin[ ]; 0 ( )

2m

E tt t

E

= (Equation 2.3)

1( )S t and 2 ( )S t are related to ( )inS t as follows:

1 2( ) ( ) {sin[ ( ) ( )] sin[ ( ) ( )]}2

sin[ ( )] cos[ ( )]

( ) cos[ ( )]

( )

m

m

in

ES t S t t t t t t t

E t t t

E t t t

S t

= + + +

= +

= +

=(Equation 2.4)

Figure 2.3: A complex phasor representation of Chireixs outphasing operation

Figure 2.3illustrates this relationship expressed by the corresponding complex phasors.

( )t ( )t

2 ( )S t

1( )S t

( )inS t

2( )S t

( )j te


18/105


8

The real signals are related to the corresponding complex phasors as follows:

1 1 1

2 2 2

( ) Re{ ( ) exp( )} where ( ) ( ) exp[ ( )]

( ) Re{ ( ) exp( )} where ( ) exp{ [ ( ) ( )]}

2 2

( ) Re{ ( ) exp( )} where ( ) exp{ [ ( ) ( )]}2 2

in in in

m

m

S t S t j t S t E t j t

ES t S t j t S t j t t

ES t S t j t S t j t t

= =

= = +

= =

(Equation 2.5)

These two constant-envelope PM signals are separately amplified by two independent

identical PAs. The output signals from the PAs are

1 1

2 2

` ( ) ( ) sin[ ( ) ( )]2

` ( ) ( ) sin[ ( ) ( )]2

m

m

ES t G S t G t t t

ES t G S t G t t t

= = + +

= = + (Equation 2.6)

where G is the identical amplifier gain. Because of the differential topology of the

power combiner, the final output at the load resistor LR is

1 2 1 2( ) ` ( ) ` ( ) [ ( ) ( )] ( ) ( ) cos[ ( )]out inS t S t S t G S t S t G S t G E t t t = = = = +

(Equation 2.7)

This final differential signal at the load resistor shows full recovery of the original AMsignal. Meanwhile, the original phase modulation (t) in the input AM signal passes through

the system unmodified.

2.1.2 Theoretical efficiency of Chireix's outphasing amplifier

As mentioned before, in Chireixs outphasing system, nonlinear PAs can be employed to

realize linear amplification. These amplifiers can be so heavily saturated that the device will

have rail-to-rail voltage swing. Under these conditions, the device can be approximated as a

fixed RF voltage source. In the case of shorted harmonics (class-B), the amplitude of the RF

voltage source can be approximated by the dc supply voltage. In this section, the efficiency

of Chireixs outphasing amplifier will be derived based on the following assumptions:

Heavily saturated class-B amplifiers are used for signal amplification so that the PAsare approximated as ideal voltage sources that have an amplitude equal to dc supply

voltage.


19/105


9

Harmonic shorts at the output ensure that the output voltage is a pure fundamental tonehaving a sinusoidal form.

A differential-topology lossless power combiner is used for signal combination

Figure 2.4: Simplified output schematic of Chireixs outphasing system

Based on these assumptions, the output of the Chireixs outphasing system can be

simplified into a diagram shown in Figure 2.4. The voltages of those two voltage sources can

be expressed in the following phasor notation:

(cos sin )

(cos sin )

with and 02

j

j

dc

e j

e j

V

1 o o

2 o o

o

V V V

V V V

V

+

= = +

= =

=

(Equation 2.8)

The voltage across the RF load resistorRLis

2 sinjL 1 2 oV V V V = = (Equation 2.9)

Recall (Equation 2.3 and (Equation 2.5, in the form of voltage signal they become

( )( ) arcsin[ ]

( )exp{ ( )}; 0 ( )

exp{ [ ( ) ( )]} exp[ ( )]2 2

exp{ [ ( ) ( )]} exp[ ( )]2 2

where is the voltage gain of the PAs and

exp2

m

m

mv

mv

v

mv

E tt

E

V t j t V t V

VA j t t j t

VA j t t j t

A

VA

in

1 o

2 o

o

V (t)

V (t) V

V (t) V

V

=

=

= + = +

= =

= { [ ( ) ]}2

j t

(Equation 2.10)

Then the differential output voltage is given by


20/105


10

2 sin

( )2 exp{ [ ( ) ]} exp( )

2 2 2

( )exp[ ( )]

mv

m

v

v

j

V V tA j t j

V

A V t j t

A

=

=

=

=

L o

in

V (t) V

V (t)

(Equation 2.11)

which is exactly an amplified recovery of the original input voltage.

The impedances seen by each of the voltage sources are

cos sin(1 cot )

2 sin 2

cos sin(1 cot )

2 sin 2( )

LL

L

LL

L

j RR j

j

R

j RR j

jR

11

1 2

*22 1

1 2

VZ

V V

VZ Z

V V

+= = =

= = = + =

(Equation 2.12)

The corresponding admittances are

2

2

2

1 2sin sin 2

1 2sin sin 2

2sin sin 2where and

o o

L L

o o

L L

o o

L L

j G jBR R

j G jBR R

G BR R

1

1

*

2 1

2

YZ

Y YZ

= = + = +

= = = =

= =

(Equation 2.13)

The RF power delivered to the load is

2* 2

1

2* 2

2 1

2

1 2

1 1 1Re{( ) } Re{ }

2 2 2

1 1 1Re{( ) } Re{ }

2 2 2

RF dc o

RF dc o RF

RF RF RF dc o

P V G

P V G P

P P P V G

*

1 1 1 1 1

*

2 2 2 2 2

V Y V V Y

V Y V V Y

= = =

= = = =

= + =

(Equation 2.14)

For a class-B amplifier, the dc currentIdcis related to the fundamental current component

I1as follows:


21/105


11

1

2 2 2 2 2 2dc dc dc dc

I I V V Vfund 1 1 1 2I V Y Y Y Y

= = = = =

(Equation 2.15)

The total DC power dissipated by the PAs is

242dc dc dc dcP I V V Y

= = (Equation 2.16)

Consequently, the theoretical efficiency of the Chireixs outphasing amplifier is given by

2 2cos( )

4 4

where is the theoretical efficiency of a class B amplifier4

RF o oB

dc o o

B

P G G

P G B

= = = = +

=

YY

(Equation 2.17)

Therefore, the theoretical efficiency of the Chireixs outphasing amplifier is the

efficiency of a class-B amplifier multiplied by the cosine of the phase angle of the load

(either admittance or impedance) presented to either voltage source. This conclusion is a

direct result from the symmetrical topology of the Chireixs outphasing system that consists

of two PA branches, and it does not depend on the topology of the power combiner as long as

it is lossless.

For the differential-topology power combiner, the final efficiency expressed in the form

of the outphasing angle is

cos( ) sinB B

Y = = (Equation 2.18)

Because

2

2 2 2 22

2sin

cos( ) sin

2sin sin 2

o L

o o

L L

G R

G B

R R

Y

= = =+ +

(Equation 2.19)


22/105


12

(a) (b)

Figure 2.5: Theoretical efficiency of the Chireixs outphasing amplifier (without load compensation);

(a) Efficiency versus outphasing angle (b) Efficiency versus normalized output power

Consequently, the efficiency significantly drops as the outphasing angle decreases,

which is shown in Figure 2.5. The degradation of the efficiency is caused by the increase

impact of the susceptance component on the admittance presented to each PA. To address

this problem, Chireix proposed the load compensation method; the basic idea of this method

is to compensate the susceptance component by adding a proper shunt reactance.

22sin sin 2

where ando o

L L

G B

R R

= =

Figure 2.6: Load admittances presented to each outphasing PA; (a) upper branch (b) lower branch

(a) (b)Figure 2.7: Normalized conductance and susceptance seen by the PA versus outphasing angle

(a) normalized conductance (b) normalized susceptance

According to (Equation 2.13, the admittance presented to each PA consists of a

conductive part Goand a susceptive partBoor -Bo, as illustrated in Figure 2.6. As mentioned


23/105


13

before, the culprit for the degradation of the efficiency is the susceptance, which is a function

of the outphasing angle. If we add a shunt susceptance with the opposite sign to the existent

susceptance at a particular outphasing angle, we can cancel the susceptance and therefore

obtain a maximum efficiency at that outphasing angle. Additionally, as a function of the

outphasing angle, the susceptanceBois symmetrical around = 45(Figure 2.7). Due to this

property, if we compensate the susceptance at a particular outphasing angle comp(0


24/105


14

( ) ( )

2 2

2

2 22

cos( )( )

2sin

2sin sin 2 sin 2

oB B

o o comp

B

comp

G

G B BY

= =+

=

+

(Equation 2.21)

The output RF power remains the same as that in (Equation 2.14 because the added

compensating reactance or susceptance is lossless.

Figure 2.9: Normalized efficiency of the Chireixs outphasing system

at three compensation angles (comp=10o, 20o, and 45o)

Figure 2.10: Normalized efficiency versus normalized output power at

three compensation angles (comp=10o, 20o, and 45o)


25/105


15

Apparently, a zero compensation angle (comp=0o) corresponds to the case without load

compensation ( =B*sin). The normalized theoretical efficiencies for three different

compensation angles (comp =10o, 20o, and 45o) of the Chireixs outphasing amplifier are

plotted in Figure 2.9. As can be seen from these curves, the choice of compensation angle

significantly influences the overall efficiency of the Chireixs outphasing amplifier over the

whole outphasing angle range. If the compensation angle is too small, due to the long

distance between the two efficiency peaks, the overall efficiency in the higher range of the

outphasing angle is very high but the overall efficiency at the lower range of the outphasing

angle will be rather low despite one of the efficiency peaks achieved at the compensation

angle. If the compensation angle is too large, the efficiency peaks move very close to each

other, and except the middle range of the outphasing angle both the efficiency for the lower

range and for the higher range of the outphasing angle drop quickly from the peak value,

especially in the lower range. Only when we choose a proper compensation angle can we

achieve the optimum overall efficiency of the Chireixs outphasing amplifier. Nevertheless,

theoretically, a combination of Chireixs outphasing operation and load compensation makes

it possible to realize very high efficiency over a wide range of the outphasing angle, which

corresponds to a wide range of output power back-off (Figure 2.10). This is exactly the main

advantage of the Chireixs outphasing operation as an efficiency enhancement technique.

2.2 A practical common-mode topology of Chireix's outphasingsystem

The Chireixs outphasing amplifier with a differential-topology power combiner canachieve very high overall efficiency by using proper load compensation. A power combiner

with such a topology, however, is less practical since the amplifier loadthe antennawill

have a ground connection. Consequently, for practical implementations of the Chireixs

outphasing amplifier, a common-mode power combiner realized by quarter-wavelength

transmission lines is usually adopted, which is illustrated in Figure 2.11.

Figure 2.11: A practical Chireixs outphasing amplifier with a common-mode power combiner


26/105


16

For this topology, we will show that it can perform an equivalent function as that of the

differential topology. Except the topology of the power combiner, other assumptions remain

the same as those in Section 2.1.2. Under these conditions, we will derive the theoretical

efficiency of this Chireixs outphasing amplifier in the following section.

Figure 2.12: Schematic of the output part of the practical Chireixs outphasing amplifier

(without load compensation)

Without load compensation, the schematic of the output part of this Chireixs outphasing

amplifier is shown in Figure 2.12. First, the load admittance presented to each outphasing PA

is obtained by using the transmission matrix of the lossless quarter wavelength line. Then,

based on the varying admittance, the theoretical efficiency is derived.

The transmission matrix of a lossless transmission line having a characteristic impedanceZ0and an electrical length is

0

0

cos sin

sincos

jZA B

jC D

Z

=

(Equation 2.22)

For a quarter-wavelength line (=90o) having a characteristic impedance Z0, its

transmission matrix is

0

4 0

0

0

jZA Bj

C DZ

=

(Equation 2.23)

Then we have the input-output relations of the quarter-wavelength lines in the two

branches:


27/105


17

0 0

0 0

andjZ jZ

j j

Z Z

= =

= =

1 o1 2 o2

1 L 2 L

V I V I

I V I V (Equation 2.24)

The voltage sources remain the same as in (Equation 2.8, thus

0 0 0

0

2

0

2

0 0

( ) 2 cos

2 cos

2 cos 2 cos= where

j j

L L

L L

L L

e e

jZ jZ jZ

R RjZ

j ZR R

Z Z R R

+ + +

= + = = =

= =

= = = =

1 2 o oL o1 o2

oL L

o o1 2 L

V V V VI I I

VV I

V VI I V

(Equation 2.25)

Therefore, the load admittances presented to the PAs are

2

2*

2

2 cos

2cos sin 2

2 cos

2cos sin 2( )

2cos sin 2where and

Lo oj

L L

Lo oj

L L

o o

L L

Rj G jB

e R R

Rj G jB

e R R

G BR R

o

11

1 o

o

22 1

2 o

V

IY

V V

V

IY Y

V V

+

= = = =

= = = + = + =

= =

(Equation 2.26)which are illustrated in Figure 2.13.

Figure 2.13: Load admittances presented to each PA in the practical Chireixs outphasing amplifier;

(a) upper branch (b) lower branch


28/105


18

According to (Equation 2.17, the efficiency of this Chireixs outphasing amplifier

without load compensation is given by (Equation 2.27. The efficiency as a function of the

outphasing angle is plotted in Figure 2.13(a).

2

2 2 22 2

2cos

cos( )2cos sin 2

( ) ( )

cos

o LB B B

o o

L L

B

G R

G B

R R

= = =

++

=

Y

(Equation 2.27)

Recall (Equation 2.14, the output RF power of the amplifier is given by

22 22 cosdc

RF dc oL

VP V G

R= =

(Equation 2.28)

The efficiency versus the normalized output RF power is plotted in Figure 2.13(b). This

curve is identical to that in Figure 2.5but now with an inverse dependence on the outphasing

angle, which proves this practical topology is an equivalence of that differential topology

discussed in Section 2.1.2.

(a) (b)

Figure 2.14: Theoretical efficiency of the practical Chireixs outphasing amplifier; (a) Efficiency

versus outphasing angle (b) Efficiency versus normalized output power


29/105


19

Figure 2.15: Load compensation in the practical Chireixs outphasing amplifier;

(a) upper branch (b) lower branch

The load compensation in the practical Chireixs outphasing amplifier is shown in Figure

2.15. After the load compensation components being added into the branches, the load

admittances presented to each PA in the practical Chireixs outphasing amplifier are

2

2*

sin 2 sin 22cos( ) ( )

sin 2 sin 22cos( ) ( ) ( )

sin2where

comp

comp o o comp

L L

comp

comp o o comp

L L

comp

comp

L

j B G j B B jR R

j B G j B B jR R

BR

1 1

2 2 1

Y Y

Y Y Y

= + + = =

= + = + = + =

=

(Equation 2.29)Also according to (Equation 2.17, the theoretical efficiency of the practical Chireixs

outphasing amplifier with load compensation is given by

( ) ( )

2 2

2

2 22

cos( )( )

2cos

2cos sin 2 sin 2

oB B

o o comp

B

comp

G

G B BY

= =

+

=

+

(Equation 2.30)

The output RF power remains the same as that in (Equation 2.28 because the added

compensating reactance or susceptance is lossless. The normalized efficiency for three

different compensation angles (comp=10o, 20o, and 45o) of the Chireixs outphasing amplifier

is plotted in Figure 2.16. Note the opposite phase dependency with respect to the earlier

found results (Figure 2.9) The normalized efficiency can also be plotted as a function of the


30/105


20

normalized output RF power, which is illustrated in Figure 2.17.

Figure 2.16: Normalized efficiency versus outphasing angle of the practical Chireixs outphasing

amplifier at three compensation angles (comp=10o, 20o, and 45o)

As shown in Figure 2.17, the dependence of the efficiency on the output power back-off

is identical to that of the differential topology depicted in Figure 2.10. This is additional

evidence that the common-mode topology is the equivalent of the differential topology for

the Chireixs outphasing operation. Because of the indispensable ground connection needed

by the load antenna, the common-mode topology is chosen for the practical implementation

of the Chireixs outphasing amplifier.

Figure 2.17: Normalized efficiency versus normalized output power of the practical Chireixsoutphasing amplifier at three compensation angles (comp=10o, 20o, and 45o)

As mentioned before, the topology of the power combiner determines how the SCS

should be realized. For a common-mode topology of power combiner, the Chireixs

outphasing system needs a different realization of the SCS from that of the differential

topology. For the original input signal


31/105


21

t ( )exp{ ( )}; 0 ( ) mV t j t V t V inV ( ) =

The SCS for the common-mode topology should convert it into two PM signal

components in the following forms:

t exp{ [ ( ) ( )]}2

t exp{ [ ( ) ( )]}2

( )where ( ) arccos[ ]

m

m

m

V j t t

Vj t t

V tt

V

in1

in2

V ( )

V ( )

= +

=

=

(Equation 2.31)

Assuming the voltage gain of the PA isAv, the amplified signals at the output of the PAs

are:

exp[ ( )] exp{ [ ( ) ( )]}2

exp[ ( )] exp{ [ ( ) ( )]}2

where exp[ ( )]2

mv

mv

mv

Vj t A j t t

Vj t A j t t

VA j t

1 o

2 o

o

V (t) V

V (t) V

V

= + = +

= =

=

(Equation 2.32)

According to (Equation 2.25, the output voltage at the load is

0 0

0

( )2 exp[ ( )]

2 cos[ ( )] 2

t

t exp[ ]2

mv

m

L L

Lv

V V tA j t

t V

R RjZ jZ

RA j

Z

= =

=

o

L

in

V

V ( )

V ( )

(Equation 2.33)

Which is a full recovery of the original input signal, except that a phase shift of 90

degrees is introduced which is caused by the quarter-wavelength transmission line. The

phasor representation of the Chireixs outphasing operation for the common-mode topology

is illustrated in Figure 2.18.


32/105


22

Figure 2.18: A complex phasor representation of the Chireixs outphasing operation

for the common-mode topology power combiner

2.3 A summary of Chireixs outphasing operation

In this chapter, based on a few assumptions, the principle of the Chireixs outphasing

operation is formulated for the case of a direct differential-topology power combiner as well

as for a practical common-mode topology power combiner. Table 2.1presents a comparisonof Chireixs outphasing operation between these two cases. While there are some differences

in the expressions, the underlying principle is identical for these two cases. Finally, the

normalized theoretical efficiency of the Chireixs outphasing amplifier versus the normalized

output RF power at four different outphasing angles0o, 10o, 20o, and 45ois plotted in

Figure 2.19, which is applicable to both the differential and common-mode topology. As can

be seen from this figure, a proper selection of the load compensation can significantly

enhance the efficiency of the Chireixs outphasing amplifier over a considerable range of the

output RF power back-off. The next chapter will describe a practical implementation of the

Chireixs outphasing amplifier based on the common-mode topology with load compensation.

Figure 2.19: Theoretical efficiency of the Chireixs outphasing system at

four different compensation angles (0o, 10

o, 20

o, and 45

o)

( )j te

tin2V ( )

tin1V ( )

tinV ( ) ( )t

( )t


33/105


23

Table 2.1: A comparison of the Chireixs outphasing operation between a differential topology

power combiner and a common-mode topology power combiner

Differential topology Common-mode topology

Input signal

tinV ( ) ( )exp{ ( )}; 0 ( ) mV t j t V t V

component signals

tin1,2V ( )

exp{ [ ( ) ( )]}2 2

( )where ( ) arcsin[ ]

m

m

Vj t t

V tt

V

=

exp{ [ ( ) ( )]}2

( )where ( ) arccos[ ]

m

m

Vj t t

V tt

V

=

Load voltage

tLV ( )

2 sin

tv

j

A

= =

=

L 1 2 o

in

V V V V

V ( )

0 0

0

2 cos

t exp[ ]2

L L

Lv

R RjZ jZ

RA j

Z

+= =

=

1 2 oL

in

V V VV

V ( )

Load admittances

Y

2 sin 2 sin 22sin comp

L L

jR R

1,2Y

= 2 sin 2 sin 22cos comp

L L

jR R

1,2Y

=

2 Re{ }RF dcP V = Y RF power

RFP

22 2sin

dc

L

VR

2 22 02cos wheredc L

L L

ZV R

R R

=

( ) cos( )B = Y Efficiency

( ) ( ) ( )

2

2 22

2sin

2sin sin 2 sin 2B

comp

+

( ) ( )

2

2 22

2cos

2cos sin 2 sin 2B

comp

+


34/105


24


35/105

Chapter 3. Design of a Chireixs/LINC amplifier

25

Chapter 3

Design of a Chireix's/LINC amplifier

3.1 Design strategies and procedure

As discussed in Chapter 2, a Chireixs/LINC amplifier consists of three partsthe SCS,

the PAs, and the power combiner, and they respectively accomplish signal component

separation, signal amplification, and amplified signal component recombination in the

Chireixs outphasing operation. Such outphasing amplifier architecture allows for the use of

nonlinear PAs driven by constant envelope signals, which can lead to dramatically higher

efficiency than linear amplifier operation. These nonlinear PAs exhibit very high efficiency

but they dont affect the final distortion levels at the system output because they operate at

constant envelope signals. The major factors contributing to the linearity degradation include

the SCS, realized either by an analog method or by a digital method, and the path imbalance

between the two PA branches. Having an influence both on the efficiency and on the linearity,

the power combiner is a place where the efficiency-linearity tradeoff needs to be dealt with.

As an AM-PM converter, the SCS is conceptually clear, a practical realization of the

SCS, however, is complex and difficult because the generation of the two component signals

involves memoryless nonlinear signal processing that requires a high degree of accuracy.

Various approaches have been proposed to achieve this function, but difficulties remain in

terms of factors, such as implementation complexity, bandwidth, and power consumption,

owing to the stringent distortion and noise requirements. A study of this topic alone for a

operational hardware implementation needs considerable time and effort. Therefore, instead

of striving to realize an analog hardware implemented SCS, we aim for a digital SCS

implementation and focused our efforts on the design and implementation of the PAs and the

power combiner. For this digital SCS implementation we will rely on arbitrary waveform

generators and I/Q (In-phase/Quadrature) up-converting modulators to generate the two

phase modulated RF input signals. Software will be used to implement the AM-PM signal

conversion.

Our final goal is to create an amplifier that provides high efficiency and excellent

linearity simultaneously. It seems natural that we carry out the design of the outphasing

amplifier in two stepsfirst the design of the efficient PA cells and then that of the power


36/105


26

combiner. The first thing in the PA cell design, is to choose a suitable amplifier operation m

ode. Depending on the operation mode that is selected, the power combiner design has to be

adjusted accordingly because different operations need different output terminations from the

power combiner. Consequently, the amplifier mode choice and the power combiner choice

must be made together, which should be done before stepping into the PA cell design and the

power combiner design.

3.2 Amplifier and power combiner choices

Basically there are two kinds of power combiners: isolating power combiners and non-

isolating lossless power combiners. An isolating power combiner provides isolation between

its input ports. In a classical LINC system that employs isolating power combiners, the

inherent high linearity of the LINC operation can be preserved, but the considerable power

loss in the combiners results in significant efficiency reduction. By contrast, a non-isolating

lossless power combiner in the PA output yields significant interaction between the

amplifiers, which leads to AM-AM and AM-PM distortion, however it provides a much

better efficiency. Therefore, both types of power combiners have advantages and

disadvantages when applied in a LINC system.

For an outphasing system implemented with an isolating power combiner, the amplifier

mode choice is relatively unrestricted because the isolated inputs of the matched combiner

provide fixed output terminations at the output of the PAs. For a system using a non-isolating

lossless power combiner, however, the output interactions must be carefully designedbecause the overall output impedance of each component PA is established by the outputs of

both PAs. If the PAs act as voltage sources, the overall impedance presented to the amplifier

by the power combiner must not be zero for any possible phase difference between the two

PAs. In contrast, for the PAs acting as current sources, the overall admittance must not be

zero.

In a Chireixs outphasing system, as discussed in the previous chapter, the Chireixs

power combining technique employs a three-port, non-isolating lossless power combiner

implemented by two quarter-wavelength transmission lines. This non-isolating Chireixs

combiner introduces significant interaction between the two PAs, which generates time-

varying loads that are presented to the output of each PA. The Chireixs outphasing operation

requires the two PAs to resemble a behavior that approximates a voltage source. Relevant

work has shown that saturated class-B, class-F, and voltage-mode class-D PAs have an

output current-voltage relationship that is similar to that of a voltage source. As a result, we


37/105


27

can choose either of them to implement a high-performance Chireixs outphasing amplifier.

In our design, we chose to implement saturated class-B PAs because the practical achievable

efficiency of saturated class-B amplifiers is close to that of class-F amplifiers or voltage-

mode class-D amplifiers while saturated class-B amplifiers are comparatively easy to realize.

3.3 Power amplifier cell design

The design of a class-B PA cell is to find the conditions under which the given active

device can operate in class-B mode and to realize these conditions also in the circuit. These

conditions include bias points, input conditions, output terminations, and stabilization

conditions. In order to determine these conditions, first we need to know what is a saturated

class-B mode.

The power amplifiers are loosely divided into two categories based on how the active

device behaves. One is the linear (or transconductance mode) PAs and the other is

nonlinear (or switch mode) PAs. Depending on the conduction angle, defined as the part of

the RF signal period during which the transistor is carrying current, the linear PAs can be

classified into several classes, such as class-A, class-B, class-AB, and class-C. The

corresponding output current and voltage waveforms are shown in Figure 3.1. Table 3.1lists

the bias point and conduction angle for each corresponding operation mode.

Figure 3.1: Current and voltage waveforms of PA in different classes of operation

In a class-B mode, the gate bias voltage equals the pinch-off voltage, resulting in a

conduction angle of half the RF signal period (), and a halfwave-rectified sinewave for the

drain current. Therefore, the transistor consumes less dc power than class-A and is more


38/105


28

efficient. With all the harmonics shorted, the output voltage across the load only has a

fundamental component and therefore has a perfect sinusoidal waveform. An appropriate

choice of the load can make the amplitude of the output voltage equal to the dc supply

voltage. Based on these assumptions, the theoretical maximum efficiency of class-B

operation is /4(or 78.5%).

Table 3.1: Classical model of operation

Mode Normalized bias

point

Normalized

quiescent current

Conduction angle

class-A 0.5 0.5 2

class-AB 0-0.5 0-0.5 -2

class-B 0 0

class-C


39/105


29

network.

3) Partially compensate the parasitic effects of the device package.4) Determine the input conditions and the optimum load impedance by load-pull

simulation

5) Use ideal components to verify the functionality of the PA cell.6) Implement the PA cell by using realistic components.

3.3.1 Device characterization and bias points

Various power amplifier technologies are competing for market share like Si-LDMOS

(Lateral-diffused MOS), bipolar transistors, GaAs MESFETs (Metal Epitaxial Semiconductor

FET), GaAs (or GaAs/InGaP) HBTs (Hetero-junction Bipolar Transistors), SiC MESFETs,

and GaN HEMTs. The properties of GaN HEMT compared to the competing technologies is

shown in Table 3.2.

Table 3.2: Attributes of various power amplifier technologies

Attribute Si GaAs SiC GaN

Energy Gap (eV) 1.11 1.43 3.2 3.4

Breakdown E-Field (V/cm) 6.0105 6.5105 3.5106 3.5106

Saturation Velocity (cm/s) 1.0107 2.0107 2.0107 2.5107

Electron Mobility (cm2/Vs) 1350 6000 800 1600

Thermal Conductivity (W/cmK) 1.5 0.46 3.5 1.7

Maximum Temperature (C) 300 300 600 700

JFOM 1.0 3.5 60 80BFOM 1.0 9.6 3.1 24.6

The GaN material has much better BFOM (Baligas figure of merit for power transistor

performance) and JFOM (Johnsons figure of merit for power transistors performance) than

its competitors. This outstanding performance is attributed to the following advantages it has:

1. The room temperature energy gap of 3.4 eV enables GaN devices to support internalelectric fields about five times higher than Si or GaAs, which means GaN has a higher

breakdown voltage, a desirable attribute of power devices.

2. As a member of HEMT family, the GaN device also inherits the feature of HEMThigh electron mobility. In the RF/Microwave domain, high electron speeds are

required to minimize internal device delays.

3. Benefiting from the excellent thermal conductivity of its SiC substrate, the GaN


40/105


30

HEMT is very suitable for high power devices with reduced cooling requirements.

Therefore, we employ GaN HEMT as the active device in our PA cell design.

(a) (b)Figure 3.2: GaN HEMT large signal models; (a) package model CGH40045F

(b) bare die model CGH40060D

(a) (b)Figure 3.3: The circuit model for package parasitics and the bare die model;

(a) package parasitics and bare die model (b) a simplified symbol for both

The active device used in the PA cell is the 45 watt GaN HEMT delivered by Cree. Two

sets of large signal models CGH40045F and CGH40060D (Figure 3.2) have been provided

for this device. CGH40045F is the large signal model of the whole device package, which

models both the die transistor and the package parasitics, whereas CGH40060D is the large

signal model for the bare die transistor alone, along with which a circuit model for the

package parasitics has also been provided (Figure 3.3).

Using the DC simulation in ADS, we can check the DC characteristics of the package

model CGH40045F. The ID-VGS and the ID-VDS relationships are plotted respectively in

Figure 3.4and Figure 3.5.


41/105


31

Figure 3.4: IDversus VGS(VDS=28V)

Figure 3.5: IDversus VDS(VGS=-3.0V::0.5V::1V)

As can be seen from these figures, the DC characteristics of the GaN device are listed in

the following table.

Table 3.3: DC characteristics of Cree GaN HEMT CGH40045F

Device DC characteristics Typical Value Conditions

Pinch-off voltage -2.9V VDS= 28V

Drain-Source breakdown 120V VGS= -3V~1V

Transconductance 4000mS VDS= 28V, ID=6A

Saturated drain current 12.5A VDS= 28V

For a class-B operation, the gate bias voltage should be set at the pinch-off point. The

valid drain voltage for this device is from 28V to 48V. We chose the lowest one as the drain

bias voltage so that the device would stay in the saturation during most of the half RF signal

period even when the input power backs off. In such a way, the device can better


42/105


32

approximate an ideal voltage source. As a result, the bias points for the active device are:

2.9V and 28VG DV V= =

3.3.2 Device stabilizationStability is of great importance for an amplifier because all the design goals, such as

efficiency and gain, will be lost once oscillation occurs. Therefore, it is essential to check and

ensure the stability of the active device before starting the PA cell design. Here we used the

single parameter criterion to judge the stability of the device. The criterion is actually an

analysis of the small signal S-parameters of the device. For small signal S-parameter

simulation, the device should be biased at the linear class-A operation. The schematic used

to check the devices stability and the simulation result are shown in Figure 3.6.

(a)

(b)

Figure 3.6: Device stability checking; (a) circuit schematic (b) simulation result

The design frequency for our Chireixs outphasing amplifier is 2.14 GHz. Apparently,

this device is not unconditionally stable around the design frequency and it is necessary to

make the device stable. Because the load of the outphasing amplifier is modulated by the


43/105


33

outphasing angle, the load impedance varies as the envelope of the original AM signal alters.

Furthermore, under extreme circumstances the antenna may be even short-circuited or

become open-circuit, which may lead to unexpected load impedance presented to the output

of the amplifiers. Therefore, to avoid disastrous consequences the safest way to handle the

stability problem is making the device unconditionally stable over the whole smith chart by

introducing into the circuit a proper stabilization network. Earlier a stabilization network was

developed by Mr. Marco Pelk to stabilize the same kind of device in another amplifier design.

We also used this stabilization network (Figure 3.7) in our Chireixs outphasing amplifier

design. The schematic and simulation result in Figure 3.8show the stabilization effect of this

network.

Figure 3.7: Input stabilization network and its simplified symbol

Courtesy of Marco Pelk

(a)


44/105


34

(b)

Figure 3.8: Stabilization effect of the stabilization network;

(a) circuit schematic (b) simulation result

3.3.3 Partially compensating the parasitic effects of the package

As can be seen from Figure 3.3(a), in the circuit model of the package parasitic effects,

there are a -type network and a short transmission line at the drain of the die model. The -

type network also acts like a very short transmission line. Therefore, the overall effect of the

-type network and the short transmission line can be approximated by a parasitic

transmission line, which transforms the load impedance presented to it (the fundamental as

well as the harmonic ones). Such a parasitic impedance transformer impairs the Chireixs

outphasing operation. This impedance transformation effect can be partially compensated by

adding a proper transmission line, as shown in Figure 3.9. The principle of this compensation

is to make the total electrical length of the added transmission line and the parasitic

transmission line roughly equal to or 180 degrees for the fundamental impedance so that

the total phase shift of the impedance produced by these two transmission lines is

approximately 2or 360 degrees, i.e. on the Smith chart the impedance is rotated a circle and

back to the original point. Ideally, with a complete compensation, the impedance seen by port

1 would be exactly the same asRin. Note that only a small shift in the real part is remaining

after the insertion of the line which realizes a partial compensation. We will include this line

in our subsequent load-pull simulations.

Because the compensation is carried out for the fundamental impedance, it is only validfor the fundamental impedance, generally not valid for the higher harmonic impedance

because the -type network is not a transmission line after all. For a special casethe even

harmonic short, especially for the second harmonic short, however, it remains valid enough.

The parasitics compensation effect for the second harmonic short can be seen from Marker 2

in Figure 3.9(b). As can be seen from this simulation result, providing even harmonic shorts

after the compensating transmission line is approximately equivalent to providing them at the


45/105


35

internal drain of the bare die inside the package.

(a)

(b)

Figure 3.9: Partial compensation of the package parasitics

(a) circuit schematic (b) simulation results

3.3.4 Load-pulldetermining the optimum load impedance

As discussed before, both the input conditions and the output terminations influence the

efficiency. To maximally transfer power from the source to the active device, an input

conjugate match is needed. To achieve excellent efficiency, a proper input drive level and

optimum fundamental impedance are needed besides suitable harmonic terminations.

The input impedance for the input match can be determined by a large signal S-


46/105


36

parameter simulation. Then, based on this input impedance, an input matching network can

be implemented. A rough value of the required source power can be estimated by the rated

power and gain of the active device. The rated power of the GaN HEMT we use is 45 watts,

which means that the maximum output power realizable in practice for this device is 45 watts.

Experience from previous work shows that the 45 watt GaN HEMT has a gain about 10 dB.

Therefore, a suitable input power level is approximately 4.5 watt or 36.5 dBm. In a load-pull

simulation, the fundamental load impedance in a certain region of the Smith chart is swept so

that the optimum termination for the maximum efficiency with the maximum practically

realizable output power (45W or 46.5dBm) is found. A rough estimate of the optimum real

part of the load impedance can be made according to the following loadline equation:

max

284.5

/ 2 12.5 / 2dc

opt

VR

I= = = (Equation 3.1)

which can be used as a starting point of the load-pull simulation. During the whole

process of the load-pull simulation, the following steps are carried out:

1) At the input, a 36 dBm power source at 2.14 GHz is provided as the excitation. Thesource impedance is set at 50 ohm for all the frequency components. At the output, even

harmonic shorting is realized by an SCSS (Short-Circuit Shunt Stub); the load impedance

is set at 50 ohm for the higher harmonics and the fundamental load impedance is 50 ohm

by default before the load-pull simulation

2) A large signal S-parameter simulation is performed to determine the input impedance.The fundamental component of the source impedance is then set at the conjugate of the

obtained input impedance to realize an input conjugate match.

3) Perform the load-pull simulation to determine the optimum load impedance under presentconditions.

4) Set the fundamental component of the load at the optimum load impedance just obtained.Because of the change of the load, the input impedance also changes, which leads to aslight mismatch at the input. Redo the input match as in step 2 to achieve a new input

match.

5) With the new input match, perform the load-pull again to obtain a slightly more accuratevalue of the optimum load impedance. Because the change of the optimum impedance is


47/105


37

slight, it has little influence on the new input match. Consequently, we can accept this

input match and obtain a better value of the optimum impedance as well.

(a)

(b)

Figure 3.10: Load-pull simulation; (a) schematic (b) simulation result

The circuit schematic and the simulation results are shown in Figure 3.10. In this

schematic, the microstrip line used for package parasitics compensation has been converted

into an ideal transmission line (TLcomp) by using the LineCalc in ADS.

Table 3.4: Results of the load-pull simulation and the corresponding conditions

Performance Conditions

Output Power 46.8 dBm Input power 36 dBm

Efficiency 78.4% Source impedance 50*(0.031-j*0.127) ohm

PAE 71.7% Optimum load admittance 0.069-j*0.103 S


48/105


38

From the above load-pull simulation, we have determined the input impedance for the

input match and the optimum admittance for the maximum efficiency at the maximum output

power (Table 3.4). Note that, because power contour and efficiency contour normally have

different centers, actually such a load is neither optimum only for the efficiency nor for theoutput power alone, but is a compromise between high output power and high efficiency. If

we choose the load for the maximum output power (48.76 dBm, about 75W), the efficiency

will be much lower than 78.5%, the theoretical efficiency of class-B PA. If we choose the

load for the maximum efficiency (84.87%), the output power will be much lower than the

output power rating of the GaN HEMT (45W or 46.5 dBm). Neither of these two results are

desirable for the transmitter in the base station applications. The optimum load we choose is

such that the efficiency can be as high as possible while the output power remains slightly

above the output power rating, 45 watts. Such a load can be regarded as an optimum one for

the maximum efficiency with an output power at the output power rating of the device. In the

final Chireix implementation the load will be a varying function of the outphasing angle.

However, the data obtained will help us to achieve the peak power conditions for the

amplifier to be completed.

For this load-pull simulation, one thing needs to explain is the location of the SCSS. As

mentioned in Section 3.3.3, the package parasitics compensation is valid enough for even

harmonic short, and therefore point B in Figure 3.10(a) is equivalent to the internal drain of

the bare die for providing even harmonic short. It is natural that we should put the SCSS at

point B to provide nearly perfect even harmonic short for the internal drain. In our load-pull

circuit, however, the SCSS was located at point A. The reason is that what the internal drain

needs for obtaining maximum efficiency is not a perfect second harmonic short but a second

harmonic impedance that is a little bit inductive (a possible explanation for this is that the

active device is not an ideal device but a device with inherent parasitics such as parasitic

capacitance). It is purely coincident that an SCSS at point A, along with the package

parasitics, can provide such a somewhat inductive impedance for the second harmonic. As a

result, providing even harmonic shorts at point B or at the internal drain produces rather

lower efficiency than at point A. By contrast, the load-pull simulation and results in the caseof providing even harmonic shorts at the internal drain are shown in Figure 3.11.


49/105


39

(a)

(b)

Figure 3.11: Load-pull simulation with even harmonic shorts at the internal drain;

(a) schematic (b) simulation result

In addition, a load-pull simulation aiming for the optimization of the second harmonic

short was also performed. With the optimized second harmonic short, the efficiency can be

further increased by 2 in percentage, but the price is a drop of the output power. Because the

improvement of the efficiency is not significant, we choose not to optimize the second

harmonic short. In the following design, we will use the results in Table 3.4to realize the PA

cell.

3.3.5 Functionality verification with ideal components

In this section, the implementation of the class-B PA cell by using ideal components will

be described. In order to implement the PA cell, three conditions need to be realized. Theyare the input match, the even-harmonic shorting, and the output loadline match.


50/105


40

(a) (b)

Figure 3.12: Input matching network realized with ideal transmission lines;


Figure 3.13: Output matching network realized with ideal transmission lines;


An input matching network can be realized by using lumped elements or ideal

transmission lines to transform the input impedance to the 50 ohm source impedance. The

input matching network realized by ideal transmission lines is shown in Figure 3.12. The

output matching network can be realized in the same way. Figure 3.13presents the design of

the output matching network. The even-harmonic shorting can be realized by a SCSS. The

PA cell realized with ideal components is shown in Figure 3.14. As can be seen from the

simulation results, the efficiency and the output RF power are very close to the values

obtained from the load-pull simulation.


51/105


41

(a)

(b)Figure 3.14: class-B PA cell realized with ideal components;


3.3.6 Implementation with realistic components

While simulation with ideal components can show maximum attainable performance,

what we really need is a circuit fabricated with realistic components. The input matching

network and the output matching network realized with ideal transmission lines can be

transformed into practical realizations of microstrip lines by using the LineCalc tool in ADS,

so is the SCSS that performs the even harmonic shorting. The input matching network

realized with practical microstrip lines and 0603 SMCs (Surface Mounted Components) is

illustrated in Figure 3.15and the output matching network in Figure 3.16while Figure 3.19

shows the final class-B PA cell realized with realistic components.

(a) (b)(b)

Figure 3.15: Input matching network realized with SMD capacitor and microstrip lines;



52/105


42

(a) (b)

Figure 3.16: Output matching network realized with SMD capacitor and microstrip lines;


SMCs are the components used in Surface Mount Technology (SMT). In SMT, SMCs

are mounted directly onto the surface of printed circuit boards (PCBs) to construct electronic

circuits. Electronic devices so made are called surface-mount devices or SMDs. In the

industry SMT has largely replaced the through-hole technology construction method of

fitting components with wire leads into holes in the circuit board. SMCs are usually smaller

than their counterparts with leads, such as through-hole components, because they have either

smaller leads or no leads at all. They may have short pins or leads of various styles, flat

contacts, a matrix of solder balls, or terminations on the body of the component. SMCs are

designed to be handled by machines rather than by humans. The electronics industry has

standardized package shapes and sizes. For example, the two-terminal packages of

rectangular passive components (mostly resistors and capacitors) are listed in Table 3.5.

Table 3.5: Sizes of two-terminal packages of rectangular passive components

(mostly resistors and capacitors)

Type Size Typical power rating

for resistors

01005 (0402 metric) 0.016" 0.008" (0.4 mm 0.2 mm) 1/32 Watt

0201 (0603 metric) 0.024" 0.012" (0.6 mm 0.3 mm) 1/20 Watt

0402 (1005 metric) 0.04" 0.02" (1.0 mm 0.5 mm) 1/16 Watt

0603 (1608 metric) 0.063" 0.031" (1.6 mm 0.8 mm) 1/16 Watt

0805 (2012 metric) 0.08" 0.05" (2.0 mm 1.25 mm) 1/10 or 1/8 Watt

1206 (3216 metric) 0.126" 0.063" (3.2 mm 1.6 mm) 1/4 Watt

1806 (4516 metric) 0.177" 0.063" (4.5 mm 1.6 mm)1812 (4532 metric) 0.18" 0.12" (4.5 mm 3.2 mm) 1/2 Watt

2010 (5025 metric) 0.2" 0.1" (5.0 mm 2.5 mm)

2512 (6332 metric) 0.25" 0.12" (6.35 mm 3.0 mm)

In our design, we use 0603 SMD components. The parasitics of the 0603 SMD

capacitors are:


53/105


43

Series resistance: 0.4 Ohm Series inductance: 0.75 nH

The parasitics of the 0603 SMD resistors are:

Series inductance: 0.8 nHThe 0603 SMD pad parasitics are shown in Figure 3.17and Figure 3.18.

(a) (b)Figure 3.17: 0603 SMD two-capacitor component and its simplified symbol;

(a) pad parasitics and capacitors (b) simplified symbol

(a) (b)

Figure 3.18: 0603 SMD three-capacitor component and its simplified symbol;

(a) pad parasitics and capacitors (b) simplified symbol


54/105


44

(a)

(b)

Figure 3.19: Class-B PA cell realized with realistic components;

(a) circuit schematic (b) simulation performance

3.4 Chireix's outphasing system design

Based on high efficiency PA cells, a Chireixs outphasing system can be implemented by

connecting them with an appropriate power combiner. This section describes the procedure

of Chireixs outphasing system design. First the design of the Chireixs power combiner is

discussed in detail and special consideration for the bandwidth has been given to the design

of the power combiner. Then two branches of PA are combined together to constitute a

Chireixs outphasing system. The implementation of the Chireixs outphasing system is

performed in three steps. First, ideal voltage sources and ideal components are used to verify

the concept of Chireixs outphasing operation. Also, ideal voltage sources are replaced by

power sources with source impedance to check the influence of the source impedance on the

outphasing operation. Next, actual active device and ideal components are used to realize the

outphasing system. Finally, all ideal components are replaced by practical components to

finish the implementation of a practical Chireixs outphasing system.

3.4.1 Power combiner design

The Chireixs power combining technique employs the three-port, non-isolating lossless

power combiner implemented by two quarter-wavelength transmission lines complemented

with Chireixs complex load compensation for a particular compensation angle. When the


55/105


45

outphasing angle is equal to the compensation angle, the efficiency of the total Chireix

amplifier should peak. In order to make this efficiency peaking also happen in practice, the

impedance offered to the internal device (excluding any parasitics) should be real, this

requires that all reactive device elements (e.g. output capacitance) and the susceptance due to

outphasing effect must be compensated at these angles.

compensation

DSC optB

optG

LR

0,4

Z

B r a n c h 1

B r a n c h 2

Figure 3.20: A simplified circuit schematic for one branch of the Chireixs outphasing system

at zero outphasing angle without load compensation

According to the principle of Chireixs outphasing operation discussed in Chapter 3,

before compensating the susceptance due to outphasing effect, the efficiency of the

outphasing system peaks at zero outphasing angle because the active device is presented

with just a real conductance at this outphasing angle. In order to make this peak efficiency

equal to the PAs maximum efficiency obtained from the load-pull simulation, the active

device should be presented with the optimum admittance (Yopt= Gopt+j*Bopt) determined in

the load-pull simulation. This can be realized by making the conductance due to outphasing

effect equal to the optimum conductance (Gopt) and compensating the output capacitance

with the optimum susceptance (Bopt). The simplified schematic for the circuit at zero

outphasing angle without load compensation is shown in Figure 3.20.

The characteristic impedance of the quarter wavelength line can be determined by the

equal relationship between the conductance due to outphasing effect and the optimum

conductance. Such an equal relationship at zero outphasing angle requires:


56/105


46

2

1 0 0

2

0

0

2cos 2| i.e. |

2

2 2 50 Z 38.1 Ohm

0.069

opt opt

L L

L

opt L

L

opt

G G GR R

ZR

G R

R

G

= =

= = =

= =

= = =

(Equation 3.2)

The resulting power combiner is shown in the simplified circuit schematic illustrated in

Figure 3.21.

compensation

D SC o ptB

o p tG

5 0 O h mL

R =

B r a n c h 1

compensation

D SC o ptB

o p tG

0, 3 8 .1 O h m4

Z

=

B r a n ch 2

0, 3 8 .1 O hm4

Z

=

Figure 3.21: A simplified schematic of the Chireixs outphasing system without load compensation

In this power combiner, the impedance transformation from 50 ohm load to the optimum

conductance in each branch is realized by only one stage of matching networkone quarter

wavelength line. There are various solutions to such a matching problem. The above solution

is the most direct and simplest one, but it is not a wide-band matching network and has a

limited bandwidth. Theoretically, wide-band matching networks can be realized by cascading

multiple stages (the trajectory of each stage on the Smith chart confined in the lowest Q

contour). Too many stages, however, require more components and produce a more complex

matching network. Here, we made a compromise between the bandwidth and the simplicity

of the matching network. We realized this match by inserting another quarter wavelength line,

i.e. by cascading two stages of transmission lines in the matching network. Figure 3.22

presents a simplified schematic of this two-stage power combiner.


57/105


47

compensation

DSC optB

optG B r a n c h 1

compensation

DSC optB

optG

B r a n c h 2

0, 23.5 Ohm4

Z

=

0, 30.9 Ohm4

Z =

0, 23.5 Ohm4

Z

=

50 OhmLR =

Figure 3.22: A simplified schematic of the Chireixs outphasing system without load compensation

with a two-stage power combiner

(a)

(b)

Figure 3.23 Bandwidth of the single-stage power combiner;



58/105


48

For this two-stage power combiner, we have optimized its 3 dB bandwidth by tuning

the characteristic impedance of each quarter wavelength line in ADS. Alternatively, we can

also make the power transfer of the power combiner a Butterworth type by calculation to

obtain an optimum bandwidth. Compared to the simple single-stage realization, the

bandwidth has been significantly improved in the two-stage power combiner. Circuit

schematic and bandwidth simulation results of the single-stage power combiner and those of

the two-stage power combiner are shown respectively in Figure 3.23and Figure 3.24.

(a)

(b)

Figure 3.24: Bandwidth of the two-stage power combiner;(a) circuit schematic (b) simulation result

3.4.2 Chireixs outphasing system without load compensation

With the power combiner, two branches of PAs can be linked together to construct a

Chireixs outphasing system. Before we use the real active device to build the PAs, ideal

voltage sources and ideal components are used to verify the functionality of the outphasing


59/105


49

operation. The circuit schematic and simulation results are shown in Figure 3.25. In order to

model the maximum output power of the GaN HEMT (45 watts), the voltage of the ideal

voltage source is set at 36.1 volts, which can produce 45 watt output power at the optimum

conductance (Gopt = 0.069) in each branch. From the theoretical derivation for Chireixs

outphasing operation in Chapter 2, recalling (Equation 2.26, (Equation 2.27, and (Equation

2.28, we have:

222cos sin 2

cos sin 22

opt

opt

L L

Gj G j

R R1,2Y

= =

cosB = 2

2 2 22 cos cosdcRF opt dcL

VP G V

R = =

The simulation results of the admittance, output power, and the normalized efficiency shown

in Figure 3.25(b) agree with these theoretical predictions pretty well. Note that Vdc here

represents the amplitude of the ideal voltage source, i.e. 36.1 volts. The reason that it differs

from the dc supply voltage (28 volts) is that the PA we have designed is not a perfect class-B

mode. For a perfect class-B operation mode, all the higher harmonics should be shorted. In

our PA operation, we have only provided even harmonic shorts and left the odd harmonic

uncontrolled.

(a) Circuit schematic

(b) Admittance in each branch


60/105


50

(c) Output power and normalized efficiency

Figure 3.25: Ideal outphasing operation without load compensation;

(a) circuit schematic (b), (c) simulation results

Such a Chireixs outphasing system has been realized with the actual active devices and

ideal components in the schematic shown in Figure 3.26(a). The simulation results are

presented in Figure 3.26(b) and (c).

(a) Circuit schematic


61/105


51

(b) Admittance in each branch

(c) Output power and efficiency

Figure 3.26: Chireixs outphasing system realized with active devices and ideal components

(without load compensation); (a) circuit schematic (b), (c) simulation results

These curves do not well correspond to those simulation results of the outphasing

operation using ideal voltage sources because the actual active devices are, after all, not ideal

voltage sources, although they can be approximated by ideal voltage sources to some extent.

One significant difference between an ideal voltage source and the actual class-B PA is thatthe latter has source impedance. If we replace the ideal voltage sources with power sources

that have source impedance, the resulting simulation results will become similar to the results

of the outphasing system using actual active devices. The outphasing system constructed by

using power sources and ideal components is shown in Figure 3.27(a), and the simulation

results are presented in Figure 3.27(b) and (c).


62/105

Linc Cherix Pa

Documents

Transcript of Linc Cherix Pa