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Transcript of LiderCalidad-Andres
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TSPi Process : Step WHO TOOL INSTRUCTIONS
Before STRAT1 Team Leader Fi ll out the project information on the Project worksheet (Name, Team name,
Project name, Start Date, Instructor, Cycle).
Before STRAT1 Team Leader Enter the team member names, ini tials, phone numbers, e-mai l addresses, andfilenames for the team members workbooks in the Team worksheet.
Before STRAT1 Team Leader Enter the role assignments on the Roles worksheet.
STRAT1: Produce the
Size Estimate
Planning Manager Enter on the SUMS worksheet, the names and size estimates of all assemblies
and parts for this cycle.
PLAN1: Produce the
Task Plan
Planning Manager Click the Generate Task List button to create a default task list.
PLAN1: Produce the
Task Plan
Planning Manager Revise the task list adding or deleting tasks as necessary. Then for each task,
estimate the size where appropriate, the time, and the time for each engineer
assigned to the task.
PLAN1: Produce the
Schedule Plan
Planning Manager Enter hours per week in the Schedule template. Hours per week are based on
the total hours for the team for each week in the schedule.
Planning Manager Click the Update Task and Schedule Plan button on the Task Worksheet to
generate a schedule.
PLAN1: Quality Plan Team Before creating the quality plan, review the quality standard in the textbook.
PLAN1: Quality Plan Quality/Process
Manager
Enter the planned defect injection rates for each phase on the SUMQ worksheet.
PLAN1: Quality Plan Quality/Process
Manager
Enter estimated phase yields for each phase.
PLAN1: Qual ity Plan Team Review the calculated defect removal rates and defect densities (Defects/KLOC)
against the Quality Standard. If necessary, adjust planned time (Task worksheet),
defect injection rates (SUMQ), or defect removal yields (SUMQ).
PLAN: Balance
Workload
Planning Manager Make 1 copy of the team workbook for each engineer. Use the filename entered
on the Team worksheet (Workbook Filename). Click the Make copies... button to
create the copies automatically.
PLAN: Balance
Workload
Each engineer Revise the tasks in the Task worksheet to reflect the individual engineers
workload (e.g. delete task not assigned to you, and where you share an
assignment with other engineers, set their planned hours to zero).
PLAN: Balance
Workload
Each engineer Revise the schedule plan on the Schedule worksheet to reflect your available
hours per week.
PLAN: Balance
Workload
Planning Manager Load the engineers' individual worksheets and the consolidated team plan
workbook into the same folder. Open the consolidated team plan workbook. Click
the consolidate plan button on the Team worksheet to build a consolidated plan
PLAN: Balance
Workload
All team members If necessary, reassign tasks to balance the workload and repeat the previous 3
steps until a balanced plan is achieved. If planned times for any task change,review the quality plan and revise it if necessary.
TSPi Process : Step WHO TOOL INSTRUCTIONS
STRAT, PLAN, REQ,
DES, IMP, TEST, PM
All team members During all TSPi phases, use the time log to record data on each task. Include the
assembly and phase for each task, the date, start time, interrupt time, stop time,
and comments.
REQ, DES, IMP, TEST All team members During TSPi phases REQ, DES, IMP, and TEST, use the defect log to record
data on each defect. Include the date, number, type, assembly, phase injected,
phase removed, fix time, fix reference, and description
Weekly All team members Click the Update Project button on the Project worksheet to update individual
plans. Print the Task and Schedule worksheets.
Weekly All team members Print the Task worksheet.
Weekly All team members Print the Schedule worksheet.
Strate Develo ment and Plannin
Weekl Trackin
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Weekly All team members Prepare a Week report. The worksheet Week includes the planning summary
information required for the week report.
Weekly All team members Send a copy of your workbook to the planning manager for use in preparing the
team's consolidated weekly report.
Weekly Planning Manager Update consolidated team plan with the current week's data and prepare status
reports for the weekly meeting.
Weekly Planning Manager Load the individual engineers workbooks and the consolidated team workbookinto the same folder. Open the consolidated team workbook. Click the
Consolidate Plans button on Team worksheet to update consolidated team plan
with the current week's data.
Weekly Planning Manager Select the Project worksheet and click the update project button before printing
status reports for the weekly meeting.
Weekly Planning Manager Print the Task worksheet.
Weekly Planning Manager Print the Schedule worksheet.
Weekly Planning Manager Prepare a Week report. The worksheet Week includes the planning summary
information required for the week report.
Weekly Planning Manager Select the Project worksheet, select the assembly SYSTEM, then select and print
the following charts:
-Earned Value
-Plan vs. Actual Hours
Weekly duringimplementation and
testing phases
Planning Manager Select the Project worksheet, select the assembly SYSTEM, then select and printthe following charts:
-Defect Removal Profile
-Quality Profile
-Percent Defect Free
TSPi Process : Step WHO TOOL INSTRUCTIONS
PM All team members Follow the weekly tracking instructions to prepare and print copies of the final
task, schedule, and week reports.
PM All team members Select the Project worksheet and click the export button to save a copy of your
data for the cycle.
PM Planning Manager Follow the weekly tracking instructions to prepare and print copies of the final
task, schedule, and week reports.
PM Planning Manager Select the SUMP worksheet and print a SUMP form for the SYSTEM and each
assembly
PM Planning Manager Select the SUMQ worksheet and print a SUMQ form for the SYSTEM and each
assembly
PM Planning Manager Select the SUMS worksheet and print a SUMS form
PM Planning Manager Select the Project worksheet and click the export button to save a copy of the
consolidated team data for the cycle.
Pro ect and C cle Postmortem
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FORM
Project!Name
Team!B2
Roles!B2
SUMS!B8
Task!A8
Task!A8
Schedule!C8
Task!A8
SUMQ!D82
SUMQ!D55
Team!B2
Task!A8
Schedule!C8
Team!B2
FORM
LOGT!A7
LOGD!A7
Project!Name
Task!A8
Schedule!C8
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Week!C2
Team!A2
Project!Name
Task!A8
Schedule!C8
Week!C2
Project!Name
Project!Name
FORM
See weekly tracking
instructions
Project!Name
See weekly tracking
instructions
SUMP!B2
SUMQ!B2
SUMS!B8
Project!Name
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TSPi - Project Summary
Name Andres Roberto Alvarez Sanchez Date 12-May-12
Project Mechanical-Review Start Date 14-May-12
Team IngeCar Instructor Oscar Hernan Fran Weeks 4
Assembly Cycle 1
Version:TSPi.20041202. 2004 Addison
Wesley .
Today's Date
Override
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Plan Actual Phase %
Design/Code 0 0 Management and Miscellaneous
Code Review 0 0 Launch and Strategy
Compile Defe 1 1 Planning
Unit Test Dde 1 1 Requirements
Design Revie 0 0 System Test Plan
COMPILE 3.47222222 REQ Inspection
CODEINSP 2.77777778 High-Level Design
UT 2.08333333 Integration Test Plan
IT 0 HLD Inspection
ST 0 Detailed Design
1 Year 0 DLD Review
Product Life 0 Test Development
QPI 0 0 DLD Inspection
Code
Code Review
Compile
Code Inspection
Unit Test
Build and Integration Test
System Test
Documentation
Postmortem
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ID Name Initials Phone e-mail
01 Angela Maria Arcila Ramirez AMAR 3136188300 [email protected]
02 Leandro Muoz Murcia LMM 3137295688 [email protected]
03 Andres Humberto Hernandez Gonz AHHG 3172284359 [email protected]
04 Andres Roberto Alvarez Sanchez ARAS 3116453692 [email protected]
05 Camilo Jaramillo Trujillo CJT 3008912786 [email protected]
06
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Workbook Filename
Planned
Tasks
Planned
Task
Hours
Planned
Schedule
Weeks
LiderPlaneacion-Angela.xls
LiderEquipo-Leandro.xls
LiderDesarrollo-Andres.xls
LiderCalidad-Andres.xls
LiderSoporte-Camilo.xls
0 0 0
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Team Member Roles
Team Leader LMM
AMAR
Development Manager AHHG
CJT
Planning Manager AMAR
ARAS
Quality/Process Manager ARAS
LMM
Support Manager CJT
AHHG
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TSPi Plan Summary - Form SUMPName Date 5/12/2012
Team Instructor Oscar Hernan Fran
Assembly Cycle 1
Program Size Plan Actual
Total Requirements Pages (SRS) 0 0Total HLD Pages (SDS)
Total Detailed Design Lines
Base LOC (B) 0 0
Deleted LOC (D) 0 0
Modified LOC (M) 0 0
Added LOC (A) 0 0
Reused LOC (R) 0 0
New and Changed LOC (N) 0 0
Total LOC (T) 0 0
Total New Reuse LOC 0 0
Estimated Object LOC (E)
Upper Prediction Interval (70%)
Lower Prediction Interval (70%)
Time in Phase (hours) Plan Actual Actual%
Management and Miscellaneous 1.0 0.0 0.0%
Launch and Strategy 1.0 0.0 0.0%
Planning 1.0 0.0 0.0%
Requirements 12.0 0.0 0.0%
System Test Plan 1.0 0.0 0.0%
REQ Inspection 1.0 0.0 0.0%
High-Level Design 0.0 0.0 0.0%
Integration Test Plan 0.0 0.0 0.0%
HLD Inspection 0.0 0.0 0.0%
Detailed Design 2.0 0.0 0.0%
DLD Review 0.0 0.0 0.0%
Test Development 0.0 0.0 0.0%
DLD Inspection 0.0 0.0 0.0%
Code 4.0 0.0 0.0%
Code Review 2.0 0.0 0.0%
Compile 2.0 0.0 0.0%
Code Inspection 2.0 0.0 0.0%
Unit Test 0.0 0.0 0.0%
Build and Integration Test 0.0 0.0 0.0%
System Test 0.0 0.0 0.0%
Documentation 1.0 0.0 0.0%
Postmortem 1.0 0.0 0.0%
Total 31.0 0.0 0.0%
Total Time UPI (70%)
Total Time LPI (70%)
Defects Injected Plan Actual Actual%
Planning 0.0 0 0.0%
Requirements 0.0 0 0.0%
System Test Plan 0.0 0 0.0%
REQ Inspection 0.0 0 0.0%
High-Level Design 0.0 0 0.0%
Integration Test Plan 0.0 0 0.0%
Andres Roberto Alvarez Sanchez
IngeCar
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HLD Inspection 0.0 0 0.0%
Detailed Design 0.0 0 0.0%
DLD Review 0.0 0 0.0%
Test Development 0.0 0 0.0%
DLD Inspection 0.0 0 0.0%
Code 0.0 0 0.0%
Code Review 0.0 0 0.0%
Compile 0.0 0 0.0%
Code Inspection 0.0 0 0.0%
Unit Test 0.0 0 0.0%
Build and Integration Test 0.0 0 0.0%
System Test 0.0 0 0.0%
Total Development Defects Injected 0.0 0 0.0%
Defects Removed Plan Actual Actual%
Planning 0.0 0 0.0%
Requirements 0.0 0 0.0%
System Test Plan 0.0 0 0.0%
REQ Inspection 0.0 0 0.0%
High-Level Design 0.0 0 0.0%
Integration Test Plan 0.0 0 0.0%HLD Inspection 0.0 0 0.0%
Detailed Design 0.0 0 0.0%
DLD Review 0.0 0 0.0%
Test Development 0.0 0 0.0%
DLD Inspection 0.0 0 0.0%
Code 0.0 0 0.0%
Code Review 0.0 0 0.0%
Compile 0.0 0 0.0%
Code Inspection 0.0 0 0.0%
Unit Test 0.0 0 0.0%
Build and Integration Test 0.0 0 0.0%
System Test 0.0 0 0.0%
Total Development Defects Removed 0.0 0
Acceptance Test 0.0 0
Product Life 0.0 0
Summary Plan Actual
LOC/Hour 0.0
CPI (Cost-Performance Index)
% Reuse
% New Reuse
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o Bedoya
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Phase Plan
Planning 0
Requireme 0
System Te 0
REQ Inspe 0
High-Level 0
Integration 0HLD Inspe 0
Detailed D 0
DLD Revie 0
Test Devel 0
DLD Inspe 0
Code 0
Code Revi 0
Compile 0
Code Insp 0
Unit Test 0
Build and I 0
System Te 0
Acceptanc 0
Product Lif 0
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Actual
0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
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TSPi Quality Plan - Form SUMQName Date 5/12/2012
Team Instructor Oscar Hernan F
Assembly Cycle 1
SYSTEM Percent Defect Free Actual
In Compile 100.0%In Unit Test 100.0%
In Build and Integration Test 100.0%
In System Test 100.0%
In Acceptance Test 100.0%
In Product Life 100.0%
Defects/Page Plan Actual
REQ Inspection 0.00 0.00
HLD Inspection 0.00 0.00
Defects/KLOC Plan Actual
DLD Review 0.00 0.00
DLD Inspection 0.00 0.00
Code Review 0.00 0.00Compile 0.00 0.00
Code Inspection 0.00 0.00
Unit Test 0.00 0.00
Build and Integration Test 0.00 0.00
System Test 0.00 0.00
Total Development 0.00 0.00
Acceptance Test 0.00 0.00
Product Life 0.00 0.00
Total 0.00 0.00
Defect Ratios Plan Actual
DLD Review/Unit Test 0.00 0.00
Code Review/Compile 0.00 0.00
Development Time Ratios Plan Actual
REQ Inspection/Requirements 0.08 0.00
HLD Inspection/High-Level Design 0.00 0.00
Detailed Design/Code 0.50 0.00
DLD Review/Detailed Design 0.00 0.00
Code Review/Code 0.50 0.00
Inspection/Review Rates Plan Actual
REQ Inspection 0.00 0.00
HLD Inspection 0.00 0.00
DLD Review 0.00 0.00
DLD Inspection 0.00 0.00
Code Review 0.00 0.00Code Inspection 0.00 0.00
A/FR 2.00 0.00
Phase Yields Plan Actual
Planning 0%
Requirements 0%
Andres Roberto Alvarez Sanchez
IngeCar
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System Test Plan 0%
REQ Inspection 0%
High-Level Design 0%
Integration Test Plan 0%
HLD Inspection 0%
Detailed Design 0%
DLD Review 0%
Test Development 0%
DLD Inspection 0%
Code 0%
Code Review 0%
Compile 0%
Code Inspection 0%
Unit Test 0%
Build and Integration Test 0%
System Test 0%
Acceptance Test 0%
Process Yields Plan Actual
% Before Compile 0% 0%
% Before Unit Test 0% 0%
% Before Build and Integration Test 0% 0%% Before System Test 0% 0%
% Before Acceptance Test 0% 0%
Defect Injection Rates (Defects Injected Per Hour) Plan Actual
Planning 0.00
Requirements 0.00
System Test Plan 0.00
REQ Inspection 0.00
High-Level Design 0.00
Integration Test Plan 0.00
HLD Inspection 0.00
Detailed Design 0.00
DLD Review 0.00
Test Development 0.00
DLD Inspection 0.00
Code 0.00
Code Review 0.00
Compile 0.00
Code Inspection 0.00
Unit Test 0.00
Build and Integration Test 0.00
System Test 0.00
Defect Removal Rates Plan Actual
Planning 0.00 0.00
Requirements 0.00 0.00
System Test Plan 0.00 0.00REQ Inspection 0.00 0.00
High-Level Design 0.00 0.00
Integration Test Plan 0.00 0.00
HLD Inspection 0.00 0.00
Detailed Design 0.00 0.00
DLD Review 0.00 0.00
Test Development 0.00 0.00
DLD Inspection 0.00 0.00
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Code 0.00 0.00
Code Review 0.00 0.00
Compile 0.00 0.00
Code Inspection 0.00 0.00
Unit Test 0.00 0.00
Build and Integration Test 0.00 0.00
System Test 0.00 0.00
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ranco Bedoya
Phase Yield Planning Guidelines
Planning 0%
Requirements 0%
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System Test Plan 0%
REQ Inspection 70% Not counting editorial comments
High-Level Design 0%
Integration Test Plan 0%
HLD Inspection 70% Using state analysis, trace tables
Detailed Design 0%DLD Review 70% Using state analysis, trace tables
Test Development 0%
DLD Inspection 70% Using state analysis, trace tables
Code 0%
Code Review 70% Using personal checklists
Compile 50% 90+ % of syntax defects
Code Inspection 70%
Unit test - at < 5 defects/KLOC 90% For high defects/KLOC - 50-75%
Integration test at < 1.0 defects/KLOC 80% For high defects/KLOC - 30-65%
System test - at < 1.0 defects/KLOC 80% For high defects/KLOC - 30-65%
Acceptance test - at < 1.0 defects/KLOC 65% For high defects/KLOC - 30%
Defect Injection Rates Planning Guidelines
Planning 0
Requirements 0.25 Only major defects
System Test Plan 0
REQ Inspection 0
High-Level Design 0.25 Only major defects
Integration Test Plan 0
HLD Inspection 0
Detailed Design 0.75 Only design defects
DLD Review 0
Test Development 0
DLD Inspection 0
Code 2 All defects
Code Review 0
Compile 0.3 Any defects
Code Inspection 0
Unit Test 0.067 Any defects
Build and Integration Test 0
System Test 0
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TSPi Size Summary - Form SUMSName
Team
Date
Instructor
Cycle Planned Size
ID
Assembly, Sub-Assembly, or
Part Name
(A)ss
embly
or
(P)art
Parent Assembly Name
Own
er Size Measure Base Deleted
Modifie
d Added
1 Programacion de Citas A SYSTEM AHH LOC 0 0 0 0
2 Agenda Diaria A SYSTEM AHH LOC 0 0 0 0
3 Gestion de Clientes A SYSTEM LMM LOC 0 0 0 0
4 Gestion de Usuarios A SYSTEM ARA LOC 0 0 0 0
5 Gestion de Vehiculos A SYSTEM AMA LOC 0 0 0 0
6 Gestion de Procedimientos de A SYSTEM CJT LOC 0 0 0 0
7 Autenticacion de Usuario A SYSTEM ARA LOC 0 0 0 0
Andres Roberto Alvarez Sanchez
IngeCar
5/12/2012
Oscar Hernan Franco Bedoya
1
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Actual Size Planned Defects Injec
Reused
New
and
Change
d Total
Total
New
Reuse Base Deleted
Modifie
d Added Reused
New
and
Change
d Total
Total
New
Reuse
Plannin
g
Require
ments
System
Test
Plan
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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ted
REQ
Inspecti
on
High-
Level
Design
Integrat
ion
Test
Plan
HLD
Inspecti
on
Detaile
d
Design
DLD
Review
Test
Develo
pment
DLD
Inspecti
on Code
Code
Review
Compil
e
Code
Inspecti
on
Unit
Test
Build
and
Integrat
ion
Test
System
Test
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Actual Defects Injected
Accept
ance
Test
Product
Life
Planni
ng
Requi
remen
ts
Syste
m
Test
Plan
REQ
Inspe
ction
High-
Level
Desig
n
Integr
ation
Test
Plan
HLD
Inspe
ction
Detail
ed
Desig
n
DLD
Revie
w
Test
Devel
opme
nt
DLD
Inspe
ction Code
Code
Revie
w
Comp
ile
Code
Inspe
ction
Unit
Test
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Planned Defects Removed
Build
and
Integr
ation
Test
Syste
m
Test
Accep
tance
Test
Produ
ct Life
Planni
ng
Requi
remen
ts
Syste
m
Test
Plan
REQ
Inspe
ction
High-
Level
Desig
n
Integr
ation
Test
Plan
HLD
Inspe
ction
Detail
ed
Desig
n
DLD
Revie
w
Test
Devel
opme
nt
DLD
Inspe
ction Code
Code
Revie
w
Comp
ile
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Actual Defects Removed
Code
Inspe
ction
Unit
Test
Build
and
Integr
ation
Test
Syste
m
Test
Accep
tance
Test
Produ
ct Life
Planni
ng
Requi
remen
ts
Syste
m
Test
Plan
REQ
Inspe
ction
High-
Level
Desig
n
Integr
ation
Test
Plan
HLD
Inspe
ction
Detail
ed
Desig
n
DLD
Revie
w
Test
Devel
opme
nt
DLD
Inspe
ction Code
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Planned Time
Code
Revie
w
Comp
ile
Code
Inspe
ction
Unit
Test
Build
and
Integr
ation
Test
Syste
m
Test
Accep
tance
Test
Produ
ct Life
Manag
ement
and
Miscell
aneous
Launch
and
Strateg
y
Plannin
g
Require
ments
System
Test
Plan
REQ
Inspecti
on
High-
Level
Design
Integrat
ion
Test
Plan
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0
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Actual
HLD
Inspecti
on
Detaile
d
Design
DLD
Review
Test
Develo
pment
DLD
Inspecti
on Code
Code
Review
Compil
e
Code
Inspecti
on
Unit
Test
Build
and
Integrat
ion
Test
System
Test
Docum
entatio
n
Postmo
rtem
Manag
ement
and
Miscell
aneous
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 2 1 1 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 2 1 1 1 0 0 0 0 0 0
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ime
Launch
and
Strateg
y
Plannin
g
Require
ments
System
Test
Plan
REQ
Inspecti
on
High-
Level
Design
Integrat
ion
Test
Plan
HLD
Inspecti
on
Detaile
d
Design
DLD
Review
Test
Develo
pment
DLD
Inspecti
on Code
Code
Review
Compil
e
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Code
Inspecti
on
Unit
Test
Build
and
Integrat
ion
Test
System
Test
Docum
entatio
n
Postmo
rtem
Baseline
Plan Date
Baselin
e Plan
Hours
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
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TSPi Task Planning Template - Form TASKName Andres Roberto Alvarez Sanchez
Team IngeCar
Date 5/12/2012
Instructor Oscar Hernan Franco Bedoya
Cycle 1
Assembly Phase Task
SYSTEM MGMT SYSTEM Management and Miscellaneous
SYSTEM STRAT SYSTEM Launch and Strategy
SYSTEM PLAN SYSTEM Planning
SYSTEM REQ SYSTEM Use Case Model
SYSTEM REQ SYSTEM Requirements
SYSTEM STP SYSTEM System Test Plan
SYSTEM REQINSP SYSTEM REQ Inspection
Gestion de Usuarios REQ CU Specification
Gestion de Usuarios REQ MockupGestion de Usuarios REQ Analisys Class
Gestion de Usuarios REQ Sequence Diagram
Gestion de Usuarios DLD Detailed Design
Gestion de Usuarios CODE Code
Gestion de Usuarios CR Code Review
Gestion de Usuarios COMPILE Compile
Gestion de Usuarios CODEINSP Code Inspection
Autenticacion de Usuario REQ CU Specification
Autenticacion de Usuario REQ Mockup
Autenticacion de Usuario REQ Analisys Class
Autenticacion de Usuario REQ Sequence Diagram
Autenticacion de Usuario DLD Detailed Design
Autenticacion de Usuario CODE Code
Autenticacion de Usuario CR Code Review
Autenticacion de Usuario COMPILE Compile
Autenticacion de Usuario CODEINSP Code Inspection
SYSTEM DOC SYSTEM Documentation
SYSTEM PM SYSTEM Postmortem
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Total Plan Hours
Reminder:
If Size and Rate are present, estimated hours is calculated as Size / Rate
whenever the plan is updated. To prevent calculation, size or rate must be bla
Team
Leade
r
opme
nt
Mana
ger
Planni
ng
Mana
ger
y/Proc
ess
Mana
ger
Supp
ort
Mana
ger
Total
Resour
ce
Hours
Estimate
d Size
Size
Meas
ure
Rate
(per
Hr.)
Time
in
Phase
%
Engr
s
Plan
Hours Plan Date
Plan
Wee
k
Actual
Hours
1 1 1.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
2 2 2.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
2 2 180 LOC 2.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
2 2 2.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
2 2 140 LOC 2.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
1 1 1.0 0.0
31.0
Plan Hours by Role
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Total Actual Hours
nk.
Actual Date
Actu
al
Wee
k
Earne
d
Value
Cumulati
ve Plan
Hours
Cumula
tive
Plan
Value
Plan
Value
Predicted
Date
Plan Date +
Current Slip
Committed
Date
Baseline
Date
Baseline
Plan Hours
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
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NotesStart
Wee
k PHISW PHIEW
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
0 0.0 0.0
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TSPi Schedule Planning Template - Form SCHEDULEName Andres Roberto Alvarez Sanchez
Team IngeCar Total Task Plan Hours 31.0
Date 5/12/2012 Total Schedule Plan Hours 31.0
Instructor Oscar Hernan Franco Bedoya Difference 0.0
Cycle 1
Date Week
Planned
Hours
Cumulativ
e Planned
Hours
Actual
Hours
Cumulativ
e Actual
Hours
Planned
Value
Cumulativ
e Planned
Value
Earned
Value
Cumulativ
e EV
Predicted
Hours
5/14/2012 1 8.0
5/21/2012 2 7.0
5/28/2012 3 7.0
6/4/2012 4 9.0
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Cumulativ
e
Predicted
Hours
Predicted
Earned
Value
Cumulativ
e
Predicted
Earned
Value
Baseline
Plan
Hours
Baseline
Cumulativ
e Plan
Hours
Baseline
Plan Value
Baseline
Cumulativ
e Plan
Value
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Notes
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TSPi Time Recording Log - Form LOGTName Date
Team Instructor
Cycle
Hours
Assembly Phase Task Date Start Int. Stop Delta
SYSTEM ITP SYSTEM Integration Test Plan 05/12/12 10:59:33 10:59:35 0.0
Andres Roberto Alvarez Sanchez 5/12/2012
IngeCar Oscar Hernan Franco
1.0
0.0
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Comments
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TSPi Defect Recording Log - Form LOGDName Date 5/12/2012
Team Instructor Oscar Hernan Franco Bedoya
Cycle 1
Date Num Type Assembly Injected Removed
Fix
Time Fix Ref.
1 30 Control Pacient PLAN HLD
Andres Roberto Alvarez S
IngeCar
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Description
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TSPi Week Summary - Form WEEKName
Team
Status for Week 1 Selected Assembly
Week Date 5/14/12 SYSTEM
Task Hours %Change Weekly Data Plan Actual
Baseline 0.0 Schedule hours for this week 8.0 0.0
Current 31.0 Schedule hours this cycle to date 0.0 0.0
%Change Earned value for this week 0.0 0.0
Earned value this cycle to date 0.0 0.0
To-date hours for tasks completed 0.0 0.0
To-date average hours per week 0.0 0.0
EV per completed task hour to date
Consolidated Team Member Schedule Data
Plan
Hours
Team Leader
Development Manager
Planning Manager
Quality/Process Manager
Support Manager
Totals 0.0
Development Tasks
Completed Phase Task Resource
Task Plan
Hrs.
TASKS DUE THROUGH WEEK 3
SYSTEM MGMT SYSTEM Management and Miscellaneous 1.0
SYSTEM STRAT SYSTEM Launch and Strategy 1.0
SYSTEM PLAN SYSTEM Planning 1.0
SYSTEM REQ SYSTEM Use Case Model 1.0
SYSTEM REQ SYSTEM Requirements 1.0SYSTEM STP SYSTEM System Test Plan 1.0
SYSTEM REQINSP SYSTEM REQ Inspection 1.0
Gestion de Usuarios REQ CU Specification 2.0
Gestion de Usuarios REQ Mockup 1.0
Gestion de Usuarios REQ Analisys Class 1.0
Gestion de Usuarios REQ Sequence Diagram 1.0
Gestion de Usuarios DLD Detailed Design 1.0
Gestion de Usuarios CODE Code 2.0
Gestion de Usuarios CR Code Review 1.0
Gestion de Usuarios COMPILE Compile 1.0
Gestion de Usuarios CODEINSP Code Inspection 1.0
Autenticacion de Usuario REQ CU Specification 2.0
Autenticacion de Usuario REQ Mockup 1.0
Autenticacion de Usuario REQ Analisys Class 1.0
Autenticacion de Usuario REQ Sequence Diagram 1.0
Autenticacion de Usuario DLD Detailed Design 1.0
Autenticacion de Usuario CODE Code 2.0
Autenticacion de Usuario CR Code Review 1.0
Autenticacion de Usuario COMPILE Compile 1.0
Autenticacion de Usuario CODEINSP Code Inspection 1.0
SYSTEM DOC SYSTEM Documentation 1.0
Andres Roberto Alvarez Sanchez
IngeCar
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SYSTEM PM SYSTEM Postmortem 1.0
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Date 5/12/12
Instructor Oscar Hernan Franco Bedoya
Cycle 1
Plan /
Actual
Plan -
Actual
8.0 Baseline 1/0/00
0.0 Plan 1/0/00
0.0 Predicted
0.0
Actual
Hours
Plan
Value
Earned
Value
0.0 0.0 0.0
Task
Actual
Hrs.
Earned or
Plan
Value
Plan vs.
Actual
Hrs.
Baseline
or
Committe
d Date Plan Date Slip Date
Predicted
Date
Actual
Date
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
0.0 12:00:00 a.m.
Project End Date
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0.0 12:00:00 a.m.
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TSPi Issue/Risk Tracking Log - Form IRTLName Date 5/12/2012
Team tructor Oscar Hernan Franco Bedoya
Cycle 1
Issue or
Risk
Number
R=Ris
k
I=Issu
e
Date
Created
P=Per
sonal
T=Te
am
Likeli
hood
(H,M,
L)
Impac
t
(H,M,
L) Owner
Follow-up
Date Description
Andres Roberto Alvarez Sanchez
IngeCar
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Current Status
Date Status
Changed
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TSPi Issue Risk Week Summary - Form IRWEEKName Date 5/12/2012
Team Team Oscar Hernan Franco Bedoya
Week 1 Cycle 1
Issue/Risk
Number
P=Per
sonal
T=Tea
m
R=Ris
k
I=Issu
e Description Status
Andres Roberto Alv
IngeCar
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Type Description
10 Documentation
20 Syntax
30 Build, Package
40 Assignment
50 Interface60 Checking
70 Data
80 Function
90 System
100 Environment
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Parameter Value Description
Design/Code Time 100% Design time as % of coding time
Code Review Time 50% Code review time as % of code time
Compile Defects/KLOC 10 Compile defects/KLOC
Unit Test Ddefects/KLOC 5 Unit test defects/KLOC
Design Review Time 50% Design review time as % of design time
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