lat sumit res
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CURRICULUM VITAE Current Location: New Delhi (NCR) Tel :+919582400356 Email:[email protected] Sumit Sharma Objective Wish to serve an organization in VLSI Domain and Embedded domain which provides me sample opportunities to grow and contribute to the better world by creating value together with a vision for the future. Educational Qualifications M. Tech. B. Tech. ITM University , Gurgaon , Haryana Institute Of Engineering And Technology , Alwar (affiliated to RTU,Kota) 2013- 2015 2008- 2012 High School SBV , Palam(affiliated to CBSE Board ) 2007- 2008 Matricula tion SBV , Palam(affiliated to CBSE Board) 2005- 2006 Skills Sequential Language C, C++ language, Verilog , System Verilog Operating system Windows 7,Linux(Red Hat),Windows Xp Project Work Energy saver using microcontroller 8051: Basically it was controlling switching of A.C appliances using relay. Moving message display system using 8051: It was just a wireless message display technique using Sim module and microcontroller. 1
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CURRICULUM VITAECurrent Location: New Delhi (NCR) Tel :+919582400356 Email:[email protected]
Sumit Sharma
ObjectiveWish to serve an organization in VLSI Domain and Embedded domain which provides me sample opportunities to grow and contribute to the better world by creating value together with a vision for the future.Educational Qualifications
M. Tech.B. Tech.
ITM University , Gurgaon , HaryanaInstitute Of Engineering And Technology , Alwar(affiliated to RTU,Kota)
2013-20152008-2012
High School SBV , Palam(affiliated to CBSE Board ) 2007-2008Matriculation SBV , Palam(affiliated to CBSE Board) 2005-2006
Skills Sequential Language
C, C++ language, Verilog , System Verilog Operating system
Windows 7,Linux(Red Hat),Windows Xp
Project Work Energy saver using microcontroller 8051: Basically it was controlling switching of A.C
appliances using relay. Moving message display system using 8051: It was just a wireless message display
technique using Sim module and microcontroller. FPGA Implementation of Booth Multiplier using Verilog. Verification of Synchronous FIFO with System Verilog. Advanced encryption standard 128 bit key using Verilog. Thesis project advanced encryption standard 256 bit key using vhdl.
Training AssociatesMTNL , New DelhiXinoe Pvt. Ltd , GurgaonTevatron technologies pvt. Ltd
: GSM, CDMA, Switching System, Optical Fibre.: System Verilog Verification using UVM 1.1: Verilog and Vhdl, System Verilog, etc.
Seminars/Workshops
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Seminar delivered on “Transparent Electronics”. Attended the seminar on “ CYBER CRIME “ Attended a value added program on Linux scripting. Attended a workshop on Linux. Attended a 5 day workshop on ethical hacking and securities. Attended a workshop on robotics.
Area of Interest RTL Design and Verification Digital VLSI Design EDA Tool designing
personal Traits1. Innovative Thinker2. Goal Focused3. Quick Learner4. Leadership quality
ReferencesNeeraj Kr. Shukla Professor
Department of EECEITM UniversityHUDA Sector-23A,Gurgaon-122017 (Haryana) IndiaE-Mail: [email protected]. +91-9212628151
Personal DossierDate of Birth : 01th April 1991
Father's Name : Mr Rajesh Sharma
Languages known : English, Hindi.
Marital Status : Single
Sex : Male
Nationality : Indian
Address : D-208/40,MadhuVihar,Uttam Nagar
New Delhi,India 110059
Declaration:
I consider myself familiar with programming and scripting aspects. I am also confident of my ability to work in a team and be an asset to your company.
I hereby declare that the information furnished above is true to best of my knowledge.
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Place: New Delhi (Sumit Sharma)
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