Lab09 ASIC Logic - access.ee.ntu.edu.twaccess.ee.ntu.edu.tw/course/soc2003/SoC Material Version...
Transcript of Lab09 ASIC Logic - access.ee.ntu.edu.twaccess.ee.ntu.edu.tw/course/soc2003/SoC Material Version...
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SOC Consortium Course Material
ASIC LogicASIC Logic
Speaker: Lung-Hao Chang 張龍豪Advisor: Prof. Andy Wu 吳安宇教授
May 21, 2003
National Taiwan UniversityAdopted from National Chiao-Tung University
IP Core Design
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2SOC Consortium Course Material
Goal of This Lab
qPrototypingqFamiliarize with ARM Logic Module (LM)qKnow how to program LM
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3SOC Consortium Course Material
Outline
qIntroductionqARM System OverviewqPrototyping with Logic ModuleqLab – ASIC Logic
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4SOC Consortium Course Material
Introduction
qRapid Prototyping – A fast way to verify your prototype design.– Enables you to discover problems before tape out.– Helps to provide a better understanding of the design’s
behavior.
qARM Integrator and Logic Module can be used for Hardware Design Verification and HW/SW co-verification.– Hardware Design Verification: using LM stand alone.– HW/SW co-verification: using LM, CM, Integrator together.
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5SOC Consortium Course Material
Outline
qIntroductionqARM System Overview
– ARM Synchronization Scheme: Interrupt– ARM Synchronization Scheme: Polling
qPrototyping with Logic ModuleqLab – ASIC Logic
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6SOC Consortium Course Material
ARM System Overviewq A typical ARM system consists of an ARM core, a DSP chip
for application-specific needs, some dedicated hardware accelerator IPs, storages, and some peripherals and controls.
GPIOsInterrupt
Controller
On chip memorycontroller and
memory
ARM920T DSP CHIPMotion
EstimationAccelerator IP
AHB
AHB-to-APBBridge
Direct MemoryAccess (DMA)
Real TimeCounter Timers LCD Controller
USBController
Remote KB/Mouse
Controller
APB
ExternalMemory
Controller
ExternalMemory
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7SOC Consortium Course Material
ARM System Synchronization Scheme: Interrupt
q A device asserts an interrupt signal to request the ARM core handle it.
q The ARM core can perform tasks while the device is in use.q Needs Interrupt Controller. More hardware.
IP0
Interrupt Controller
ARM CORE
IP1 IP2 IP3IP0, IP1, IP2, and IP3 raised interruptrequest (IRQ) at the same time. TheIRQs are sent to the interrupt controller.
Interrupt controller receives the IRQsand update the IRQ status indicating theIRQ sources.
ARM core receives the IRQs,deteremines which IRQ should behandled according to programmedpriorities. and then executes thecorresponding interrupt service routine(ISR).
IP 0
clear IP0's IRQ
The ISR performs its operations andclears the IP0's interrupt.
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8SOC Consortium Course Material
ARM System Synchronization Scheme: Polling
q The ARM core keeps checking a register indicating if the device has done its task.
q The ARM core is busy “polling”the device while the device is in use.
q Less hardware.
ARM COREARM core polls IP0's ready register afterIP0 has been enabled.
Once IP0 is done with its operation,ARM core will know from the changedvalue of the ready register.
ARM core will execute thecorresponding operations and thendisable IP0.
IP 0
Disable IP0Polling IP0
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9SOC Consortium Course Material
Outline
qIntroductionqARM System OverviewqPrototyping with Logic Module
– ARM Integrator AP & ARM LM– FPGA tools– Example 1– Example 2– Exercise
qLab – ASIC Logic
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10SOC Consortium Course Material
AP Layout
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11SOC Consortium Course Material
What is LM
qLogic ModuleqA platform for developing Advanced
Microcontroller Bus Architecture (AMBA), Advanced System Bus (ASB), Advanced High-performance Bus (AHB), and Advanced Peripheral Bus (APB) peripherals for use with ARM cores.
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12SOC Consortium Course Material
qIt can be used in the following ways:– As a standalone system– With an CM, and a AP or SP motherboard– As a CM with either AP or SP motherboard if a
synthesized ARM core is programmed into the FPGA– Stacked without a motherboard, if one module in the stack
provides system controller functions of a motherboard
Using the LM
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13SOC Consortium Course Material
LM Architecture
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14SOC Consortium Course Material
Components of LMqAltera or Xilinx FPGAqConfiguration PLD and flash memory for storing
FPGA configurationsq1MB ZBT SSRAMqClock generators and reset sourcesqA 4-way flash image selection switch and an 8-way
user definable switchq9 user-definable surface-mounted LEDs (8G1R)qUser-definable push buttonqPrototyping gridqSystem bus connectors to a motherboard or other
modules
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15SOC Consortium Course Material
LM Layout
8-way swtich
4-way swtich
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16SOC Consortium Course Material
Links
qCONFIG link– Enable configuration mode, which changes the JTAG
signal routing and is used to download new PLD or FPGA configurations.
qJTAG, Trace, and logic analyzer connectorsqOther links, switches, and small ICs can be added
to the prototyping grid if required.
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17SOC Consortium Course Material
FPGA tools
Xilinx GUI Synthesis Tool
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18SOC Consortium Course Material
A Timing Information Example
We strongly suggest you to perform place-and-route operation on a better PC, it’s a very time-consuming work!
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19SOC Consortium Course Material
Example 1
qPath = .\lab5\Codes\HW\example1\qCount up on logic analyzer channel aqCount down on logic analyzer channel bqReset by pushbuttonqLEDs scan from left to right.qSwitches [0:1] (brown:red) control the clock
frequency (CTRLCLK1) and affect the LEDsscanning frequency.
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20SOC Consortium Course Material
Example 1 (cont.)
Example1
CLK1
nPBUTT
SW[1:0]
LED[7:0]LAA[15:0]
LAACLKLABCLKCTRLCLK1[18:0]
PWRDNCLK1, PWRDNCLK2,
SnCE, FnOE, FnWE
LAB[15:0]
CTRLCLK2[18:0]
Logic Analyser
Set Frequency1MHz
0 1
111Disable SSRAM and FLASH
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21SOC Consortium Course Material
On-board Clock Generators
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22SOC Consortium Course Material
Clock Signal Summary
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23SOC Consortium Course Material
Programming the LM Clock
1MHz: CTRLCLKx=19'b11001111100000001002MHz: CTRLCLKx=19'b11000111100000001005MHz: CTRLCLKx=19'b1100001110000000111
10MHz: CTRLCLKx=19'b1100000110000000111
Constraint:
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24SOC Consortium Course Material
Example 2
qThe example code operates as follows:1. Determines DRAM size on the core module and sets up
the system controller2. Checks that the logic module is present in the AP
expansion position3. Reports module information4. Sets the logic module clock frequencies5. Tests SSRAM for word, halfword, and byte accesses.6. Flashes the LEDs7. Remains in a loop that displays the switch value on the
LEDs
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25SOC Consortium Course Material
Two Platform – AHB & ASB
q Two versions of example 2 are provided to support the following implementations:– AHB motherboard and
AHB peripherals– ASB motherboard and
AHB peripherals
qWhich AMBA has been downloaded on board can be observed by the alphanumber display– H: AHB– S: ASB
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26SOC Consortium Course Material
AHB Platform
AHBAHBTop
AHBDecoder
AHBMuxS2M
AHBZBTRAM
AHB2APB
AHBAPBSys
APBRegs
APBIntcon
Core SDRAM OtherModules
AHB
AH
BA
PB
ZBTSRAM
MYIP
Logical Module
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27SOC Consortium Course Material
Example2 Files Descriptionq Hardware files .\Lab7\Codes\HW\example2\Verilog
– AHBAHBTop.v– AHBDecoder.v– AHBMuxS2M.v– AHBZBTRAM.v– AHB2APB.v– AHBAPBSys.v– APBIntCon.v– APBRegs.v
q Software program files .\Lab7\Codes\SW\example2\– sw.mcp– logic.c – logic.h– platform.h– rw_support.s
For Xilinx synthesis tool to generatelmxcv600e_72c_xcv2000e_via_reva_build0.bit
For codewarrior to generatesw.axf
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28SOC Consortium Course Material
Software Description
q5 files included in .\Lab7\Codes\SW\example2\– sw.mcp: project file– logic.c: the main C code– logic.h: constant definitions– platform.h: constant definitions– rw_support.s: assembly functions for SSRAM testing
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29SOC Consortium Course Material
Integrator Memory Map
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30SOC Consortium Course Material
Work Flow Summary
Run the AXD image with MultiICE
Prepare HDLDesign
Synthesis
Place&RouteFPGA Bitstream
Generation
Prepare SoftwareDesign
Make & BuildAXD ImageGeneration
Downloading theBitstream to LM's
FPGA
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31SOC Consortium Course Material
Outline
qIntroductionqARM System OverviewqPrototyping with Logic ModuleqLab – ASIC Logic
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32SOC Consortium Course Material
Lab 5: ASIC Logicq Goal
– HW/SW Co-verification using Rapid Prototyping
q Principles– Basics and work flow for
prototyping with ARM Integrator– Target platform: AMBA AHB sub-
systemq Guidance
– Overview of examples used in the Steps
q Steps– Understand the files for the
example designs and FPGA tool– Steps for synthesis with Xilinx
ISE 5.1i/5.2i
q Requirements and Exercises– RGB-to-YUV converting hardware
module. See next slide
q Discussion– In example 1, explain the differences
between the Flash version and the FPGA one.
– In example 1, explain how to move data from DRAM to registers in MYIP and how program access these registers.
– In example2, draw the interconnect among the functional units and explain the relationships of those interconnect and functional units in AHB sub-system
– Compare the differences of polling and interrupt mechanism
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33SOC Consortium Course Material
Exercise: RGB to YCrCb Converter
qConvert the rgb2ycrcb() into hardware module and implement it on the ARM development system. Evaluate the improvement.– Hint: you may modify ahbahbtop.v, ahbdecoder.v,
ahbmuxs2m.v, and ahbzbtram.v files in example2
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34SOC Consortium Course Material
Reference
[1] http://twins.ee.nctu.edu.tw/courses/ip_core_02/index.html[1] LM-XCV2000E.pdf[2] DUI0098B_AP_UG.pdf
[3] progcards.pdf