Lab. I - 1

Lab. I1. CADENCE 를 이용한 LayoutLab. I1. CADENCE 를 이용한 Layout

Lab. I - 2

Physical Design Environment FlowPhysical Design Environment FlowSetup Tech File

Defining components

Creating a SchematicDesign Entry

Developingparameterized cells

Simulatingthe schematic

HSPICE

Laying out and editing designsVirtuoso Layout Editor

Generating layoutfrom schematic

Connectivity drivenlayout editing

Create abstractcellview

Placeand

Route

Automatic device levelrouting

Compacting designsand

applying design rulesVerifying

symbolic designs

Verifying designsLVS, DRC

Parasitic simulationHSPICE

Verifying final chip andpreparing mask

Lab. I - 3

Terms and DefinitionsTerms and Definitions

Library a collection of cells that corresponds to a specific process

technology

Cell a design object that forms an individual building block of a

chip or system

View a defined representation of a cell in the technology file with a

registered viewType property

CIW the Command Interpreter Window, which is the initial control

window that appears when you start Design Framework II

Lab. I - 4

Command Interpreter Window (CIW)Command Interpreter Window (CIW)

Input FieldSKILL functions or expressions

Output FieldRunning history of commands

Menu banner Log file

Invoking Library Manager

Lab. I - 5

Library StructureLibrary Structure

Library a collection of cellscontains all the different views associated with each of

the cells

Cella low-level building block used to create a chip or

logical system

Viewa particular representation of a celleach cell can have a layout view, schematic view,

symbolic view, and etc.

Lab. I - 6

nor2nmos2

Library Structure (cont.)Library Structure (cont.)

sample

nmos

symbol layout cdl

Library

Cell

View

G

D

S G

SD

Lab. I - 7

Defining Libraries to EditDefining Libraries to Edit

displays libraries found in the cds.lib file lets you edit the cds.lib online in this form you can

add/remove librariessave information to the cds.lib file

Lab. I - 8

Opening a New LibraryOpening a New Library

create a new library read a ASCII technology file

Lab. I - 9

Opening a New DesignOpening a New Design

use either the Open File form or the Library Manager

Lab. I - 10

Display OptionsDisplay Options

Display level indicates the highest and

lowest levels in the design hierarchy that can be seen in a detailed cellview

Grid control minor grid : the distance

between each gridpoint major grid : the number of

minor gridpoints between each major gridpoint

Lab. I - 11

Layer Selection WindowLayer Selection Window

Visibility click with the middle button

on the layer name AV : all visible NV : none visible

Selectability click with the right button on

the layer name AS : all selectable NS : none selectable

all instances andpins selectable

library name

current drawinglayer

Lab. I - 12

Selecting ObjectsSelecting Objects

Select one object at a time

Select all objects in an area

click left to select The selected objectis highlighted

Shift click to selectanother object

drag left mouse

Lab. I - 13

Moving and Stretching ObjectsMoving and Stretching Objects

Press left on a startpoint

Press and hold the left mousebutton until the object is placed.

Moving objects Stretching objects

After selecting an edgethe arrow apears

Press left on the start point

Press and drag the left mousebutton to stretch the object

Lab. I - 14

Pan and ZoomPan and Zoom

Panning let you move your

viewing window to different areas of the designs

direction : vertical, horizontal, diagonal

Zooming let you zoom in or zoom

out bindkey : Shift-z(zoom

out) Control-z(zoom in)

use the arrow keys

zoom out [Z]

zoom in [^Z]

Lab. I - 15

BindkeyBindkey

Two command style select object + select

command + do command select command + select

object + do command

When mouse pointer approaches to an objects or an edge, it is highlighted in yellow dashed line

When an object is selected, it is highlighted in white line

When a command is selected, an instruction appears in the bottom line of the editor window

type ‘ESC’ to deselect a command

type ‘^D’ to deselect an object

Lab. I - 16

Bindkey (cont)Bindkey (cont)

Zoom in z + ‘click SP’ + ‘click EP’ z + ‘drag region’

ruler k + ‘click SP’ + ‘click EP’ K : delete all ruler

rectangle r + ‘click SP’ + ‘click EP’ r + ‘drag region’

stretch s + ‘click edge’ + ‘click

EP’

Copy c + ‘click object’ + ‘click

destination’

delete d + ‘click object’

path p + ‘click SP’ + ‘click MP’

+ … + ‘click EP’

full view f : view through the

bottom level layout ^F : view only the top

level layout*SP : start point*EP : end point*MP : middle point

Lab. I - 17

Layout Example - InverterLayout Example - Inverter

1st version 2nd version

Lab. I - 18

Layout Example - Two InvertersLayout Example - Two Inverters

Place two inverters(top view)

Place two inverters(full view)

align and route

Lab. I - 19

Lab. I2. CADENCE 를 이용한 Circuit Extraction

Lab. I2. CADENCE 를 이용한 Circuit Extraction

Lab. I - 20

DIVA ToolDIVA Tool DRC (Design Rule Check)

typical checks include material spacing, enclosure, and overlap

Extractor device parameters and connectivity are extracted from the layout

LVS (Layout Versus Schematic) performs design matching of nets, devices, and device

parameters compares any combination of physical or schematic designs

Lab. I - 21

DRC (Design Rule Check)DRC (Design Rule Check)

Switch namename parts of the DRC rules you want to execute

click left button

Lab. I - 22

Finding Errors with ExplainFinding Errors with Explain

CIW message after DRC finishes

click left button

Lab. I - 23

ExtractionExtraction

Extract Method flat : creates a single level extracted view, regardless of

the design hierarchy of the layout

click left button

Lab. I - 24

Making SPICE NetlistMaking SPICE Netlist

Top Cell Name select top cell name

View Name select extracted view

Library Name select cell library

Output FileSPICE file name

Lab. I - 25

Lab. I3. CADENCE 를 이용한 Schematic Edit

Lab. I3. CADENCE 를 이용한 Schematic Edit

Lab. I - 26

Composer Schematic WindowComposer Schematic Window

Select library name

type cell name

type ‘schematic’ as view name

Lab. I - 27

Select ComponentSelect Component

Select nmos->symbol

Lab. I - 28

Place MOSPlace MOS

Select pmos->symboland

place PMOS

Lab. I - 29

Connect WireConnect Wire

Add->wire

left button click

right button click

Lab. I - 30

Add pinAdd pin

1. Type pin name

2. Click left button

Lab. I - 31

Add VDD/GNDAdd VDD/GND

Add->component

Click left button

Save schematic

Lab. I - 32

Create CellViewCreate CellView

Symbol 에서pin 의 위치

Lab. I - 33

Edit SymbolEdit Symbol

삼각형은 edit menu를 이용하여 그린다 .

Lab. I - 34

Design Buffer with New SymbolDesign Buffer with New Symbol

Select new symbol(myinv)

Lab. I - 35

Lab. I4. CADENCE 를 이용한 LVSLab. I4. CADENCE 를 이용한 LVS

Lab. I - 36

LVS(Layout Versus Schematic)LVS(Layout Versus Schematic)

Checks the consistency of connectivity and devices between the extracted cellview of a layout and the schematic it was designed from

generated fromschematic

generated fromlayout

Lab. I - 37

Running LVS and Finding ErrorsRunning LVS and Finding Errors

1

2

3

Lab. I - 38

Analyzing ResultsAnalyzing Results

Unmatchednet : shows nets that cannot be matched instances : shows device that cannot be matched terminals : shows rewired devices and unmatched pins

Prunednet and instances show objects that you want LVS to

ignore

Mergednets shows nets that, if connected, would compare

correctly between views

Lab. I - 39

Lab. I5. CADENCE 를 이용한 16 비트 가산기의 설계

Lab. I5. CADENCE 를 이용한 16 비트 가산기의 설계

Lab. I - 40

실습 과제 - 16 비트 가산기 설계실습 과제 - 16 비트 가산기 설계

내용16 비트 가산기의 레이아웃가산기의 종류는 관계없음셀의 비트당 높이는 60um 임SPICE 시뮬레이션 조건

동작 온도 : 85(centigrade)입력전압의 rise/fall time : 0.5nsec출력 load : 0.5pF

사용 공정0.6um TLM (idec.tf)

제출 방법homepage 에 공지 예정

http://sonata.kaist.ac.kr/course/ideclab

Lab. I - 41

16 비트 가산기의 설계 예(Carry Selector Adder)16 비트 가산기의 설계 예(Carry Selector Adder)

SumGeneration

LogicSum = A B Ci

CarryGeneration

LogicCout = A*B + Ci(A + B)

Ci

CoutA B SumA B

1 비트 가산기

4 비트 가산기

Lab. I - 42

Datapath Design ExampleDatapath Design Example

16-bit adder

MUX[0]

MUX[1]

MUX[2]

MUX[3]

Block 별로 일정

bit 별로 일정

Lab. I - 43

Project Directory SetupProject Directory Setup

Setup working directorymkdir ideclab

copy environment file idec06.tf (0.6um technology file)display.drf (display resource file)divaDRC.rul (DRC, extraction rule file)divaLVS.rul (LVS rule file)cdsinit (initialization file)

Lab. I - 44

조교 연락처박봉일 : bipark@duo.kaist.ac.kr양우승 : woosee@duo.kaist.ac.kr이재곤 : topgon@duo.kaist.ac.kr

Project 관련 homepagehttp://sonata.kaist.ac.kr/course/ideclab

Project 를 위한 다음 강의 (1/21) 의 시간 조정이 있습니다 .강의 시간은 1/14 일에 정하겠습니다 .