Korea Test Conference

Jin-Soo Ko

(jin-soo.ko@teradyne.com)

June 25, 2014

ATE Debugging tool

효율적 테스트 / 디버그를 위한 디자인과 테스트 업체의 연구 방안

SW AND DEBUG TOOLS MAGNIFY NEEDLE!

MARKET TRENDS DRIVING ATE SW TOOL ROADMAP

3

Test EngineerShorter Time To Market

Less Than 15 Days Si to Samples

Functional IntegrationLarge Test ListsCollaborative Development

Quality<100 DPM For Mobility Devices

Complex FlowsIncreased Device

Configuration and Repair

COT PressuresHigher Multisite, Concurrent

Test, Datalog overhead

Faster Time To Volume

>1M devices within 2 Months

IG-XL: #1 IN ATE SOFTWARE - WHY NEED GOOD SW-DEBUG TOOL?

30% faster test program development time Native MultiSite, Program Modularity, Templates, “Debug in the Zone”, Complete tool set, ESA

Optimal throughput early in the product ramp resulting in faster time to profits.

IG-XL’s Pure Parallel, Native MultiSite, Background DSP, TrueCT, Timelines

Faster time to entitled yield Scan fail capture throughput, APIs to design environments, Protocol Aware

Better quality programs that result in fewer RMAs and defect escapes

VBT, Spike-Check tool, Simulation Tools, IG-Review, IG-Diff

New users become self sufficient faster Easy to learn programming language, DUT Centric use model, Template programming

IG-XL has been ranked #1 in ATE Software for the last four years by VLSI Customer Satisfaction Research Survey

DESIGN TEST DESIGN LOOPD

esig

n

Sim

ulat

ion

On-Tester Debug/ Characterization (hours/minutes)

• Timing/Levels• Mixed Signal• Repeatability• Correlation

Pattern & Test program. Gen.

events

transactions

ATPG

STDF

“off tester” tools

“on tester” tools

Failure Analysis / Yield Enhancement

EDA-based Pattern Viewer• Simultaneous display of EDA and tester

information

• Diagnose Physical Device Faults

5

HOW ARE SCAN FAILURES RESOLVED NOW?

• Tools are not integrated

• Information is lost or delayed between Test / Design / FA

• Investigations can take weeks to complete

6

THE TESTER IS ONLY PART OF A BIGGER PROCESS

Advanced ATE SW tools for Time to Market

OPENEDA: CONNECTING ATE SW (IG-XL) TO THE ENTIRE DESIGN AND TEST ENVIRONMENT

Design and Test Development:

EDA LinksTest Program GenerationFeedback To SimulationTest-Design IntegrationYield LearningData Analysis

High Volume Manufacturing:

Test Floor ManagementFactory Data ManagementAdaptive TestPart Average TestingOperator InterfacesPeripherals and HandlersYield MonitoringOEE

8

Program Instruments with Psets (All

instruments in parallel)

Select Source Signal

Trigger measurements at precise times

Reprogram Instruments with PSets

Select different Source Signal

Trigger measurements at precise times

Automatic data move and processing

-3dB

Automatic data move and processing

…and so on…

Since the Engineer can control all the events from one pattern, we have Pattern Oriented Programming (POP)

Exact Timeline

WHAT THE TEST ENGINEER SEES…. POP

9

CONCURRENT TEST TOOL

TestsBlock A

TestsBlock BTests

Block CTestsBlock D

TestsBlock E

Initial

TestsBlock F

TestTime

Full FunctionalTest

Concurrent Test FlowSerial Test Flow

TestsBlock A

TestsBlock B

TestsBlock C

TestsBlock D

TestsBlock E

TestsBlock F

TestTime

Initial

Full FunctionalTest

Development Challenges• Common bus/pins• Shared test resources• Flow manipulation• Multi-site implementation• Adaptive test & Retest• Debug tools

10

Timeline viewer

MULTI-SHEET USE MODEL

• Separate test code & data for each sub program

• Tied together at the Job List Sheet

• IG-XL 8.10.11 completes the Multi-Sheet Model

Sub-Program B

Sub-Program A

• Enabler for independent development• Reduces time to integrate

= no more manual merging of sub programs

RF TOOLS- LTE-A TX SIGNAL DEBUG TOOL AND RESULT

IG-XL 7.30

• ESA 2.0 3GPP LTE TD-SCDMA 802.11n 4x4 MIMO VSA 10.01• 1 port vector• Power de-embedding• Signal sheet support• Smith charting

IG-XL 7.40

• ESA 2.5 3GPP LTE Update Bluetooth 3.0 VSA 11

IG-XL 8.00.01

• ESA 3.0 LTE 8.9 VSA12

IG-XL 8.10

• ESA 3.5 LTE-A (R10) 802.11ac VSA 14

IG-XL 8.20

• ESA 4.0 LTE-A (100MHz) 802.11ac (160MHz) 802.11ac (80+80) BT 4.0 (LE) VSA 16• 90% reduction in VSA

instance creation times

PROTOCOL AWARE

“Stored Response” ATE Complex Device Architecture

Tries to Test

Integrated Mobile Device

CPU

DRAMI/F

FlashI/F

JTAGI/F

USBI/F

DSPBB

Proc

Power MgmtFunctions

Audio / BBFunctions GPS

3G RF

WiFi

FM/TVWrite.jtag ( ADDR: 04h, DATA: 55h)Read.jtag (ADDR: 0Ah, DATA read_var)

Protocol Definition Editor For defining and modifying protocols

Protocol StudioFor online debug of protocol transactions

• Transaction results

• Debug displays

• Data capture setups

• Module management

• Port Properties