Huy chương,đia chỉ in huy chương thể thao,làm huy chương lưu niệm,nhận cung cấp huy chương nhôm
Julio C. G. Pimentel (pimentel@ieee) Hoang Le-Huy ([email protected])
description
Transcript of Julio C. G. Pimentel (pimentel@ieee) Hoang Le-Huy ([email protected])
Pimentel 1 P225/MAPLD 2004
Julio C. G. Pimentel ([email protected])Julio C. G. Pimentel ([email protected])Hoang Le-Huy ([email protected])Hoang Le-Huy ([email protected])
Gilbert Sybille ([email protected])Gilbert Sybille ([email protected])
LEEPCI - Laboratory of Electro-technology, Power Electronics and LEEPCI - Laboratory of Electro-technology, Power Electronics and Industrial ControlIndustrial Control
An FPGA-Based Real Time Power An FPGA-Based Real Time Power System Simulator for Power System Simulator for Power
ElectronicsElectronics
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Plan
Introduction Proposed Approach
Implementation Flow
Library of Components
Experimental Results
Conclusion
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Introduction
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Applications Power system stability analysis High frequency switched converters High frequency motion control
applications: Industrial machines Hybrid vehicles
Many more …
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Evolution of Real Time Power System Evolution of Real Time Power System SimulatorsSimulators
Continue Time ModelsContinue Time ModelsAmplifiers and passive Amplifiers and passive devicesdevicesReduced scale modelsReduced scale models
Transient Network Transient Network Analyzers (Analyzers (1970)1970)
HybridsHybrids
Digital ComputersDigital Computers(1990)(1990)
Discrete Time ModelsDiscrete Time ModelsParallel processorsParallel processorsMatrix RepresentationMatrix RepresentationInteractive Numeric Interactive Numeric Methods (algorithm)Methods (algorithm)
Proposed ApproachProposed Approach
Hardware EmulationHardware EmulationFPGAs + VHDLFPGAs + VHDLDSP or DSP or ProcessorProcessor
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Proposed Approach
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General ArchitectureGeneral Architecture
Decouple the electrical network in two parts:Decouple the electrical network in two parts:1.1. Linear part - RLC network is modelled as a Linear part - RLC network is modelled as a
matrix and processed by a microprocessormatrix and processed by a microprocessor2.2. Nonlinear part – nonlinear devices are Nonlinear part – nonlinear devices are
modelled as VHDL sub-circuits and processed modelled as VHDL sub-circuits and processed in the FPGAin the FPGA
Voltage and currents calculated by each part are Voltage and currents calculated by each part are exchanged at the end of each time stepexchanged at the end of each time step
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Data Flow Processing Model The sub-circuits are interconnected through their
input and output ports The inputs of a sub-circuit can only change at the
end of a time step The outputs of a sub-circuit only depends on its
inputs At the end of a time step the sub-circuit transfers
its calculated voltages and currents to the next sub-circuit
The sub-circuits are modelled in VHDL and implemented in a FPGA
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The synchronization ProblemThe synchronization Problem The sub-circuits I/O The sub-circuits I/O
signals can be: signals can be: – Control signals: CLK, Control signals: CLK,
RST, EN, STC, EOC RST, EN, STC, EOC and REGand REG
– Voltages and Voltages and currents – fixed currents – fixed point integerpoint integer
– Logical signals: Logical signals: carry On/OFF carry On/OFF information (PWM information (PWM outputs, outputs,
RSTCLK
Voltages
ENSTCEOCReg
LogicalSignals
Sub
CircuitCurrentsVoltages
Currents
LogicalSignals
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The synchronization Problem (cnt’d)The synchronization Problem (cnt’d)
RSTCLK
EOC1
EOC2
EOCn
Master
State
Machine
The control signals are:The control signals are:– Generated by a master state Generated by a master state
machine that synchronizes the machine that synchronizes the whole systemwhole system
– Sent to all VHDL sub-circuitsSent to all VHDL sub-circuits The SM controls:The SM controls:
– Initialization - Stability Initialization - Stability depends a lot on the depends a lot on the initialization strategyinitialization strategy
– SequencingSequencing1.1. Send data to/from DACSend data to/from DAC2.2. Send data to/from uPSend data to/from uP3.3. Process dataProcess data
EN
STC_l
STC_nl
REG_l
REG_nl
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I(t-1)Vb(t-1)
Z-1
Z-1
Decoupling StrategyDecoupling Strategy
Decouple the linear and nonlinear parts by Decouple the linear and nonlinear parts by introducing a Voltage-Current pair introducing a Voltage-Current pair => reduce the size of the problem=> reduce the size of the problem
Problem: the value of I et Vb used in each Problem: the value of I et Vb used in each part are delayed by one time step part are delayed by one time step => system may become => system may become unstableunstable
?
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Decoupling Strategy (cnt’d)Decoupling Strategy (cnt’d)
?
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Decoupling Strategy (in parallel)
Sources Nonlinear
linear
Z-1Z-1
AC, DC,Sin, Pulse,Step, etc.
Diode,Thyristor,MOSFET,Control, etc.
State Space Model [A, B, C, D]
VHDL
ALGORITHM
Total: 2 time step delay
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Decoupling Strategy (in series)
Total: ONLY 1 time step delay (more stable)
Sources Nonlinear
linear
Z-1
AC, DC,Pulse,Step, etc.
Diode,Thyristor,MOSFET,Control, etc.
State Space Model [A, B, C, D]
VHDL
ALGORITHM
ZeroDelay
The simulation of the nonlinear part takes much less than 1 us
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Implementation Flow
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Implementation FlowImplementation Flow
Translate PSBTo
VHDL
Elaboration
Synthesis
PlacementRouting
FPGA Programming
PSB/Matlab Schematic
Library of ComponentsFor DRTPSS
VendorLibrary
FPGA Design Flow
DRTPSSSimulator
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Library of parameter-driven components
Sources: DC, ramp, sinus, etc. 1and 3PWM modulators PI and PID controllers DQ-ABC and ABC-DQ converters Components (diode, MOST, Thyristor,
etc.) Digital filters and CORDIC D/A converters
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Sinusoidal sourceSinusoidal source
n, nc, VMax
Sin_1Ø
clkclock
outn
Freqn
en
0 10 20 30-1
-0.5
0
0.5
1
Résolution: 8 bits x Entrée: b'00001111Fréquence: 78.7 Hz
Time ( ms )
Vsi
n (V
)
0 100 200 300 400 500-80
-60
-40
-20
0
Résolution: 8 bits x Entrée: b'00001111Fréquence: 78.7 Hz
Frequency (Hz)
Vsi
n (d
Bv)
78.7 Hz
The sinusoidal source (example):The sinusoidal source (example):Can generate a sinus with 16-bit resolution (amplitude Can generate a sinus with 16-bit resolution (amplitude and phase)and phase)Approximation: series of Taylor (can also use a lookup Approximation: series of Taylor (can also use a lookup table):table):
Implemented using multiply-accumulate operationsImplemented using multiply-accumulate operationsDistortion < 1%Distortion < 1%
XXXXXXSin 5432 8003.14468.53252.5020264.01406.3)(
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PWM ModulatorPWM Modulator
The PWM modulator (example)The PWM modulator (example)•Resolution: ex.: 8 bitsResolution: ex.: 8 bits•frequency: 2.99 Mhzfrequency: 2.99 Mhz•Modulation factor: 25%Modulation factor: 25%
n
PWM_1Ø
en
ld
clkclock
outinputn
load
enable
0 0.2 0.4 0.6 0.8 1
x 10-4
0
1
2
3
4
Résolution: 8 bits - Entrée: b'01000000Fréquence: 46.7 kHz - Rapport cyclique = 25%
Temps (s)
Vpw
m (V
)
0 1 2 3 4 5 6 7
x 104
-60
-40
-20
0
Résolution: 8 bi ts - E ntrée: b '01000000Fréquence: 46.7 kHz - Rapport cyclique = 25%
Fréquence (Hz)
Vp
wm
(dB
)
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33 sinusoidal PWM Modulator sinusoidal PWM Modulator
clock
out_An
Freqn
out_Bn
out_Cn
n, nc, VMax
Sin_3Ø
clk
en
0 50 100 150 200 250 300 350 400
0
2
4Résolution: 8 bits
Vpw
m a (V)
0 50 100 150 200 250 300 350 400
0
2
4
Vpw
m b (V)
0 50 100 150 200 250 300 350 400-2
0
2
4
Time ( µs )
Vpw
mc (V
)
0 10 20 30-0 .5
0
0 .5
Ré so lution: 8 b its x E ntrée : b '000 01111Fré quence: 7 8 .7 Hz
Time ( m s )
Vs
in (
V)
END Q
CR
PWM_1Ø
EnLdclk
out_A
n
END Q
CR
PWM_1Ø
EnLdclk
out_B
n
END Q
CR
PWM_1Ø
EnLdclk
out_C
n
clock
Sin_1Ø
clk
nFreq
n
State machine
clk
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Experimental Results
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Ex1: Full Wave Rectifier
PSB
FPG
ASi
m
•FPGASim – proposed simulator (real FPGASim – proposed simulator (real time simulator)time simulator)
•PSB – Power System Blockset of Matlab PSB – Power System Blockset of Matlab (non real time simulator)(non real time simulator)
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Ex2: Thyristor Rectifier
FPG
ASi
m
PSB
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Ex3: Effect of Transitory on a DC-DC Buck Converter
FPG
ASi
m
PSB
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Ex4: DC-DC Buck Converter with PI Controller
L1=20mHR=20C=30uF
Kp=0.1Ki=4
FPG
ASi
m
PSB
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Ex5: Three-phase DC-AC PWM Converter
FPG
ASi
m
PSB
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Ex6: 50Hz – 60Hz Cicloconverter
Vpeak=150V Ls=100uH
Vc=100uF
Rl=10Ohm Ll=100mH
FPG
ASi
m
PSB
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Conclusion
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FPGA Used Xilinx 2VP30 Virtex II PRO
Logic Cells (1): 30,816 Slices: 13,696 18 X 18 Bit Multiplier Blocks: 136 Maximum User I/O Pads: 644 PowerPC Processor Blocks: 2
(1) Logic Cell = (1) 4-input LUT + (1)FF + Carry Logic
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Summary (nonlinear part only)Fclk max
Time step
# of gates
# of FFPs
usage
Ex4 58 MHz 0.17us 160K 500 9%
Ex5 55 MHz 0.18 us 370K 1300 20%
Ex6 60 MHz 0.17 us 500K 1700 27%
NOTE: 1) implemented on a Xilinx 2VP30 Virtex II PRO FPGA 2) results taken after placement and routing
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Conclusion Proposed a new approach to implement
DRTPSSs based on programmable hardware and HDL languages
The proposed simulator produces results comparable to those obtained with the PSB/Matlab from Mathworks
The initial results show that the technique has the potential to create a breakthrough in DRTPSS and set a new level of performance for these simulation tools