IP JESD204 DA38J84 IOT Report - Intel...IOT Report 1.0 27 September 2013 PKO Rev. Change No. Release...

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IPC-JESD204-B DAC38J84 IOT Report

1.0 27 September 2013 PKO

Rev. Change No. Release Date Change Information Author

Page No: 1 of 20 Approved by

Head of IPC Group

of 20 IPC-JESD204-B DAC38J84IOT Report V 1.0 Release Date: 9/28/2013

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1.0 First Release 27.09.2013 Initial Release PKO

Rev Change No. Release date Change Information Author

Revision History

Document No: MTIX-XXXXXX Title: IPC-JESD204-B DAC38J84IOT Report






Table of Contents

1 INTRODUCTION ..................................................................................................................................................... 5

2 SCOPE ................................................................................................................................................................... 5

3 APPLICABLE AND REFERENCE DOCUMENTS .......................................................................................................... 5

4 ACRONYMS AND DEFINITIONS .............................................................................................................................. 5

5 ARRIA V GT – DAC38J84 HARDWARE IOT SETUP.................................................................................................... 7

5.1 ARRIA V GT DAC38J84 HARDWARE TEST BED COMPONENTS .......................................................................................... 7

5.2 ARRIA V GT DAC38J84 HARDWARE TEST BED CLOCKING ............................................................................................... 7

5.3 ARRIA V GT DAC38J84 HARDWARE TEST BED FPGA2 PIN OUT ...................................................................................... 8

6 STRATIX V GX – DAC38J84 HARDWARE IOT SETUP .............................................................................................. 10

6.1 STRATIX V GX DAC38J84 HARDWARE TEST BED COMPONENTS ..................................................................................... 10

6.2 STRATIX V GX DAC38J84 HARDWARE TEST BED CLOCKING ........................................................................................... 11

6.3 STRATIX V GX DAC38J84 HARDWARE TEST BED FPGA1 PIN OUT ................................................................................. 11

7 TEST DESCRIPTION AND RESULTS ........................................................................................................................ 14

7.1 DAC38J84 HARDWARE TEST BED VHDL SETUP ........................................................................................................... 14

7.2 DAC38J84 HARDWARE TEST BED NIOS SOFTWARE ..................................................................................................... 15

7.3 DEVICE CONFIGURATION OVERVIEW ............................................................................................................................ 16

7.4 TEST CASES OVERVIEW .............................................................................................................................................. 17

7.5 TEST RESULTS ........................................................................................................................................................... 18

7.6 TEST RESULTS INTERPRETATION ................................................................................................................................... 18

7.7 QUICK SETUP GUIDE .................................................................................................................................................. 19

8 DISCLAIMER ........................................................................................................................................................ 20






List of Figures

Figure 1DAC38J84 Hardware test bed Components ........................................................................... 7

Figure 2 DAC38J84 Hardware test bed Components ........................................................................ 10

Figure 3 HW test bed diagram ........................................................................................................... 14

Figure 4 DAC GUI showing no errors.................................................................................................. 19

List of Tables

Table 1 Pin Out for FPGA2 of the IOT test bed .................................................................................... 9

Table 2 Pin Out for FPGA1 of the IOT test bed .................................................................................. 13

Table 3 Relevant software commands for the DAC38J84 IOT test bed ........................................... 15

Table 4 DAC38J84 tested device configurations ............................................................................... 16

Table 5 DAC38J84 Test Results ........................................................................................................... 18






1 Introduction The purpose of this document is to provide the reader with detailed understanding of how the Inter-Operability Testing of the JESD204B receive and transmit IP cores against various hardware devices has been carried out.

Each IOT setup shares a significant number of commonalities – which is the rationale behind incorporating them into a single document.

From an application point of view, the receiver and transmitter are totally separate cores – a project may utilize only one or several instances of each. However for sake of design simplicity a common RX+TX setup has been selected for the DUT.

2 Scope This document is intended for a technical audience (engineering, marketing, customer support) with an understanding on serial interface protocols and RF systems. Engineering background on digital design is required.

The scope of this document is to present the hardware test bed setup and components, the test methodology and test cases as well as the test results. The scope is to provide integration engineers with sufficient knowledge to adapt and verify the cores in a customized environment and application.

3 Applicable and Reference Documents

Document ID Title

JESD204B.01 Serial Interface for Data Converters (Revision of JESD204B, July 2011). Date January 2012

Avalon Spec Avalon Interface Specification (rev. 13 May 2013). Altera (www.altera.com/literature/manual/mnl_avalon_spec.pdf)

4 Acronyms and Definitions

A/D = Analog to Digital

ASIC = Application Specific Integrated Circuit

ASSP = Application Specific Standard Product






CF = Control bits per frame

CS = Control Bits per sample

D/A = Digital to Analog

DC = Direct Current

F = Number of Octects

FPGA = Field Programmable Gate Array

HD = High Density

IC = Integrated Circuit

IP = Intellectual Property

L = Number of Lanes

M = Number of Converters

MCDA-ML = Multiple-Converter Device Alignment, Multiple-Lanes

N = Sample Resolution

N’ = Sample Envelope

RTL = Register Transfer Logic

S = Samples per converter

SCR = Scrambler

VHDL = VHSIC Hardware Description Language

Names Convention:

Generics Names = CAPITAL

Registers Names = CAPITAL BOLD

Signal Names = italic bold






5 Arria V GT – DAC38J84 Hardware IOT Setup

5.1 Arria V GT DAC38J84 Hardware Test Bed Components

The hardware test bed consists of the following items:

1. Arria V GT FPGA Development Kit (www.altera.com/products/devkits/altera/kit-arria-v-gt.html)

2. DAC38J84 FMC Evaluation Card (Engineering sample)

3. USB cable x2, Power adapter x2, SMA cables x4

The IOT is based on visual feedback of the test pattern visible on the outputs of the DAC connected to an oscilloscope. The analog outputs of the DAC card are connected to the oscilloscope via SMA cables.

Figure 1DAC38J84 Hardware test bed Components

5.2 Arria V GT DAC38J84 Hardware Test Bed Clocking

The clock is generated on the LMK device on the DAC and provided to the Arria V GT evaluation card via FMC. The MTI JESD204B IP Cores utilize a 40bit serdes interface and comparing to DAC38J84 which uses only a 20bit serdes interface should be clocked at half the frequency. The serdes expects the frequency to be 1/20th of the line rate 250 MHz for 5G. The device clock is further divided by a factor of 2 inside the FPGA having a 125 MHz device clock for a 5G line rate.

The SYSREF pulse is also generated in the LMK device on the DAC card and propagated to the MTI JESD204B IPC over the FMC connector.

http://www.altera.com/products/devkits/altera/kit-arria-v-gt.html






5.3 Arria V GT DAC38J84 Hardware Test Bed FPGA2 Pin Out

Node Name Direction Location I/O Standard

clkina_50 Input PIN_AP34 1.8 V

cpu1_resetn Input PIN_L6 2.5 V

fmc_clk_in_GTX Input PIN_AB9 LVDS

fmc_clk_in_GTX(n) Input PIN_AB8 LVDS

fmc_led_jesdsync Output PIN_AU13 2.5 V (default)

fmc_rx_0 Input PIN_AE1 2.5-V PCML

fmc_rx_0(n) Input PIN_AE2 2.5-V PCML

fmc_rx_1 Input PIN_AA1 2.5-V PCML

fmc_rx_1(n) Input PIN_AA2 2.5-V PCML

fmc_rx_2 Input PIN_U1 2.5-V PCML

fmc_rx_2(n) Input PIN_U2 2.5-V PCML

fmc_rx_3 Input PIN_R1 2.5-V PCML

fmc_rx_3(n) Input PIN_R2 2.5-V PCML

fmc_spare_led_1 Output PIN_AN7 2.5 V (default)

fmc_spare_led_2 Output PIN_AG17 2.5 V (default)

fmc_sync Output PIN_AN19 1.8V

fmc_sysref Output PIN_AW15 LVDS

fmc_sysref(n) Output PIN_AW14 LVDS

fmc_tx_0 Output PIN_AD3 1.5-V PCML

fmc_tx_0(n) Output PIN_AD4 1.5-V PCML

fmc_tx_1 Output PIN_Y3 1.5-V PCML

fmc_tx_1(n) Output PIN_Y4 1.5-V PCML

fmc_tx_2 Output PIN_T3 1.5-V PCML






fmc_tx_2(n) Output PIN_T4 1.5-V PCML

fmc_tx_3 Output PIN_P3 1.5-V PCML

fmc_tx_3(n) Output PIN_P4 1.5-V PCML

user1_led_g[0] Output PIN_M19 2.5 V (default)

user1_led_g[1] Output PIN_L19 2.5 V (default)

user1_led_g[2] Output PIN_K19 2.5 V (default)

user1_led_g[3] Output PIN_J19 2.5 V (default)

user1_led_g[4] Output PIN_K20 2.5 V (default)

user1_led_g[5] Output PIN_J20 2.5 V (default)

user1_led_g[6] Output PIN_T20 2.5 V (default)

user1_led_g[7] Output PIN_R20 2.5 V (default)

Table 1 Pin Out for FPGA2 of the IOT test bed






6 Stratix V GX – DAC38J84 Hardware IOT Setup

6.1 Stratix V GX DAC38J84 Hardware Test Bed Components

The hardware test bed consists of the following items:

1. Stratix V GX FPGA Dev. Kit (http://www.altera.com/products/devkits/altera/kit-stratix-v-advanced.html)

2. DAC38J84 FMC Evaluation Card (Engineering sample)

3. HSMC Debug Header Breakout Board (provided with the FPGA EVM)

4. SMA cables x4, USB cable x2, Power adapter x2

5. Pin connecting wire

The IOT is based on visual feedback of the test pattern visible on the outputs of the DAC connected to an oscilloscope. The analog outputs of the DAC card are connected to the oscilloscope via SMA cables.

Due to the lack of appropriate connection on the pins of the FMC an additional wire must be connected to enable FPGA 1 to receive the sync signal from the DAC. This is done by connecting pin 1 of J21 on the DAC card to pin 3 of J1 connector on the HSMC Debug Header Breakout Board. FPGA 2 will route this signal back to FPGA 1.

Figure 2 DAC38J84 Hardware test bed Components

http://www.altera.com/products/devkits/altera/kit-stratix-v-advanced.html






6.2 Stratix V GX DAC38J84 Hardware Test Bed Clocking

The clock is generated on the LMK device on the DAC and provided to the Stratix V GX evaluation card via FMC. The MTI JESD204B IP Cores utilize a 40bit serdes interface and comparing to DAC38J84 which uses only a 20bit serdes interface should be clocked at half the frequency. The serdes expects the frequency to be 1/20th of the line rate – 500 MHz for 10G. The device clock is further divided by a factor of 2 inside the FPGA having a 250 MHz device clock for a 10G line rate.

The SYSREF pulse is also generated in the LMK device on the DAC card and propagated to the MTI JESD204B IPC over the FMC connector.

6.3 Stratix V GX DAC38J84 Hardware Test Bed FPGA1 Pin Out

Node Name Direction Location I/O Standard

clkina_50 Input PIN_R25 1.8 V

cpu1_resetn Input PIN_AY33 2.5 V

fmc_clk_in_GTX Input PIN_AB39 LVDS

fmc_clk_in_GTX(n) Input PIN_AB40 LVDS

fmc_led_jesdsync Output PIN_V12 2.5 V (default)

fmc_rx_0 Input PIN_AB43 2.5-V PCML

fmc_rx_0(n) Input PIN_AB44 2.5-V PCML

fmc_rx_1 Input PIN_Y43 2.5-V PCML

fmc_rx_1(n) Input PIN_T44 2.5-V PCML

fmc_rx_2 Input PIN_V43 2.5-V PCML

fmc_rx_2(n) Input PIN_V44 2.5-V PCML

fmc_rx_3 Input PIN_T43 2.5-V PCML

fmc_rx_3(n) Input PIN_T44 2.5-V PCML

fmc_rx_4 Input PIN_M43 2.5-V PCML

fmc_rx_4(n) Input PIN_M44 2.5-V PCML

fmc_rx_5 Input PIN_K43 2.5-V PCML

fmc_rx_5(n) Input PIN_K44 2.5-V PCML






fmc_rx_6 Input PIN_H43 2.5-V PCML

fmc_rx_6(n) Input PIN_H44 2.5-V PCML

fmc_rx_7 Input PIN_F43 2.5-V PCML

fmc_rx_7(n) Input PIN_F44 2.5-V PCML

fmc_spare_led_1 Output PIN_K10 2.5 V (default)

fmc_spare_led_2 Output PIN_K9 2.5 V (default)

fmc_sync Output PIN_AT8 2.5 V (default)

fmc_sysref Output PIN_J10 LVDS

fmc_sysref(n) Output PIN_H10 LVDS

fmc_tx_0 Output PIN_W41 1.5-V PCML

fmc_tx_0(n) Output PIN_W42 1.5-V PCML

fmc_tx_1 Output PIN_U41 1.5-V PCML

fmc_tx_1(n) Output PIN_U42 1.5-V PCML

fmc_tx_2 Output PIN_R41 1.5-V PCML

fmc_tx_2(n) Output PIN_R42 1.5-V PCML

fmc_tx_3 Output PIN_N41 1.5-V PCML

fmc_tx_3(n) Output PIN_N42 1.5-V PCML

fmc_tx_4 Output PIN_J41 1.5-V PCML

fmc_tx_4(n) Output PIN_J42 1.5-V PCML

fmc_tx_5 Output PIN_K39 1.5-V PCML

fmc_tx_5(n) Output PIN_K40 1.5-V PCML

fmc_tx_6 Output PIN_H39 1.5-V PCML

fmc_tx_6(n) Output PIN_H40 1.5-V PCML

fmc_tx_7 Output PIN_G41 1.5-V PCML

fmc_tx_7(n) Output PIN_G42 1.5-V PCML

user1_led_g[0] Output PIN_H25 2.5 V (default)






user1_led_g[1] Output PIN_P23 2.5 V (default)

user1_led_g[2] Output PIN_AH19 2.5 V (default)

user1_led_g[3] Output PIN_AT11 2.5 V (default)

user1_led_g[4] Output PIN_G23 2.5 V (default)

user1_led_g[5] Output PIN_AY9 2.5 V (default)

user1_led_g[6] Output PIN_H22 2.5 V (default)

user1_led_g[7] Output PIN_BB8 2.5 V (default)

Table 2 Pin Out for FPGA1 of the IOT test bed






7 Test description and results

7.1 DAC38J84 Hardware Test Bed VHDL Setup

The test bed consist of a top level entity “jesd204b_eval_DAC38J84_top” which instantiates the nios processor and the core test bed “jesd204b_eval_core”, and also routes the two blocks together and to the In Out interfaces (clocks, HSMC, FMC, LEDs and pushbuttons).

The “jesd204b_eval_core” module instantiates the RX and TX IP Cores, they can be used back to back but in the DAC38J84 test bed scenario only the TX core is utilized. It also instantiates the serdes modules and the required reset and reconfiguration blocks accompanying them. This module also controls the generation incremental test data pattern.

The RX and TX cores do not include serdes modules but provide a multiple of 10bit wide interface to them. The width of this interface is controlled with a generic NO_SERDES_WORDS. In this test bed a 40 bit interface is used for the serdes. The IP cores also include a CPU interface to which the NIOS processor is connected allowing reading and writing of the internal register values during the CORE operation.

CPU IF

Sample IF

CPU IF

Sample IF

CPU IF

SerD

es P

HY’

s

USB JTAG interface

PLL /2

OSC50 MHz

SerDesloopback

CLOCK

NIO

S C

PU

JESD204BTX IP-core

SYSREF

Reset

Reset

Reset

Dat

a G

ener

atio

n

and

Val

idat

ion

JESD204BRX IP-core

Lane #0 DAC #0

DAC #1DAC38J84

DAC #2

DAC #3

Lane #1Lane #2Lane #3Lane #4Lane #5Lane #6Lane #7

SerD

es P

HY’

s

Figure 3 HW test bed diagram






7.2 DAC38J84 Hardware Test Bed NIOS Software

The software running on the NIOS processor plays key role in the IOT test bed. It has access to the CPU interfaces of the TX and RX cores as well as the test bed core module. It is able to reconfigure on the fly the various operating parameters of the RX core. The DAC38J84 device however must be configured manually through the GUI interface. This allows the software to control the test parameters, device configurations, and run times. It is also able to read out the test results from the data validator error indicators as well as the RX core error counters.

The NIOS software provides a console based interface allowing the user to initialize and monitor the automated test sequence as well as the IP core and serdes status. It provides direct access to the IP core and test bed registers. This allows full control of the IP core.

Command Description

Main Menu

c Rx module status (enabled, scrambling)

d Rx module configuration (enable, scrambling)

k, g Run full DAC38J84 IOT test sequence (k is used for LMF 442, g for LMF 841)

r Read Write registers and SPI sub menu

t Evaluation test bed status (SerDes status, RX Error counters, Data Validators status)

y Evaluation test bed configuration (Resets, Serdes Loopback)

Register sub menu (r)

a Set the command address

v Set the value to write

r Read from address set by (a)

w Write value set in (v) to address set by (a)

Table 3 Relevant software commands for the DAC38J84 IOT test bed






7.3 Device Configuration Overview

The DAC38J84 evaluation card consists of a DAC38J84 chip each sending data to up to 4 converters over 1 to 8 lanes.

The following device configurations have been tested:

# L M F K HD SCR S N N’ CF CS

1 4 4 2 10 0 0 1 16 16 0 0

for four lanes carrying data to four converters

2 8 4 1 10 1 0 1 16 16 0 0

for eight lanes carrying data to four converters

Table 4 DAC38J84 tested device configurations

To configure the TX ip for configuration #1 use the ‘k’ nios software command. To run configuration #2 use the ‘g’ command.






7.4 Test Cases Overview

The following test case has been used for the IOT.

1. Incremental Pattern test – A test pattern where each consecutive sample is an increment of the

previous one. This test can be configured in the following manner:

On the DAC38J84:

a. Use the provided configuration scripts with the DAC GUI to configure the device

On the MTI RX IPC test bed:

b. Use the nios ‘k’ or ‘g’ command to configure the IP core. The TX data generator defaults

to Incremental Pattern so there is no generator configuration necessary.

c. Test results can be observed on the oscilloscope connected to the DAC

Note: These test case configuration sequences assume the DAC38J84 and MTI JESD204B RX modules have

been configured with the correct and matching L,M,F,N,N’,K,SCR,S,CS,HD,CF values.






7.5 Test Results

The test results can be observed with an oscilloscope. Because the DAC device lacks incremental test pattern validators the scope can be used to observe if a correct data sequence is received and properly converted into the analog domain.

Table 5 DAC38J84 Test Results

The image shows the incremental data pattern mixed with a sine wave.

7.6 Test Results Interpretation

Tests are considered successful if the proper data pattern is seen on the scope and the DAC device does not report errors for the used lanes in the GUI.






Figure 4 DAC GUI showing no errors

7.7 Quick Setup Guide

This chapter describes the necessary steps required to reproduce the test results.

1) Synthesize the DAC38J84 IPC test bed. This step will require generation of the NIOS core in QSYS.

Or use the provided .sof file

2) Build the IOT HW test bed from the components listed in the beginning of this chapter

3) Compile the NIOS software project

4) Upload the SOF files (on stratix V for FPGA1 and FPGA2, on Arria V just the FPGA2) and run the NIOS software

5) The default configuration is prepared for quick IOT testing, use the “k” command to start the IOT for LMF 442. If running the LMF841 at 10G configuration, use the “g” command to start the IOT.

To interpret the results, check the DAC GUI and oscilloscope waveforms.






8 Disclaimer

Copyright

Microelectronics Technology Inc. All rights reserved

Disclaimer Liability

Contents herein are current as of the date of publication. MTI reserves the right to change the content without prior notice. In no event shall MTI be liable for any damages resulting from loss of data, loss of use, or loss of profits and MTI further disclaims any and all liability for indirect, incidental, special, consequential or other similar damages. This disclaimer of liability applies to products, publications and services during and after the warranty period. This publication may be verified at any time by contacting MTI’s Technical Assistance at [email protected]

mailto:[email protected]

IP JESD204 DA38J84 IOT Report - Intel...IOT Report 1.0 27 September 2013 PKO Rev. Change No. Release...

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