Introduction to IC Testing - 博九娱乐网络娱乐-博九娱乐网...
Transcript of Introduction to IC Testing - 博九娱乐网络娱乐-博九娱乐网...
Introduction to IC Testing
Testing Goals :.Improve the reliability
.Save money in manufacturing
Types of Tests(1) By testing purpose
. Characterization
. Production
. Burn –in . Incoming inspection
(2) By manufacturing level .wafer-in-process : on-line monitor .wafer : circuit probe (C.P.) . Package : final test (F.T.)
(3) By testing item. Functional. DC parameter. AC parameter
(4) By process technology . TTL . NMOS . CMOS . BiCOMS . GaAs . Others
(5) By device type
. Digital : uP ,Gate array,ASIC
. Memory : Sram, Dram, Rom
. Analog : Power IC
. Mixed-Mode : ADC,DAC,Telcom
. Others : CCD ,LCD,
Test Items(1) Functional test
. Truth table
. Algorithmic pattern generation
(2) DC parametric test .Open and shorts .Output drive/sink current (IOH,IOL) . Leakage . Power current . Standby current . Threshold levels( VIH,VIL)
(3) AC parametric test. Propagation delays. Setup and hold times. functional speed. Rise and fall times. Jitter
Terms that Apply to the DUT
Input pin : A device pin that acts as a buffer between external signals and the internal logic of deviceOutput pin : A device pin that acts as a buffer between the internal logic of a device and the external signalsTri-State : A device pin that acts as an output pin but has the added capability of turning off going to a high impedance statePower pin : A device pin that is connected to a power supply or ground
Terms that Apply to the Test System
PE card : Circuit used to supply input signals to the DUT and receive output signals from the DUT Drivers : Circuit on the PE card which supply logic 0 and logic 1 levels to the DUT Comparators : The circuitry located on the PE card which sense the logic 0 and logic 1 levels from the DUT
Signal : The wave shape of an input signalFormat supplied by the PE card driver
circuitry
PMU : The Precision Measurement Unit Which can , Force current measure voltage Force voltage measure current DPS : The Device Power Supply Which can , Force current measure voltage Force voltage measure current Supply voltage and current to the DUT
Negative current : Current flow from the DUT into the testerSource current : When an output pin is in the logic 1 state,it can supply current from the DUT to the tester Positive current : Current flow from the testerSink current : When an output pin is in the logic o state,it can accept current from the tester through the device to the ground
Test Cycle : The time duration of one test vector execution . The test cycle is based on the operating freqency of the DUT . 100ns=1/10MHZ ( SSE. L5710) Tester Channel : Circuitry on the PE card which applies and/or process voltage,current and timing for one DUT pin
Terms that Apply to Test parametersVCC : The supply voltage of a TTL deviceICC : The current consumed by the circuitry of a TTL deviceVDD : The supply voltage of a MOS deviceIDD : The current consumed by the circuitry of a MOS deviceIIH : Input Leakage High is the maximum amount of current that is allowed to flow into an input pin when a high voltage value is forced onto the pinIIL : Input Leakage Low is the maximum amount of current that is allowed to flow out of an input pin when a low voltage value is forced onto the pin
VOH : Voltage Out High is the voltage value produced by an output when given an logic 1
VOL : Voltage Out Low is the voltage value produced by an output when given an logic 0
IOH : Current Out High is the amount of current that an output must source when driving a logic 1
IOL : Current Out Low is the amount of current that an output must sink when driving a logic 0
DUT
INPUT
PIN
VDD
IIL leakage path
IIH leakage pathVSS= 0V
R ( ~ M ohm)
R ( ~ M ohm)
VSS
VDD
VDD
IIL
IIH
Actual Device Input Circuit ( IIL , IIH)
VSS
VDD
P MOS
N MOS
VDD
VSS= 0V
OFF
ONR
VDD
IOL
Actual Device Output Circuit ( VOL /IOL)
VOLOFFControl
( 1 )DUT
Output
Pin
ONIOL
E
SPEC.
IOL(MIN) =8.0MA
VOL(MAX)= 0.4V
R= E/I
E=VOL-VSS
R=0.4(V)/8(MA)
R=50 OHM(MAX)
VDD
VSS= 0V
OFF
ON
VDD
VOLOFFControl
( 1 )DUT
Output
Pin
ONIOL
E
SPEC.
IOL(MIN) =8.0MA
VOL(MAX)= 0.4V
R= E/I
E=VOL-VSS
R=0.4(V)/8(MA)
R=50 OHM(MAX)
0.4
50
R
0.32
40
0.48
60
When IOL= 8MA
The device output pins must sink at least a specified
amount of current and stay in the correct logic state
VDD
VSS= 0V
OFF
ONR
VDD(4.75V)
Actual Device Output Circuit ( VOH /IOH)
VOH
OFF
Control ( 0 ) DUT
Output
Pin
ON
IOHIOH
SPEC.
IOH(MIN) =-5.2MA
VOH(MAX)= 2.4V
R= E/I
E=VDD-VOH=4.75-2.4=2.35
R=2.35(V)/5.2(MA)
R=452 OHM(MAX)
E
TTL Output SpecVOH=2.4V at-2.6mAVOL=0.4V at 24.0mA
TTL Output SpecIIL=0.8mA at 0.4VIIH=150A at 2.4V
Device Fanout Capability
VOH =2.4V 2.6MA /150uA = 17.3 --> 17
VOL = 0.4 V24 MA /0.8 MA= 30
Open Drain/Source OutputsOPEN DRAIN : output can only drive low - they only sink current
OPEN SOURCE : output can only drive high - they only source current
VDD
Open Drain Output
VDD
Open Source Output
External Resistor
External Resistor
VDD
P MOS
N MOS
Standard CMOS CellOpen Drain Open Source
G
S
DG
D
S
How to test a open drain device
VDD
Open Drain Output
External Resistor
D
S
G
VCM(4V)
IOL(~ 1uA)
IOH
VOH (2v)
VOL(1v) X
GD
SGate X
1 0v (L)
0 VCM(4V) (H)
How to test a open Source device
VDD
Open Source Output
External Resistor
D
S
G
VCM(0.5V)
IOL
IOH(~ 1uA)VOH (2v)
VOL(1v)
X
GD
S
Gate X
0 VDD (H)
1 VCM(0.5V)(L)
VDD
VIH
VIL
F_Ctrl
D_Ctrl
IOL
IOH
VCM
L_Ctrl
VOH
VOL
Cmp_Hi
Cmp_Lo
PMU
L5710 Pin Electronics Block Diagram
DCL TO DUT
VIH
VIL
0/1
ON/OFF
VOL
VOH
VCC
GND
A B010101 HLHLHL
CMP_H
CMP_L
A B
0 11 0
/* AB */
* 0H *; * 1L *;
Truth table pattern
7404
Connect to DPS
Connect to GND
TPDhl TPDlh
A
B
TPDhl:Hi to Lo Propagation delay
TPDlh:Lo to Hi Propagation delay
VDD
CLK
DATA
IN
DATA
OUT
CLK
DATA IN
DATA OUT
2.0 V
0.8 V
2.0 V
0.8 V2.4 V0.4 V
100 ns
Valid Data in
(b)(a)
(a) set up time (b) hold time
1 0 1 0
LH L
L
CLK
DATA IN
DATA OUT
Output strobe
2.0 V
2.0 V0.8 V
0.8 V
0.4 V2.4 V
DATA IN
T0
0
T0
100ns
T0
200ns
T0
300ns
T0
400ns
2.0 V
0.8 V