Introduction to High Momentum Trigger in PHENIX Muon Arms RIKEN/RBRC Itaru Nakagawa 中川格 1.
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Transcript of Introduction to High Momentum Trigger in PHENIX Muon Arms RIKEN/RBRC Itaru Nakagawa 中川格 1.
1
Introduction to High Momentum Trigger in PHENIX Muon Arms
RIKEN/RBRCItaru Nakagawa中川格
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RHIC Accelerator Complex
2
Polarized Proton-Proton Operation at RHIC
2003 2004 2005 2006 2007 2008 2009 2010 2011 2012
200GeV
500GeV test production
test production
Forward (North&South) Muon Arms
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1. Muon Tracking Chambers– 3 stations of Cathode strip
chambers– Each station has multiple planes
for redundancy– Slow read out -> No trigger
2. Muon Identifier– 5 layers of Iarocci tubes in x and y– 80 cm of steel plate absorber
(total)– Provides trigger p > 2 GeV
St#1
St#2
St#3
MuTr
Same configuration in SouthSame configuration in South
MuID
B
Current Muon System
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Trigger Rate @ sqrt(s) = 200 GeV
100 GeV
€
rp
-Trigger Rate < 2 kHz
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Trigger Rate @ sqrt(s) = 500 GeV
250 GeV
€
rp
Rate ~ 9 MHz !!
Design Luminosity√s = 500 GeV σ=60mb L = 1.5x1032/cm2/s
Rejection Factor ~ 4500
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High Momentum Muon TriggerRun11 500 GeV Projection
New TriggerUpgrade
MuIDTrigger
Rate
9 MHz
90 kHz
σtot=60mb
L=1.5x1032cm-2s-1
BBCMuID Rejection PowerRP~100
Trigger UpgradeRP ~ 45
2 kHzPHENIX Band Width for Muon
Required Rejection Power
RPtot ~ 4500
1. High Rejection Power2. High Efficiency
W
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R1(a+b)
R3
r=3.40m
MuTr
(I) Three dedicated trigger RPC stations (CMS design):
R1(a,b): ~12mm in j, 4x θ pads
R2: ~5.4mm in j , 4x θ pads
R3: ~6.0mm in j, 4x θ pads
(Trigger only – offline segmentation higher)
NSF (Funded)
JSPS (Funded)
(II) MuTr front end electronicsUpgrade to allow LL1 information
Rejection ~12,000, beam background immune.
PHENIX Muon Trigger Upgrade
10
Momentum Dependent Trigger
B
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How New Trigger Works?Search for a Stiff
Track ONLINE!Slow MuTr could
trigger with INCOMING tracks
Fast RPC will reject them
PT Sensitive Trigger Does The Job
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W Trigger System
MuTrFEE
B
Trigger
Interaction Region Rack Room
Trigger events with straight track(e.g. Dstrip <= 1)
~10s
12
W Trigger System
MuTRGADTX
MuTRGMRG
MuTrFEE
B
2 planes
5%
95%
Trigger
Trigger
Interaction Region Rack Room
Optical
1.2Gbps
Amp/Discri.Transmit
DataMerge
MuTRG
Trigger events with straight track(e.g. Dstrip <= 1)
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W Trigger System
MuTRGADTX
MuTRGMRG
MuTrFEE
Resistive Plate Counter(RPC) (Φ segmented)
B
2 planes
5%
95%
Trigger
Trigger
Interaction Region Rack Room
Optical
1.2Gbps
Amp/Discri.Transmit
DataMerge
MuTRG
RPCFEE
RPC / MuTRG data arealso recorded on disk.
Trigger events with straight track(e.g. Dstrip <= 1)
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W Trigger System
MuTRGADTX
MuTRGMRG
Level 1TriggerBoard
MuTrFEE
Resistive Plate Counter(RPC) (Φ segmented)
B
2 planes
5%
95%
Trigger
Trigger
Trigger
Interaction Region Rack Room
Optical
1.2Gbps
Amp/Discri.Transmit
DataMerge
MuTRG
RPCFEE
Trigger events with straight track(e.g. Dstrip <= 1)
RPC / MuTRG data arealso recorded on disk.
15
W Trigger System
MuTRGADTX
MuTRGMRG
Level 1TriggerBoard
MuTrFEE
Resistive Plate Counter(RPC) (Φ segmented)
B
2 planes
5%
95%
Trigger
Trigger
Trigger
Interaction Region Rack Room
Optical
1.2Gbps
Amp/Discri.Transmit
DataMerge
MuTRG
RPCFEE
Trigger events with straight track(e.g. Dstrip <= 1)
RPC / MuTRG data arealso recorded on disk.
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W Trigger System (Final)
MuTRGADTX
MuTRGMRG
Level 1TriggerBoard
MuTrFEE
Resistive Plate Counter(RPC) (Φ segmented)
B
2 planes
5%
95%
Trigger
Trigger
Interaction Region Rack Room
Optical
1.2Gbps
Amp/Discri.Transmit
DataMerge
MuTRG
RPCFEE
Trigger events with straight track(e.g. Dstrip <= 1)
RPC / MuTRG data arealso recorded on disk.
DCM
DCMDCM
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MuTrig-FEE Developers
MuTRGADTX
MuTRGMRG
ADTX Board
Yoshi Fukao
Kohei Shoji
Kazuya Aoki
Katsuro Nakamura
Kenichi Karatsu
Tsutomu Mibe
MRG Board & DCMIF
Installation
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2008 North Arm
2009 South Arm
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New MuTRIG-FEE in North Arm
Before Install
2008 Install
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MuTrig-FEE ParametersFunction Options
Discriminator LED CFD
Threshold 0 ~ 100 mV (40,60mV)
Gap LOGIC OR AND
2 of 3 3 of 3LL1 Width 1 ~ 7 (2,3)
St1 St2 St3
2 of 3 AND
3 of 3 AND
No MuTRG-FEE
MuTRNon-Stereo Gaps
21
Resistive Plate Chamber(RPC)
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24
Hadron Absorber
25
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Neutron Absorber + RPC1
Yoshimitsu ImazuKentaro Watanabe
• How much neutron backgrounds?• How we can reduce these
background effect?
Recap clamp
MuTR-FEE Trigger Performance
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MuTRG System Run09 performance
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•MuID Algorithm•Track Matching w/ MuID•Timing cut w/ RPC•Track Matching w/ RPC•Neutron Backgrounds•etc ..
MuTrg-FEE x MuID
Better efficiency is the trade off of weak rejection power
LL1 Efficiencies
ADTX
MuTr
MRG
LL1
DCMIF DCM
GL1 Trigger
Identical hitinformation
€
Efficiency =# hits processed thru LL1
# hits processed thru DCMIF
Josh Perry’s Online Monitor
LL1 boards developed by U.Iowa
LL1 Trigger Emulator Online PlotLL1 efficiency
Stability Monitored by Sanghwa Park (SNU)
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Summary• Forward Muon Trigger Upgrade hardware
developments are nearly final stage. Thanks for many students / young researchers.
• We continue to improve performance of existing detectors (hardware and software wise).
• Physics Analysis (not only W), performance improvement, trigger operation, maintenance, etc… There are many things to do!
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Back up Slides
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Efficiency Turn on Curve
New TriggerUpgrade
MuIDTrigger
W
black : offline emulatorred : GL1 fired
Not firing by low momentum track!
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MuTR-FEE SG1 Trigger
Before Long Shutdown
After Long Shutdown
PHENIX Band Width Limit for Muon
Reje
ction
Pow
er
Improved Rejection Power after Long Shutdown or OR->AND2 Logic?
OR
AND2Surviving BBC rate 2MHz!
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Summary• New Muon Trigger-FEE SG1 trigger is under operation
as physics trigger for W• LL1 demonstrates stable performance w/ almost
100% efficiencies for both North&South• Trigger efficiency behaves pretty much as we
designed. Low efficiency in low PT, high efficiency in high PT regions.
• SG1xMUIDxBBC trigger functions with sufficient rejection power so far up to BBC rate ~ 2MHz.
• Combined with RPC will provide even stronger and more reliable trigger for W.