INDUSTRIAL AUTOMATION 1 - אוטומציה תעשייתית 1

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Microprocomputers

Lamps

Pneumatic or Hydraulic Cylinders

Numerical Displays

L O G I C C I R C U I T

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- Conveyor Belts

Ym

Relays

Solenoid Valves

X4

X2

- Lift ing Devices

Fixed Automation

Data Processing

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Y3

- Pumps

Sensor Inputs

TYPICAL OUTPUT DEVICES

Pneumatic Valves

Xn

Heaters

Electronic Gates

Programmable Counters

X3

INDUSTRIAL AUTOMATION

Electric Motors

Semi-Flexible Automation

Audioble Signals (Bells, Buzzers, Sirens)

Moving-Part Logic (MPL)

Programmable Control lers (PLC)

S E Q U E N C E C O N T R O L

Y2

X5

Y4

Output Signals

Timers

X1 Y1

- Robot Arms

Drum Programmers

Microprocessors

Fixed Automation

Pneumatic or Hydraulic Motors

PART 1

PART 1 � Chapters 1 - 6��

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List of Figures PART 1 Updated : July 27, 2003

CHAPTER 0 Introduction 0-1 Formal Infromation 0-2 Silabus Subjects List 0-3 Silabus - General Fig. 0-1 0-4 Subject Definition Fig. 0-2 (a-d) 0-4 Information Types Fig. 0-3 (a-g) 0-4 Binary Switching Elements Fig. 0-4 (a-b) 0-4 Self Correction

CHAPTER 1 Motion Actuators Fig. 1-1 1-1 Solenoid Fig. 1-2 1-1 Force- Fig. 1-3 1-1 Step Motor Fig. 1-4 1-1 Pneumatic Cylinder With Air Cushions Fig. 1-5 (a-g) 1-1 Basic Cylinder Types Fig. 1-6 1-1 Fifteen Ways of Using Cylinder Fig. 1-7 1-1 Fig. 1-8 1-2 Eight Types of Pneumatic Rotary Actuators Fig. 1-9 1-2 Air Motor

CHAPTER 2 Sensors Fig. 2-1 (a-d) 2-1 Common Actuation Methods for Limit Switches Fig. 2-2 2-1 Common Contacts Arrangements Fig. 2-3 2-1 Limit Switch Symbols for Different Contact Configurations Fig. 2-4 (a-b) 2-1 SPDT switch type BBM and MBB Fig. 2-5 (a-c) 2-1 Three Operation Methods of Photoelectric Sensores Fig. 2-6 (a-g) 2-2 Methods for Actuating Reed Switches Fig. 2-7 2-2 Use of Reed Switch to Sense Piston Position Fig. 2-8 2-2 Arc Suppression Methods for Protecting Relay Contacts Fig. 2-9 2-2 Proximity Sensor Fig. 2-10 2-2 Proximity Sensor Applications Fig. 2-11 2-2 Use of Magnetic Proximity Sensor Fig. 2-12 (a-d) 2-3 Four Basic Types of Pressure Switches Fig. 2-13 2-3 Pressure Switch Fig. 2-14 2-3 Level Switch Fig. 2-15 2-3 Two Flow Switches Fig. 2-16 2-3 Symbols for various Sensor Switches Fig. 2-17 (a-b) 2-3 Sensor Switch with/without dead band Fig. 2-18 2-3 Pneumatic Limit Valves And Their Fluid-Power Symbols Fig. 2-19 2-3 Limit Valve Fig. 2-20 2-4 Back Pressure Sensor Fig. 2-21 2-4 Back Pressure Sensor With Overtravel Protection Fig. 2-22 2-4 Using Back Pressure Sensor Fig. 2-23 (a-b) 2-4 Annular Back Pressure Sensor

Fig. 2-24 2-4 Interruptable Jet Sensor Fig. 2-25 2-4 Interruptable Jet Sensor Fig. 2-26 2-4 Interruptable Jet Sensor Fig. 2-27 2-4 Ultrasonic Sensor and Several Applications Fig. 2-28 2-4 Spring Sensor

CHAPTER 3 Introduction to Switching Theory Fig. 3-1 (a-I) 3-1 Boolean Algebra Concept Fig. 3-2 (a-f) 3-2 Algebric Minimization 1 Fig. 3-3 (a-c) 3-2 Algebric Minimization 2 Fig. 3-4 (a-d) 3-2 Karnaugh Maps Concept Fig. 3-5 3-3 4-Variables Karnaugh Map Example 1 Fig. 3-6 3-3 4-Variables Karnaugh Map Example 2 Fig. 3-7 3-3 4-Variables Karnaugh Map Example 3 Fig. 3-8 3-3 4-Variables Karnaugh Map Example 4 Fig. 3-9 3-3 4-Variables Karnaugh Map Example 5 Fig. 3-10 3-3 4-Variables Karnaugh Map Example 6 Fig. 3-11 3-4 4-Variables Karnaugh Map Example 7 Fig. 3-12 3-4 4-Variables Karnaugh Map Example 7.1 Fig. 3-13 3-4 4-Variables Karnaugh Map Example 8 Fig. 3-14 3-4 4-Variables Karnaugh Map Example 8.1 Fig. 3-15 3-4 4-Variables Karnaugh Map Example 9 Fig. 3-16 3-4 4-Variables Karnaugh Map Example 10 Fig. 3-17 3-4 4-Variables Karnaugh Map Example 11 Fig. 3-18 (a-b) 3-5 Majority Function Fig. 3-19 (a-d) 3-5 Motor Operation Control Fig. 3-20 (a-f) 3-5 BCD to 7-Segment Fig. 3-21 3-6 Various Switches & Relays Types Fig. 3-22 (a-e) 3-6 Majority Function Circuit Fig. 3-23 (a-d) 3-6 3-To-8 Decoder Circuit Fig. 3-24 (a-b) 3-7 3D 5-Variable Karnaugh Map, And Its Development Fig. 3-25 3-7 Optional Method of Constructing 5-Variable Karnaugh Map Fig. 3-26 3-7 Simplification of 5-Variable Function Fig. 3-27 3-7 Exercise Fig. 3-28 (a-b) 3-7 3D 6-Variable Karnaugh Map, And Its Development Fig. 3-29 (a-c) 3-7 Simplification of 6-Variable Function Fig. 3-30 (a-c) 3-8 Creation of 7-Variable Karnaugh Map Fig. 3-31 (a-b) 3-8 Simplification of 7-Variable Function Fig. 3-32 (a-b) 3-8 Creation of 8-Variable Karnaugh Map Fig. 3-33 3-8 Simplification of 8-Variable Function Fig. 3-34 3-8 Number of Variable Required to Define a Cell Fig. 3-35 (a-c) 3-9 Saving Contacts and Contact Springs Fig. 3-36 (a-b) 3-9 Fig. 3-37 3-9 Use of Relay Fig. 3-38 3-9 Use of Logic Gate Fig. 3-39 3-9 Logic Gate Symbols Fig. 3-40 (a-b) 3-9 Minimize by Selecting Non-Prime Cells Fig. 3-41 3-9 Multiple Output System Fig. 3-42 (a-b) 3-9 Minimize by Selecting Non-Prime Cell in a Multiple Output System

CHAPTER 4 Industrial Switching Elements Fig. 4-1 (a-k) 4-1 Typical Simple Gates Packages (SSI Small Scale Integrated) Fig. 4-2 (a-b) 4-2 Equivalent Circuits For Function AB+CD+EF Fig. 4-3 (a-b) 4-2 Fig. 4-4 (a-b) 4-2 Equivalent Circuits For Function ABCDEFGH Fig. 4-5 (a-e) 4-2 Static Hazard Elimination Fig. 4-6 (a-b) 4-2 Switch Bounce Elimination Fig. 4-7 4-3 I/O Modules for Electronic Gates Fig. 4-8 4-3 Optical Coupler Fig. 4-9 : 4-3 Relay Construction Fig. 4-10 4-3 Typical Relay Shapes Fig. 4-11 4-3 Typical Relay Contacts Fig. 4-12 4-3 Solenoid Valve Fig. 4-13 (a-m) 4-4 Pneumatic Valve Gates Fig. 4-14 (a-b) 4-5 Operation of 5/2 Spool Valve Fig. 4-15 4-5 Shuttle Valve (OR Gate) Fig. 4-16 4-5 Pneumatic Universal Gate (Samsomatic) Fig. 4-17 4-5 Pneumatic Universal Gate (Dreldea) Fig. 4-18 (a-e) 4-6 Pneumatic Gates (Telemechanique) Fig. 4-19 4-7 Fluid Flip-Flop Fig. 4-20 4-7 Fluid OR-NOR Gate Fig. 4-21 4-7 Fluid NOR Gate Fig. 4-22 4-8 Pneumatic Binary Amplifier (Single Stage) Fig. 4-23 4-8 Pneumatic Binary Amplifier (Two Stage) Fig. 4-24 4-9 Flow-Chart Showing Elements used in Binary Control System Fig. 4-25 4-9 Comparison Between Switching Methods

CHAPTER 5 Electrinc Ladder Diagrams Fig. 5-1 5-1 Ladder Diagram Fig. 5-2 (a-c) 5-1 Set-Reset Relay Flip-Flop Fig. 5-3 (a-b) 5-1 Flip-Flop Implementation Example Fig. 5-4 (a-b) 5-1 Cylinder Actuation Valves Fig. 5-5 (a-c) 5-1 Positions of Cylinder Limit-Switches Fig. 5-6 (a-b) 5-1 Graphic Symbols of Limit-Switches Fig. 5-7 (a-g) 5-2 Fig. 5-8 5-3 Cascade Method Target & Rules Fig. 5-9 (a-b) 5-3 Typical Process Definition Fig. 5-10 5-3 Typical Groups Partitioning Fig. 5-11 5-3 Typical Initial Cascade Circuit Fig. 5-12 (a-d) 5-4 Relays Cascade Design Process 1 (No Return Springs) Fig. 5-13 (a-d) 5-4 Relays Cascade Design Process 1 (With Return Springs) Fig. 5-14 (a-d) 5-5 Relays Cascade Design Process 2 (No Return Springs) Fig. 5-15 (a-d) 5-5 Relays Cascade Design Process 2 (With Return Springs) Fig. 5-16 (a-b) 5-6 Sequential System Fig. 5-17 (a-b) 5-6 Stability Definition Fig. 5-18 5-6 Huffman Method Design Steps Fig. 5-19 5-6 Huffman/PLC Combination Fig. 5-20 5-6 Merge Flow Lines Rules Fig. 5-21 (a-k) 5-7 Huffman Process For Sequence A+,A- (With Return Springs)

Fig. 5-22 (a-k) 5-7 Huffman Process For Sequence A+,A- (No Return Springs) Fig. 5-23 (a-k) 5-8 Process For Sequence A+,A-,A+,A-(With Return Springs) Fig. 5-24 (a-k) 5-8 Process For Sequence A+,A-,A+,A-(No Return Springs) Fig. 5-25 (a-d) 5-9 Automatic Mixing System Cascade Method Fig. 5-26 (a-h) 5-9 Automatic Mixing System Huffman Method Fig. 5-27 (a-b) 5-10 Full/Partial Input Streams A+,A-,A+.A- Fig. 5-28 (a-e) 5-10 Full/Pseudo Karnaugh Maps Fig. 5-29 (a-e) 5-10 Pseudo Map for A+,A-,A+,A- Fig. 5-30 5-10 Pseudo Map for 2 Cylinders & 4 States Fig. 5-31 5-10 Pseudo Map for 4 Cylinders & 8 States Fig. 5-32 (a-h) 5-11 Pseudo Karnaugh Map Example Fig. 5-33 5-12 GRAFSET for Automatic Mixing System of Fig. 5-36 Fig. 5-34 5-12 GRAFSET for Alternative Parallel Paths Fig. 5-35 5-12 GRAFSET for Simultaneous Parallel Paths Fig. 5-36 5-13 GRAFSET for Drilling Station

CHAPTER 6 Swquential Systems with Random Inputs Fig. 6-1 (a-m) 6-2 Thickness Detector System Design Fig. 6-2 (a-l) 6-3 Traffic Light Control System Design Fig. 6-3 (a-k) 6-1 Alarm System Design Fig. 6-4 (a-j) 6-4 Motor Direction Detection System Design Fig. 6-5 (a-i) 6-5 Combination Lock System Design


CHAPTER 7 Pneumatic Control Circuits Fig. 7-1 7-1 Intuitive Design Of Sequence A+,B+,A-,B- Fig. 7-2 7-1 Intuitive Design Of Sequence A+,B+,B-,A- Fig. 7-3 (a-b) 7-1 Cascade Design Of Sequence A+,B+, B-, A-,C+.C- Fig. 7-4 7-1 Cascade Design Of Sequence A+,A-,A+,A- Fig. 7-5 7-1 Multiple Limit-Valves Replacement Fig. 7-6 7-2 Pneumatic Cascade Basic Concept Fig. 7-7 (a-c) 7-2 Pneumatic Cascade Group Configurations Fig. 7-8 (a-g) 7-3,4 Pneumatic Cascade Design Process Steps Fig. 7-9 7-5 Pneumatic Cascade Example 1 Fig. 7-10 7-5 Pneumatic Cascade Example 2 Fig. 7-11 (a-b) 7-6 Flip-Flop Valve & Steering Valve Fig. 7-12 7-6 Two Steering Valves Providing Three Addresses Fig. 7-13 7-6 Three Steering Valves Providing Four Addresses Fig. 7-14 (a-e) 7-6 Design Sequence A+,A-,A+,A-,A+,A- Fig. 7-15 (a-d) 7-6 Design Sequence A+,B+,A-,B-,(A+/B+),A-,B- Fig. 7-16 (a-e) 7-7 Design Sequence A+,B+,B-,C+,B+,B-,C-,A- Fig. 7-17 7-8 Simplified Input Map Fig. 7-18 (a-d) 7-8 Design a Sequence With Passive States Fig. 7-19 7-9 Examples of Complex Functions Fig. 7-20 7-9 Function Tables Background Fig. 7-21 (a-b) 7-9 Function Tables Arrangement Fig. 7-22 (a-b) 7-9 3/2 Valve Connections yielding Single Output Function Fig. 7-23 7-10 Valve Connections With 2 Separate Outputs, 2-Variables Input Fig. 7-24 7-11 Valve Connections With 2 Separate Outputs, 3-Variables Input Fig. 7-25 7-12 Valve Connections With 2 Separate Outputs, 4/5-Variables Input Fig. 7-26 7-13 Valve Connections yielding Flip-Flop Output Functions Fig. 7-27 7-14 Example 1 Fig. 7-28 (a-f) 7-14 Example 2 (Huffman Solution for Sequence A+,A-,A+,A-) Fig. 7-29 (a-h) 7-15 Solution for Sequence A+,B+,B-,A-,B+,B- Fig. 7-30 (a-c) 7-16 Stop-Restart With Single Button & Separate Buttons Fig. 7-31 7-16 Stop-Restart With Multiple Remote-Control Stop Buttons Fig. 7-32 7-16 Electronic Circuit for Fig. 7-31 Fig. 7-33 7-16 Emergency Stop Modes Definition Fig. 7-34 (a-d) 7-16 Pneumatic / Electric Fig. 7-35 7-17 Fig. 7-36 7-17 Fig. 7-37 7-17 Fig. 7-38 7-17 Fig. 7-39 7-17 Fig. 7-40 7-17

CHAPTER 8 Miscellaneous Switching Elements & Systems Fig. 8-1 (a-h) 8-1 Sequence Chart for Common Timers Modes Fig. 8-2 8-1 - Fig. 8-3 8-1 - Fig. 8-4 8-1 -Delay Off- Fig. 8-5 8-1 - Fig. 8-6 8-1 - Fig. 8-7 (a-b) 8-1 Sequence Charts for Pulse Shaper Fig. 8-8 8-1 Relay Pulse Shaper Fig. 8-9 8-1 Pneumatic Pulse Shaper Fig. 8-10 (a-c) 8-2 Basic Set-Reset Flip-Flop (SR) Fig. 8-11 (a-b) 8-2 Toggle Flip-Flop (T) Fig. 8-12 (a-d) 8-2 T Flip-Flop Implementation - Counters Fig. 8-13 (a-c) 8-2 D Flip-Flop Implementation Shift Register Fig. 8-14 8-3 10-Stage Shift Register Fig. 8-15 8-3 Shift Register With 4 Parallel Tracks Fig. 8-16 8-3 Schmitt-Trigger Response Fig. 8-17 8-3 Schmitt-Trigger Response to Fuzzy Waveform Fig. 8-18 8-3 Truth Table for Error-Checking of BCD code Fig. 8-19 8-4 Truth Table for 2-Out-of-5 Code Fig. 8-20 (a-d) 8-4 Use of Karnaugh Map to Obtain Cyclic Code Fig. 8-21 8-4 Reflected Cyclic Code for Six Numbers Fig. 8-22 8-4 Fig. 8-23 8-5 Binary 8-Section Encoder Fig. 8-24 8-5 Typical 8-Section Encoder Fig. 8-25 8-5 Single-Output Incremental Encoder Fig. 8-26 8-6 Two-Output Incremental Encoder Fig. 8-27 (a-j) 8-6 Motor Direction Detection System Design (Copy of Fig. 6-4) Fig. 8-28 8-6 Simplified Block Diagram of a Closed-Loop NC System Fig. 8-29 8-6 Block Diagram of Open-Loop NC System Fig. 8-30 (a-c) 8-7 Adder for 2-Bit Numbers Fig. 8-31 8-7 Iterative Adder Block Diagram Fig. 8-32 (a-c) 8-7 Iterative Binary Adder Design Fig. 8-33 (a-g) 8-8 Iterative Parity Checker Fig. 8-34 (a-f) 8-8 Iterative 2 Out of n Checker Fig. 8-35 (a-g) 8-9 Iterative Binary Numbers Comparator Fig. 8-36 8-10 Comparison Between Natural-Binary & Reflected Cyclic Code Fig. 8-37 8-10 Iterative Circuit for Translating Natural-to-Reflected Cyclic Code Fig. 8-38 8-10 Iterative Circuit for Translating Reflected Cyclic to Natural Fig. 8-39 8-10 Truth Table for Translating Natural-to-Reflected Cyclic Code

CHAPTER 9 Semi-Flexible Automation Hardware Programmers Fig. 9-1 9-1 Drum Programmer Fig. 9-2 9-2 Drum Programmer Solution Fig. 9-3 (a-b) 9-2 Patch Board & Matrix Board Fig. 9-4 (a-b) 9-2 Fig. 9-5 9-2 Schematic Representation of Programmable Counter Fig. 9-6 9-2 Programmable Counter With a Single-Cycle Start Mode Fig. 9-7 9-2 Sequence A+,B+,C+,A-,(B-/C-),A+,A- - No Return Springs Fig. 9-8 9-2 Sequence A+,B+,C+,A-,(B-/C-),A+,A- - With Return Springs Fig. 9-9 (a-e) 9-3 Programmer Based on 1/n Code Fig. 9-10 (a-e) 9-3 Programmer Based on 2/n Code Fig. 9-11 (a-c) 9-4 Programmable Counter Example 1 Fig. 9-12 (a-c) 9-4 Programmable Counter Example 2 Fig. 9-13 (a-e) 9-4 2/n Stability Cases Fig. 9-14 9-5 1/n Code Programmer for Two Simultaneous Parallel Paths Fig. 9-15 9-5 1/n Code Programmer for Two Alternative Parallel Paths Fig. 9-16 9-5 1/n Code Programmer With Skipped Steps Option Fig. 9-17 9-5 1/n Code Programmer With Repeated Steps Option Fig. 9-18 9-6 Flow Chart for Selecting System Design Method

CHAPTER 10 Flexible Automation Programmable Controller Fig. 10-1 10-1 Block Diagram of Programmable Controller (PLC) Fig. 10-2 10-1 PLC Classifications According to Size Fig. 10-3 10-1 Discrete Input Devices to PLC Fig. 10-4 10-1 Discrete Output Devices Actuated by PLC Fig. 10-5 10-1 Standard Discrete I/O Interface Modules Fig. 10-6 10-1 Type of Electronic Memories Fig. 10-7 10-1 I/O Connection Diagram Fig. 10-8 (a-b) 10-1 PLC- Different I/O Connections Locations Fig. 10-9 10-2 Typical PLC Memory Map Fig. 10-10 10-2 PLC Programming Languages Fig. 10-11 10-2 Ladder Diagram Section Appearing on Screen Fig. 10-12 10-3 PLC Configuration Fig. 10-13 10-3 Typical PLC Control System Fig. 10-14 10-3 PLC Network (Macro) Fig. 10-15 (a-e) 10-4 PLC I/O Variables Assignment Fig. 10-16 (a-g) 10-4 PLC Motor Control System Fig. 10-17 10-5 Forward/Reverse Circuit Fig. 10-18 10-5 Example of Ladder Diagram Segment Fig. 10-19 10-5 I/O Assignment for Fig. 10-18 Fig. 10-20 10-5 Ladder Diagram of Fig. 10-18 in PLC Format Fig. 10-21 10-5 PLC Program for Fig. 10-20 Fig. 10-22 10-5 Use of LIFO Memory Stack Fig. 10-23 10-5 PLC Program for Fig. 10-22 Fig. 10-24 (a-f) 10-6 PLC Cascade Design for sequence (A+/B+),C+,A-,C-,C+,(B-,C-) Fig. 10-25 (a-b) 10-7 Multiple Use of LIFO Stack

Fig. 10-26 (a-b) 10-7 Rearrangement of Ladder-Diagram to Simplify Program Fig. 10-27 (a-b) 10-7 Timer Set for 20 Sec Fig. 10-28 10-7 PLC Program for Fig. 10-27 Fig. 10-29 (a-b) 10-7 Counter Set to Count to 25 Fig. 10-30 10-7 PLC Program for Fig. 10-29 Fig. 10-31 (a-b) 10-7 PLC Light-Flash Program Fig. 10-32 (a-c) 10-7 PLC Up/Down Counter Program Fig. 10-33 10-8 Two-Hand Safety Circuit Using PLC Fig. 10-34 (a-b) 10-8 PLC Design for Sequence 6x(D+,D-),D+,10 sec delay.D- Fig. 10-35 (a-c) 10-8 Ladder Diagram and Program for sequence of Fig. 10-34 Fig. 10-36 (a-d) 10-9 Timers and Counters Fig. 10-37 (a-c) 10-9 Fig. 10-38 (a-c) 10-10 Master-Control-Relay Command (MCR) Fig. 10-39 (a-c) 10-10 Jump Command (JMP) Fig. 10-40 (a-d) 10-10 Fig. 10-41 (a-c) 10-10 Equivalent PLC and Relay Circuits Fig. 10-42 10-11 Effect of Scanning Action on Internal States of Relays Fig. 10-43 (a-b) 10-11 Importance of Proper Rung Order Fig. 10-44 10-11 Trigger Flip-Flop Circuit for PLC Fig. 10-45 10-11 PLC Sequence Chart for Fig. 10-44 Fig. 10-46 10-11 Analog Input Devices for PLC Fig. 10-47 10-11 Standard Analog-Input Interface Modules Fig. 10-48 10-11 Analog Output Devices Actuated by PLC Fig. 10-49 10-12 Standard Analog-Output Interface Modules Fig. 10-50 10-12 Storing an Analog Input Value Fig. 10-51 10-12 Instruction Block Fig. 10-52 10-12 Transferring a Word to Analog Output Module Fig. 10-53 10-12 Fig. 10-54 10-12 Fig. 10-55 10-13 Fig. 10-56 10-13 Fig. 10-57 10-13 Logic Operations Fig. 10-58 10-13 Data Commands Fig. 10-59 10-13 PLC Micro/Macro Definition Fig. 10-60 10-13 Several Possible LAN Topologies Fig. 10-61 (a-f) 10-14 PLC Design of Thickness Detector System Fig. 10-62 (a-e) 10-14 PLC Design of Traffic Light Control System Fig. 10-63 (a-l) 10-15 PLC Design of Alarm System Fig. 10-64 (a-e) 10-16 PLC Design of Motor Direction Detector System Fig. 10-65 (a-i) 10-17 Combination Lock System

CHAPTER 11 Introduction to Assembly Automation Fig. 11-1 11-1 Bladed Wheel Hopper Feeder Fig. 11-2 11-1 Central Board Hopper Feeder Fig. 11-3 (a-c) 11-1 Shape of Centerboard Slot Fig. 11-4 11-1 Rotary Centerboard Hopper Feeder Fig. 11-5 11-1 Design Sheet for Reciprocating Tube Hooper Feeder Fig. 11-6 11-1 Revolving Hook Hopper Feeder Fig. 11-7 11-2 Design Sheet for Tumbling Fig. 11-8 11-2 Magnetic-Disk Hopper Feeder Fig. 11-9 11-2 Vibratory Bowl Feeder Fig. 11-10 11-2 Design Sheet for Vibratory Bowl Feeder Fig. 11-11 11-2 Disk Feeder Fig. 11-12 11-2 Slide Escapement

CHAPTER 12 Robotics and Numerical Control Fig. 12-1 (a-b) 12-1 Cartesian Robot and Coordinate System Fig. 12-2 12-1 Cylinde Robot and Coordinate System Fig. 12-3 12-1 Spherical Robot and Coordinate System Fig. 12-4 12-1 Articulated Robot and Coordinate System Fig. 12-5 12-1 Robot Work Envelope Fig. 12-6 12-1 RCC Device

CHAPTER 13 Simester Exams 13-1 Simester Exam Example - Questions 13-3 Simester Exam Example Responses 13-7 Typical Simester Exam Questions - Questions

Relay SPDT

a2

K?

RELAY SPST

START

+ -+ -

+ - +

S?

SW DPDT

S?

SW SPDT

K?

RELAY DPDT

+ -

a1

2-Input NAND1

23

2-Input NOR2

31

2-Input AND1

23

2-Input OR1

23

Inverter

3-Input AND

+ -

+

Time

Value

Value

Value

Time

Time

Time

Value

"Low"

"High"

"Unspecified"

Signal

LOGIC

IMPLEMENTATION

Fig. 0-2 Information Types

In Out

Logic

Element

Fig. 0-4 Self Correction

(d)

(a)

(b)

Fig. 0-3 Binary (Switching) Elements

(open)

A+ A-

(open)

a1,a2 = 00

e. Electrical Limit Switches

a. Electrical Switches

b. Electro-Mechanical Relays

d. Pneumatic Valves

c. Electronic Gates

f. Pneumatic Limit Valves

A-A+

g. Various Elements

BINARY SENSORS :

Pressure , Flow , Temperature , Height etc

a. Analog

b. Digital

c. Binary (Logic, "Digital")

d. Logic Levels

INDUSTRIAL AUTOMATION

Automation of Mechanical Industrial Production SystemsControl SectionOn-Off (Binary) Elements and InformationVarious Methodes to Obtain Low-Cost Systems

Fig. 0-1 Subject Definition

0-4

Time

Value

Value

Value

Time

Time

CHAPTER 1

MOTION ACTUATORS

Linear and Angular Motion Electrical Linear Actuators Electrical Rotary Actuators Fluid-power Linear Actuators Fluid-power Rotating Actuators Boolean Functions Standard Formats

CHAPTER 2

SENSORS

Electric Position Sensors Contacts Symbols Photoelectric Sensors Reed Switches Proximity Sensors Pressure, Flow and Level Switches Pneumatic Limit Valves Back-Pressure Sensors

CHAPTER 3

INTRODUCTION TO SWITCHING THEORY

Boolean Algebra Truth Tables Functions Algebric Minimization DeMorgan Theorem Universal Systems Boolean Functions Standard Formats Karnaugh Maps Maximal Cells Essentoal (Maximal) Cells Adjucent Cells Minimzation By Karnaugh Maps 4-Variables Minimization Examples 5 8 Variables Implementation

F2

= (A NOR A) NOR (B NOR B)

X.X' = 0

0 1 0

= (A NAND A) NAND (B NAND B)

Net : Connected / Not-connected

0.1 = 0

0

F1 = XY+X'Z+YZ

0

0 0

f'(A,B,C,D) = A'B'C'D' + A'B'C'D + A'BCD' + AB'C'D' +

0 1 1

1.0 = 0

0 0 0 0

+ AB'CD'+AB'CD+ABCD'+ABCD

F2 = XY+X'Z

F

1 0 0 0

1 1

X.Y'

1 0 0

X+0 = X

1.1 = 1

f. More Useful Operators

2. Universal Products of Sum :

Binary sensors (Temperature, Pressure, etc)

F1 = XY+X'.0+Y.0 = XY

1

1 0 1 0

1 1

h. Universal Systems

X+Y'

1 0 1

X+1 = 1

+ AB'C'D + ABC'D' + ABC'D

0+0 = 0

NAND (NOT AND) :

f(A,B,C,D) = (A+B+C+D)(A+B+C+D')(A+B'+C'+D)(A'+B+C+D).

"ON" / "OFF"

0 0 0 1

1

1 0 0 1

1 1

AND , OR , NOT

1 1 0

X+X = X

X nand Y = (X.Y)'

"HIGH" / "LOW"

0 0 1 0

1

1 1 1 0

F2 = XY+X'.0 = XY

Fig. 3-1 : Boolean Algebra Concepts

1 1

AND , NOT

1 1 1

3-1

George Boole

X+X' = 1

NOR (NOT OR) :

0+1 = 1

0 0 1 1

1

1 1 0 0

F1 = XY+X'1+Y.1 =

X

1. Universal Sum-of-Products :

Binary Items and Variables

X+X.Y = X

BOOLEAN ALGEBRA

X nor Y = (X+Y)'

1+0 = 1

0 1 0 0

1

1 1 0 1

= XY+X'+Y = X'+Y

Y

0 0

OR , NOT

.(A'+B+C+D')(A'+B'+C+D)(A'+B'+C+D')

Logic , Boolean , Binary , Digital

X+X'.Y = X+Y

XOR (Exlussive OR)

1+1 = 1 {*}

0 1 0 1

0

1 0 1 1

F2 = XY+X'.1 =

A+B = (A'.B')'

Z

0 0

NAND

Representations :

(X+Y).(X+Z) = X+YZ

X xor Y = X'Y+XY'

2. Universal Products of Sum :

0' = 1

0 1 1 0

0

1

= X'+XY = X'+Y

0 0

NOR

"0 / "1"

b. Basic Operators

X(Y+Z) = XY+XZ

INHIBITION

3. Minimal Sum-of-Products :

3. Minimal Sum-of-Products :

1' = 0

0 1 1 1

If Z=0 then :

(AB(C'+DE'))' = A'+B'+C(D'+E)

a. Basic Definitions

XY+X'Z+YZ = XY+X'Z

IMPLICATION

f(A,B,C,D) = A'BC'+AC+B'C+CD

A+B = (A'.B')' = ((A.A)'.(B.B)')' =

4. Minimal Products of Sum :

A

If Z=1 then :

0

1

XY+X'Z+YZ = XY+X'Z

Implementations :

c. Basic Relations

f(A,B,C,D) = (A'+C)(B+C)(A+B'+C'+D)

B

g. DeMorgan Theorem

1. Universal Sum-of-Products :

1

AND OR NOT

F1 = XY+X'Z+YZ

0 0 0

A.B = (A'+B')'

X.0 = 0

4. Minimal Products of Sum :

C

False and True replaced by 0 and 1

(A.B)' = A'+B'

f(A,B,C,D) = A'B'CD'+A'B'CD+A'BC'D'+A'BC'D+A'BCD+

1

F2 = XY+X'Z

A' = (A+A)' = (A NOR A)X.1 = X

i . Functions Basic Representations

Switch or Relay ON/OFF Position :

(A+B)' = A'.B'

0

Logic Theory Implementation in Switching

d. Minimization - Truth Table

e. Minimization - Math Operations

F1

A.B = (A'+B')' = ((A+A)'+(B+B)')' =X.X = X

0 0 1

A' = (A.A)' = (A NAND A)

1 1 1 1

Contacts : Open / Closed

0.0 = 0

(A.B+A'.C)' = (A'+B').(A+C')

0

XY+X'Z+YZ = XY+X'Z

D

X2 X1 X0 T

A

B

C

D

00 01 11 10

00

01

11

10

AB

CD

00 01 11 10

0

1

A

BC

C

A

BAN OCTAL NUMBER IS DEFINED BY THE BINARY COMBINATION X2,X1,X0

WHERE N(X2,X1,X0)=4.X2+2.X1+1.X0

A COMBINATIONAL SYSTEM DETECETS IF THE NUMBER IS DIVIDABLE

T = X2'X1'X0'+X2'X1.X0'+X2'X1.X0 +

=X0'(X2'X1'+X2'X1+X2X1'+X2X1)+X2'X1X0==X0'(X2'(X1'+X1)+X2(X1'+X1))+X2'X1X0==X0'(X2'+X2)+X2'X1X0==X0'+X2'X1X0==X0'+X2'X1

BY EITHER 2 OR 3

b. Block Diagram

X1 COMBINATIONAL CIRCUIT

X1

X1

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1

0

0

1

1

0

1

1

c. Truth-Table d. Minimization Steps

a. System Definition

Fig. 3-3 : Algebric Minimization (2)

AN INSURANCE COMPANY SELECTS CLIENTS ACCORDING TO THE FOLLOWING

CRITERIA : NATIONALITY, GENDER, AGE AND HAVING DRIVING-LICENSE.

CLIENT MUST SATISFY AT LEAST ONE OF THE FOLLOWING CONDITIONS :

FIND THE MINIMAL REQUIRED CONDITIONS

NATIONAL ITYG E N D E RA G ELICENSE

ABCD

CRETERIA VARIABLE 1 0

ISRAELI NON- ISRAEL IM A L E FEMAIL5 0 O R A B O V E U N D E R 5 0H A S L I C E N S E DOESN 'T HAVE L ICENSE

= A+B'C'D'+B'C'D+BC'D'+BC'D+BCD'+BCD' =

ISRAELIUNDER 50MALE

SIMPLIFIED RESULT :

INSURANCE COMPANY REQUIREMENTS

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

A B C D T

1

and/orNON-ISRAELI UNDER 50 WITH DRIVING LICENSE

NON-ISRAELI UNDER 50 WITHOUT DRIVING LICENSE

ISRAELI

NON-ISRAELI MAIL 50 OR ABOVEand/or

Fig. 3-2 : Algebric Minimization (1)


b. Boolean Variables Assignment

d. Truth Table

e. Truth Table Minimzation

f. Minimal Requirements

+ X2.X1'X0'+X2.X1.X0'=

and/or

T = A+A'B'C'D'+A'B'C'D+A'BC'D'+A'BC'D+A'BCD'+A'BCD

= A+B'C'(D'+D)+BC'(D'+D)+BC(D'+D)'

= A + C' + B

= A+B'C'+B.C'+BC = A + B'C' + B(C'+C) == A + B'C' + B

and/orand/or

1

111111111111

00

Fig. 3-4 : Karnaugh Maps Concept

d. 4-Variables Map Representations

c. 3-Variables Map Representations

A

BA

B0 1

0

1

b. 2-Variables Map Representations

A

B

A

B

Karnaugh Maps

* Visual method for boolean functionsminimization

* Each variable occupies half map* n variables split map into 2 basic cells, named

* Any two adjacent elements are representedby two "Adjacent" minterms

* Merging two adjacent elements produces

* Two adjacent 2-element cells may be merged

map Elements* Each element is represented by a n-variable

boolean product, named "Minterm"

a 2-elements cell, represented by a product of(n-1) variables

Into a 4-elements cell, represented by aproduct of n-2 variables, and so on

a. Map Concepts and Basic Properties

B'

A'

A'B'C'

ABC ABC'AB'C' AB'C

A'BC A'BC'A'B'C

n

= A+A'(B'C'D'+B'C'D+BC'D'+BC'D+BCD'+BCD)' =

c. Direct Minimzation

T = A+A'C'D+A'BC+A'C'D' = A+A'(C'D+BC+C'D')= A+C'D+BC+C'D'= A+C'(D'+D)+BC= A+C'+CB= A+B+C'

T

3-2

1

1

1

11

A

B

C

D

Minimal solutions : 2

1

1

F2 = BC + B'C'D + A'C'D

1

Minimal Solution 1

1

1

1

II

F1 = A'C' + AC + ABD + AB'D'

Essential cells : 4

1

1

1

Non-Essential cells : 6

Fig. 3-5 : Example 1

A

B

C

D

A

B

C

D

1

III

1

1

1

III

1

1

F4 = A'C' + AC + BC'D + B'C'D'

1

1

1

1

A

B

C

D

1

1

A

B

C

D

I

1

F2 = BCD' + ABD + A'BC'

1

1

1

1

1

IV Minimal Solution 2

1

1

1


1

1

Essential cells : 2

A

B

C

D


1

1 1

1

1

1

1

1

Minimal Solution 4

1

1

III

1

1

Essential cells : 2

1IV


1

F = A'C'D + ACD + A'BC + ABC'

1

1

1

A

B

C

D

F2 = A'C' + AC + ABD + B'C'D'

1

3-3

1

1

V

1 Minimal solutions : 1

1

1

IV

1

Essential cells : 3

1

1

A

B

C

D1

1

1

1


1

II

F1 = ABC + BC'D + A'BD'

11

1

II

1

1

1

1

1

III

1A

B

C

D

1

1

II


1

F1 = BC + B'C'D + A'BD

1

1

1

II

1

1

1

1

1

1

1

1

1

II

1

A

B

C

D1

1

1

1

1

1

1

1

1

1


1

1

1

1

1

1

A

B

C

D

1

1

1

1

A

B

C

D

F = AD + C'D + A'CD'

1

1

A

B

C

D

1

1 1

1

A

B

C

D

1

1

1

1

1

1

I

1

1

1

1

A

B

C

D

1

2

1

1

1

1

1

1

Essential cells : 0

VI

1F3 = A'C' + AC + BC'D + AB'D'



II

A

B

C

D


1

1

1

Fig. 3-7: Example 3

I

III

1

1

1

IV


I

I

Essential cells : 3

1

Maps Definit ions1

1

1

1

A

B

C

D

1

1

1

1

1

I



A

B

C

D

Function "Area"

1

1

V

1

1


1 1

1

A

B

C

D

A

B

C

D

1

1

1

1

F = AC + B'C + A'BC' + CD

1

1

A

B

C

D

1

1

A

B

C

D

All (Maximal) Cells

1

1

I

1

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

Essential cells : 2

F' = A'BCD' + AB'C'D

Non-Essential cells : 0Minimal solutions : 1

F4 = A'D + B'C + AB+ C'D'


F1 = A'C' + B'D'+ AB + CD

Essential cells : 0

F3 = AD'+ BC'+ CD + A'B'


F2 = BD+ AC + A'B'+ C'D'

F = (A + B' + C' + D).(A' + B + C + D')

F5 =F6 =

Essential cells : 2Non-Essential cells : 1 (+2)

F = AD' + A'B' + BCD

Minimal solutions : 1Selected Don't Cares : All

Essential cells : 0Non-Essential cells : 3 (+5)


F = AC' + C'D + A'CD'

Selected Don't Cares : None

F = AD + A'D'



Essential cells : 2

Selected Don't Cares : Partial

Essential cells : 1



F1 = ACD + AB + A'C'

Selected Don't Cares : Partial

F2 = ACD + AB + A'D'Note : F1 and F2 are equivalent but not identical

Essential cells : 0Non-Essential cells : 8

Minimal solutions : 1Selected Don't Cares : None


Fig. 3-12 : Example 7.1

Fig. 3-13 : Example 8 Fig. 3-14 : Example 8.1

Fig. 3-15: Example 9



I

I

I

I

I

I

I II

II

II

II

II

II

II

III

III

III

III

III

III

III IV

IV

V VI

-

-

----

- ---

--- -

---

--

-

--

--

-

--

-- -

----

-

-- -

-

-

--

--

---

--

-

-

--

--

-

--

-

--

--

-

F' = AB'D + A'BD' + BC'D

--

---

-

-

3-4

1

1

1

1

1 1 1

11

1 1

1 111

1

1

1

1 1 1

11

1 1

1 111

1

1

1

1 1 1

11

1 1

1 111

1

1

1

1 1 1

11

1 1

1 111

1

1

1

1 1 1

11

1 1

1 111

1

1

1

1 1 1

11

1 1

1 11

0

0

0

0

0

0

0 0

0

0 0

00 0

0

0 0

00 0

0

0 0

01 1 1

1

11

1

1 1 1

1

11

1

1 1 1

1

11

1

-

1

1

1

11

1

1

1

1

1

1

11

1

1

1

1

1

1

11

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1 1 1

1

1

1

1 1 1

1

1

1

1 1 1

1

1

1

1 1 1

1

Maps Definitions

Function "Area"All (Maximal) CellsMinimal Solution 1Minimal Solution 2Minimal Solution 4V

IIIIIIIV

F = (A'+B+D').(A+B'+D).(B'+C+D')

X Y Z A B C00 01 11 10

0

1

X

Y,Z

00 01 11 10

0

1

X

Y,Z

X

Y

X

X

Z

Z

ZYX

Y

Y

X Y Z M

00 01 11 10

0

1

X

Y,Z

X

X

Y

Y

X Y Z

Z

Z

Y

X

00 01 11 10

00

01

11

10

D1,D0

D3,D2

00 01 11 10

00

01

11

10

D1,D0

D3,D2

00 01 11 10

00

01

11

10

D1,D0

D3,D2

00 01 11 10

0

1

X

Y,Z

A = X + Y + Z

A

C

B

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0

1 1 1

1 0 0

1 0 0

1 1 0

1 1 0

1 1 0

1 0 0

0 0 1 0

0 1 1 1

1 1 1 1

0 0 1 0

0 0 0 0

B = XY + XZ + YZ

C = XYZa. Truth-Table

b. Karnaugh-Maps

c. Contact Circit Realization

Fig. 3-19 : Motor Operation Control

B

SWITCH-YSWITCH-X

C

SWITCH-Z

d. Electrical Diagram

A

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0

1

0

0

1

1

1

0

a. Truth-Table

Fig. 3-18 : Majority Function

M = XY+XZ+YZ

0 1 1 1

0 0 1 0

b. Karnaugh-Map

1 1 1 1

D3 D2 D1 D0 E F G

BCD to 7-SEGMENTS CONVERTER

d. Truth-Table (Partial)

Design a combinat ional c ircui t that gets a BCD input, and converts i t to7-Segment d isplay.

D2D3

c. Block Diagram

D0D1

1 0 0 0

0 0 0 00 0 0 1

0 1 1 00 1 1 1

0 1 0 00 0 1 1

0 1 0 1

1 0 0 1

1 0 1 11 1 0 01 1 0 11 1 1 0

1A B C D


e. Karnaugh Map of "F"F=D2'+D1'D0'

1 1 - 1

1 0 - 1

1 0 - -

1 0 - -

A=D3+D2.D1'+D2'D1+D1.D0'=

0 1 - 1

0 1 - 1

1 0 - -

1 1 - -

0 1 - 1

1 0 - -

0 1 - 1

1 1 - -

f. Karnaugh Map of "A"

Fig. 3-20 : BCD to 7-Segments

Binary combinat ions 1010-1111 (above decimal 9) may not appear asinputs, and are refered as don't-care.

BCD is short form of Binary-Coded-Decimal. I t Represents 10 decimaldigits (0-9) in 4-bit binary code (0000-1001).

1111

11

000

------

-----

-

00

011

11111

=D3+D2.D1'+D2'D1+D2.D0'

0 0 1 0

1 0 1 0

b. 7-Sigments Arrangement

(Exer1-7)

0 1 1 1

3-5

E FF

E

G

BD

G

A

D

C

C

AB

*

*

* *

M1

B

B'A'

CB

A

SW PUSHBUTTON

+-

M

A

BC

A

M

B

+ -

C

RELAY 4PST

A

C

SW DPST

+-

C

RELAY SPDT

SW DPDT

RELAY 4PDT

A

RELAY DPST

C

B

RELAY DPDT

B

RELAY SPST

SW SPST

M

SW SPDT

A

B

A

+-

B

M2

M3

M4

M5

M6

M7

AB'

B

C

C

C'

C'

C'

C

C'

C

COMMON

A

B

C

A'B'C'A'B'CA'BC'A'BCAB'C'AB'CABC'ABC

A

B

C

COMMON

Fig 3-23 : 3-TO-8 DECODER CIRCUIT

A'B'C'A'B'CA'BC'A'BCAB'C'AB'CABC'ABC

A B C

a. Block-Diagram

b. Switches-Operated Circuit

c. Contacts Circuit

d. Relays-Operated Circuit

b. Majority Boolean Function

b. Switches-Operated Circuit

T = AB + AC + BC = AB + (A + B)C

d. Switches Remote Operat ion

Fig. 3-22 : "MAJORITY" Function Circuit

3 Long Lines, Carrying Low Currente. Relays Remote Operation

c. Contacts Circuit

9 Long Lines, Carrying High Current

Fig. 3-21 : Various Switches and Relays Types

LAMP

ABC

A'BC'

A'B'C

ABC'

AB'C

A'B'C'

AB'C'

A'BC

3-6

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

1 2 3 42

43

1

A

B

C

DE

D

a. 3-D Representation b. Flat Representation

Fig. 3-24 : Three-Dimentional Five-VariableKarnaugh Map, and Its Developmenet

E' E

1 1

1

1

1

0

0

0 0

0

0

0

0

-

--

-1

1

1 1

1

0 0

0 00

0 0

0 0 0

T=A'B'C'D'+A'BDE'+A'B'CDE'+AB'C'D'+A'BC'DE+ABCDE+ABCD'E

with impossible conditions : A'B'CD''=1 ACDE'=1

a. Original Function

T=B'C'D'+A'BC'D+CDE'+ABCE

c. Simplified Function

b. Karnaugh MapFig. 3-26 : 5-Variable Minimzation Exercise (With Solution)

T=A'B'C'E'+A'B'CD'+ABC'DE'+AB'C'E'+AB'CD'E'+B'C'D'E+A'B'C'DE+CD'E


T=


b. Karnaugh Map Fig. 3-27 : 5-Variable Minimzation Exercise, (Without Solution)

b. Flat Representation

a. 3-D Representation Fig. 3-28 : Three-Dimentional sIx-VariableKarnaugh Map, and Its Developmenet

E

F

E' E

EE'

F

E T=A'BC'F'+AB'C'DE'F+ABDF+ACDE+ACD'E++A'C'DE'+A'C'DEF'

with impossible conditions :A'B'C'D'=1 A'BCD'F=1


T=A'C'F'+ACE+C'DE'F+ABDF


Fig. 3-29 : 6-Variable Minimzation Exercise (With Solution)

- - - --

1

1 1

1

1

1

1

1 11

1 1

1

1 1

1

11

1 1

-0 0

00

0 0

00

0 0

00

0 0

00

0 0

00

0

0

0

0

0

0

0

00

0

0

0

0

0 000

0

*

*

*

*

* *

b. Karnaugh Map

3-7

Fig. 3-25 : Optional Constructionof Five-Variable Karnaugh Map (Not Recommended)

*

A

B

C

D

E

F

G

G

F

E

H

A

B

C

D

1 2 3 4

2

3

1

4

E

F

G

F

E

G

11

1 1

11

11

11

11

1 1

11

1

11

11

11

1

1 1

- ---

T=A'C'D'G'+ABCF'+B'D'FG+A'C'EF'

E

F

G

H

--

-- -

- - - -

- --- --

--

----

--

--

--

--

--

--

--

--

-

--- -

-

-

-

--

-- -

--

-

--- -

-

-

-

--

-- -

-

--

-

--- -

-

-

-

--

--

-

- - - -

1 1

1 1

11

11111

1 1

11

1

1

11

-

--

- 11

11

11

1

1

2 3 4 5 6 7 81 2 3 4 5 6 7

1 2 3 41 2 3

2 3 4 5 6 7 8

1 2 3 4 5 61 2 3 4 5

1 21

Single Square2-Square Cell4-Square Cell8-Square Cell16-Square Cell32-Square Cell64-Square Cell128-Square Cell

Size of Cell

Number of Variablesin The Function

a. Upper Level

Fig. 3-30 : Seven-Variable KarnaughMap, and Its Developmenet

b. Lower Level

c. Flat Representation AB'C'D'EF'G'

3-8

b. Simplif ied Function

a. Function Karnaugh MapFig. 3-31 : 7-Variable MinimzationExercise (With Solution)

11

Fig. 3-33 : 8-Variable Minimzation Exercise

11

a. Upper Level a. Lower Level

Fig. 3-32 : Eight-Variable KarnaughMap, and Its Developmenet

Fig. 3-34 : Number of Variables Requiredto Define Certain Cell Address

* *

*

*

*

-

1 & >1 =1 >1 & &S

R

y

y'

S

R

y

y'

S

R

y

y'FF

1 2

X2X2

CR1X1

CR1

X1

1 2

X21 2

X2

X21 2

X1CR1

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

NOT AND OR EXCLUSIVEOR NOR NAND IMHIBITION FLIP-FLOP

OldEuropeanSymbols

Old USASymbols

New SymbolsRecommendedby ISO

Y1

Y1 X1

Y2

CR1=Y1.X2+Y2.X2'+Y1.X1'+Y2.X1

Fig. 3-35 : Saving Contacts and Contacts Springs

T=Y2.Y3+Y1.Y3+Y1.Y2.Y3'


Y2

Y3

Y1

Y3

Y1 Y2

T

Y2

Y3

Y1

Y3

Y2

T

Y2 Y2

Y1

CR1=Y1(X1'+X2)+Y2(X1+X2')

Y2

Y1

6 Contacts , 12 Springs 4 Contacts , 10 Springs8 Contacts , 16 Springs

X1

CR1=Y1(X1'+X2)+Y2(X1+X2')

(X1')

(X1)

(X2)

(X2')

b. Sneak Path Y2.Y3'

T=Y2.Y3+Y1.Y3+Y1.Y2.Y3'+(Y2.Y3')

Fig. 3-36 : Sneak Path Creation

RELAY

yyyy

y'

GATEx3x2x1

x4

Fig. 3-37 : Use of Relay

Fig. 3-38 : Use of Gate

ExitationFunction(Y)

OutputVariables (y,y')

InputVariables (x')

T

OutputFunction (T)

y'y'

Y

a. Original Function b. Saving Contacts c. Saving Contact Springs

0

0

0 0 0

1

1

- -----

--- 1-

--

- -

0

-- 0

-0

0 1

0

-

T=BC'+A'C'D= T=B'C'D+A'C'D==(B+A')C'D

Fig. 3-40 : Minimize by SelectingNon-Prime Cells

b. 4 Gatesa. 5 Gates

=C'(B+A'D)

T3

OutputVariables

RELAY

A

T2

T1BCDE

InputVariables

Fig. 3-41 : MultipleOutput System

0 0 0 0

0

0

00

0 1111

1 1

-

0 000

00

00

1

1

1111

0

0

T1=AC'+BCD(Instead of A'C+BD)

T2=A'B+BCD

Fig. 3-42 : Minimize by Selecting Non-Prime Cells, inMultiple-Ourtut System

a. Function T1 b. Function T2

Fig. 3-39 : Logic Gate Symbols

3-9

CHAPTER 4

INDUSTRIAL SWITCHING ELEMENTS

Electronic Gates Electronic Gates Implementation Input/Output Module�Electric Relays

Moving Parts Logic (MPL)

9

6

12

11

10

78

J

CLK

K

Q

Q

PR

CL

4

1

16

15

14

23

J

CLK

K

Q

Q

PR

CL

1 2 3 4 5 6 7

891011121314

GND

VCC

SN54LS00SN74LS00

2 61

VCC

SN54LS04

14 8

SN74LS04

11

GND

3

91012

54

13

7

2 61

VCC

SN54LS20

14 8

SN74LS2011

GND

3

91012

54

13

7

13

7

11

SN74LS76

65

10

1

12

VCC2 4

914

3

GND

SN54LS76

1 2 3 4 5 6

891011121314

GND

VCC

SN54LS32SN74LS32

7

b. Quad 2-Input OR Gate

a. Quad 2-Input NAND Gate

e. Hex INVERTER

d. Dual 4-Input NAND Gate

8

1516

2 61

VCC

SN54LS27

14 8

SN74LS2711

GND

3

91012

54

13

7

c. Tripple 3-Input NAND Gate

f. Dual J-K FLIP-FLOP

Fig. 4-1 : Typical Simple Gates Packages (SSI - Small Scale Integrated)

SN54LS00

SN 54 LS 00

Technology

Vendor

Family

Function(Serial Number)

h. Chip Name "Code"

i. Families

74 : Commercial Family54 : Military Family

Difference : Temperature Range

Many More Families

j . Technologies Characteristics

High / Low SpeedHigh / Low Power DissipationHigh / Low Power Drive (Fan-Out)High / Low Power Supply Voltage

And Many More

2 61

14 811

3

91012

54

13

7

g. Chip Configuration

k. Grid-Array Package(not SSI)

4-1

1

23

4

56

9

108

12

1311

1

23

4

56

9

108

1

23

4

56

9

108

12

1311

4

56

1

23

9

108

1

23

1

23

00 01 11 10

0

1

C

A,B

00 01 11 10

0

1

C

A,B

BCDEFGH

A

T

B

CD

EF

GH

A

T

b. 7 Gates , 2 Packages , 3xT delay

ANTI-BOUNCE CIRCUIT

OUT

A

B

AB

OUT

PRESS BOUNCE RELEASE BOUNCE

AB

CD

EF

AB

CD

FE

AB+CD+EFD

F

C (CD)'

(EF)'

(AB)'

E

AB

((AB}'.(CD)'.(EF)')' =

= AB+CD+EF

Fig. 4-2 : Equivalent Circuits for Function AB+CD+EF

a. AND-OR-NOT system b. NAND system

A (AB)'

A'C

AB+A'C

B

C

AB B

C

A

Fig.4- 3 : Equivalent Circuits for Function AB+A'C

a. AND-OR-NOT system b. NAND system

AB+A'C

(A'C)'

A'

A'

4 Gates , 3 Packages 4 Gates , 1 Package

Fig. 4-4 : Equivalent Circuits for Function ABCDEFGH

a. 7 Gates , 2 Packages , 7xT delay

Required Signal (OUT)

Fig. 4-6 : Switch Bounce Elimination

b. Eliminate Bounce by a Simple Flip-Flop

A'C

AB+A'C

AB

0 1 1 1

0 0 1 0

B

C

A

A'

0 1 1 1

0 0 1 0

AB

CD

EF

AB

AB+A'C+BC

CA'

CB

Fig. 4-5 : Hazard Elimination

(a)

(b)

(d)

(e)

a. Contact Bounce (A,B) and

AB

A'C

AB+A'C

A

Transition From 011 to 111

2

1

(Gate 1 Slower Than Gate 2)

(c)

4-2

(Save Packages)

(Increase Speed)

+-

+-

+-

+ + +

+

+ +

+

A A B B

T=A T=A' T=A.B T=A+B

a. YES Gate b. NOT Gate c. AND Gate

AA

d. OR Gate

B

T=A.B'A

e. INHIBITION Gate

B

T=A+B'A

f. IMPLICATION Gate

A

B

T=A+BT=A.B

i. AND/OR Gate

A

B

T=A.B'T=A+B'

j. INHIBITION/IMPLICATION Gate

A

T=A'T=A

h. YES/NOT Gate

A

Fig. 4-13: Pneumatic Valve Gates

T=A.C+A'B

BC

g. SELECTOR Gate

(T=A+B)

A

B

Hot

Cold

Hot

Cold

k. Non-Valve "OR" Element l. Almost equal HOT/COLDpressure - No Flow

m. COLD Pressure Less Than HOT -HOT Flows Into COLD

4-4

X1

X4

X2

X1

D

a. Position 1

X2

E

C

D

C

B

P2

A

P2

b. Position 2

P1

T=X1+X2

E

Fig. 4-14 : Operation of 5/2 Spool Valve

X5

X1

(Samsomatic, W. Germany)

P1

X3

Fig. 4-15 : Shuttle Valve

4-5

X4

A

X2

Fig. 4-16 : Pneumatic Universal Gate (MPL)

T

T=X5(X1'+X2)+X4.X1.X2'

T=X3(X1'+X2)+X4(X1+X2')

(OR Gate)

Fig. 4-17 : Pneumatic Universal Gate (MPL)

B

(Dreloea, E.Germany)

Fig. 4-18 : Pneumatic Gates (TELEMECHANIQUE, France)

Fig. 4-19 : Fluid Flip-Flop (Wall Attachment Principle)

Fig. 4-20 : Fluid OR-NOR Gate

Fig. 4-21 : Fluid NOR Gate (Impact Modulator, AIR Logic, USA)

4-8

Fig. 4-22 : Pneumatic Binary Amplifier (Single Stage, AIR LOGIC, USA)

Fig. 4-23 : Pneumatic Binary Amplifier (Two Stage, CLIPPARD, USA)

Fig. 4-25 : Comparison Between Switching Methods

4-9

Fig. 4-25 : Comparison Between Switching Methods

4-10

CHAPTER 5

ELECTRIC

LADDER DIAGRAMS

Ladder Diagram Relays, Cylinders, Valves Symbols Sequential Sequences Relays Cascade Implementation Huffman Methode Flow Diagram Primitive and Merged Flow Tables State Assignment Output and Exitation Functions

a2

+ -

a2

a2

+ -

+ -

a1

a1

a1

+ -

a1

STOPSTART

CR1

CR1

STOPCR1

CR1

CR1

CR1

CR1

START

STOPSTART

CR1

CR1

CR1

1

2

3

45

6

7

8

RELAY CR1

START STOP

a2

+ -

a1

a2

A+ A-(Closed) (open)

A+ A-

(Closed)A+ A-

(open) (open)

(open)

Fig. 5-5 : Positions of Cylinder Limit Switches

A+

a. Normally Open b. Normally Closed

Fig. 5-6 : Graphic Symbols of Limit Switches

SwitchingCircuit-1 Load-1


Load-3SwitchingCircuit-3


Load-nSwitchingCircuit1-n

|||

|||

Fig. 5-1 : Ladder Diagram

ResetCircuit

SetCircuit

a. Basic Circuit

b. Basic Contacts Circuit

c. General Circuit

Fig. 5-2 : Set-Reset Relay Flip-Flop

a. Example - Schematic Circuit

RedLamp

RedLamp

RedLamp

RedLamp

Voltage

b. Example - Wiring Diagram

Fig. 5-3 : Flip-Flop Implementation Example

a1,a2 = 10

a1,a2 = 00

a1,a2 = 01

a. Position "-"

b. Position "Moving"

c. Position "+"

A+ A-

a. Valve Without Return Spring

b. Valve With Return Spring

Fig. 5-4 : Cylinder Actuation Valves

5-1

cr1

cr1

START

a2

A+

CR1

b1

A-

START

a2

b1 A+

A-

B+a1

cr1

cr1

CR1

START

a2

b1 A+

A-

B+a1

b2TMR

B-

START A+b1 cr1

cr1

A-

A+

a2

STARTb1

CR1

B+

TMRb2

tmr B-

b2

B+

b1

cr1

A-

B-

b2

a2CR1

TMR

cr1START

a1

b2

A+

CR2

cr2

cr1

tmr

tmrcr1

cr1

cr1CR3

cr3

a1

cr1

cr1

START,A+,A-,B+,10 Sec delay,B-(STEPS:

1 2 3 4 5)

Long Start causes Actuation ofA+ and A- simultaneously

c. Step 2 : Actuate A-

PROBLEM

B+ is also actuatedbefore cycle starts

d. Step 3 : Correct and Actuate B+

PROBLEM

b. Step 1 : Actuate A+

e. Steps 4-5 : Correct and Actuate TMR and B-

PROBLEMB+ and B- are actuated simultaneously.CR1 is actuated infiniti ly

f. Correct problems of (e)

a. Process Sequence (No Return Springs)

g. Isolate Limit Swithes from Solenoids Current

Fig. 5-7 : "Intuitive" Design Problems

5-2

Add reset (b2') to CR1

A+

CR1

cr3'START

cr1

cr4' cr2'

CR2

cr2

cr3'

cr4'

CR3

cr3

CR4

cr4

cr1

cr2

cr3

B+

A-

B-

C+

C-

cr

cr

cr

cr

cr

cr

START , A+ , , C+ , , A- , B-B+C-

A+

Group 1Termination

Group 2Termination

Group 3Termination

Group 4 (Last)Termination

Group(s) Condit ion(s)




Condit ion(s)Group(s)

Condit ion(s)Group(s)

Fig. 5-11 : Typical Initial Cascade Circuit,of 3-Cylinder / 4-Groups Process

A- ,

Fig. 5-9 : Typical Process Definition

START , A+ , , C+ , , A- , B-B+C-

A+A- ,

Fig. 5-10 : Typical Groups Partitioning

I I I I I I VI

RELAYS CASCADE SYSTEMS

* Maximal size groups (to obtainminimum number of group relays)

* Same "Letter" may appear no more

conflicted commands to a cylinder)

Fig. 5-8 : Cascade Method Target & Rules

than once in a group (to avoid

* Except for specific cases, groupsPartit ioning doesn't depend on having

or not having valves return springs

* Avoid conflicting actuation of acylinder

* Distinguish between situationswhere a cylinder performs more thana single cycle

A+

A-

B+

B-

C-

C+

START

a2

a1

b2

b1

c1

c2

1 2 3 4 5 6 7 8 9

a. Sequence List Representation

b. Flow Chart Representation

5-3

a1

a1 b2

a. Process Sequence Information

START , A+ , , C+ , , A- , B-A-

B+

C-

A+

1. Cylinders are actuated by 5/2 valves without

2. Valves are actuated electrically (solenoids).

START , A+ , , C+ , , A- , B-A-

B+

C-

A+

I I I I II I V

b. Groups Partitions

Fig. 5-12 : Relay Cascade Design Process 1 (No Return Springs)

c. Total Initial Circuit

return springs.

d Complete Circuit

d. Complete Circuit

c. Total Initial Circuit

Fig. 5-13 : Relay Cascade Design Process 1 (With Return Springs)


START , A+ , , C+ , , A- , B-A-

B+

C-

A+

1. Cylinders are actuated by 5/2 valves with


START , A+ , , C+ , , A- , B-A-

B+

C-

A+

I I I I II I V

b. Groups Partitions

return springs.

B+ duration

5-4

cr2'cr4'cr3'START

cr4'cr2

cr3

cr3

cr4

cr

cr

cr

cr

cr

cr C-

C+

B-

B+

A-

A+

CR1

CR2

CR3

CR4

C-

C+

B-

B+

A-

A+

cr2'cr4'cr3'START

cr1

cr1

cr3'

cr2 cr2

cr1

cr3'cr1

cr4'cr2

cr3

cr3

cr4

cr1

cr3

cr2

cr3

cr2

cr2

cr2

cr3

a2

a2

c2

c1

cr2'cr4'cr3'START

cr1

cr1

cr2

cr3'

CR1

CR2

CR3

CR4

cr2

cr3

cr4'

cr3

cr4

cr

cr

cr

CR2

CR4

CR1

CR3

A+

B+

C+

cr4'cr3' cr2'START

cr1

cr1

cr2

cr3'a2

cr2

cr3

cr4'c2

cr3

cr4

c1 a2b1 b1

A+

B+

C+

cr1

cr3

cr2

cr3

cr4

cr2

a1

a1 b2

CR3

CR2

CR1

CR4

d. Complete Circuitc. Total Initial Circuit

Fig. 5-14 : Relay Cascade Design Process 2(Without Return Springs)


START , A+ ,


B- ,B+ , C+ , A- , D+ , A+ , D- ,C- , A- ,

b. Groups Partit ion

START , A+ , B- ,B+ , C+ , A- , D+ , A+ , D- ,C- , A- ,

I I I I I I (IV)

d. Complete Circuitc. Total Initial Circuit

Fig. 5-15 : Relay Cascade Design Process 2(With Return Springs)


START , A+ ,

1. Cylinders are actuated by 5/2 valves with return springs.2. Valves are actuated electrically (solenoids).

B- ,B+ , C+ , A- , D+ , A+ , D- ,C- , A- ,

b. Groups Partit ion

START , A+ , B- ,B+ , C+ , A- , D+ , A+ , D- ,C- , A- ,

I I I I I I (IV)

5-5

c2

cr2'

cr1

cr1

cr2

cr2

cr3

cr3

cr4

cr2'

cr3'

cr4'

cr

cr

cr

cr

cr

cr

cr

cr

A+

A-

B+

B-

C+

C-

D+

D-

CR1

CR4

CR2

CR3

cr3' cr4' cr3' cr4'

cr1

cr2'START START

cr1 cr3'

cr2

cr3

cr3

cr4

cr1

cr1

cr1

cr2

cr2

cr2

cr3

cr3

cr3

cr4

d2 b1

b1 a1

c1

a2

a2

a1

b2

d1

A-

B-

C-

D-

D+

C+

B+

CR1

CR4

CR2

CR3

START cr3'

cr1

cr2'

cr1

cr2 cr1

cr2

cr3'

cr2

cr3

cr1

cr1

cr1

cr1

A+

A+

B+

C+

D+

CR2

CR3

CR1

START cr3'

cr1

cr2'

cr1

cr2

cr3'

cr2

cr3

cr1

cr1

cr2

cr2

cr2

cr3

cr3

cr3

cr3

D+

C+

B+

A+

CR2

CR1

CR3

b1

a1

a1

a2

a2

b2

d1

c1

c2

d2

1. Cylinders are actuated by 5/2 valves without return springs.

B+

A+ D+

2

2

4

4i

ElectricalDelay

Set

Reset

MechanicalDelay

td1

td2

Unstable State

Stable State Unstable State

td3

td4

Combination System

MemorySystem

External Inputs

External Outputs

Internal State

MemoryExitation

Combination System

External Inputs

External Outputs

Internal State

Set-ResetControl

X1

Xn

Z1

Zm

SRY

SRY

Y1

Yk

a. General Block Diagram

b. General Detai led Block Diagram

Fig. 5-17 : Stability States

a. Relay Flip-Flop Transit ion Response

Each transit ion is combined of UnstableState, followed by a Stable State.

Unstable State duration is the time delayfrom the command start (set/reset) to itsfully execution.

Refering to relay fl ip-flop, unstable Stateduration is the time delay from the set(or reset) start until relay contact closing (or releasing).

Unstable state i wil l be represented byits number : i.

Stable state i wil l be represented by itsnumber surround by a circle :

* System requirements definit ion

* Primitive f low diagram

* Primitive flow table* Merge options Diagram

* Merge groups selection

* Merged flow table

* States assignment

* Flip-flops exitation expressions

* Output table

* Outputs expressions

* System Logic Circuit

Fig. 5-18 : Huffman Design Steps

Huffman method is very effective inreducing the number of relays fl ip-flops.

Fig. 5-19 : Huffman/PLC Combination

Two (or more) l ines in f low table can be merged,as long as they don't conflict.

Merging l ines reduce internal states, reducenumber of required f l ip-f lops, and make designmore simple.

21

1

1

3

-

3

-

-

-

-

Line i

Line j

Merged Lines (i,j)

Fig. 5-20: Merge Flow Lines Rules

Fig. 5-16 : Sequential System

b. Stability Definition

5-6

When system realization is based on PLC,number of "relay" fl ip-flops doesn't actuallyeffect system cost.

The Huffman-PLC method implementsflip-flop for each state, but eliminates thecomplexity of Huffman method, and alsoenables to implement large PseudoKarnaugh maps.

Design process by Huffman methodmay become very complex, from"State Assignmsnt" step, and on.Furthermore, it is based onKarnaugh maps, which el iminatethe number of involved variables.

It is also effective for design ofsystems with Random Inputs.

START

START

-

0d. Primitive Flow-table

0

{1,2) , (3,4)

j . Exitation and Output Functions

S1 = a2

k. Relays Ladder Diagram

(Different Format)

a1

-

0

a2

d. Primitive Flow-table

k. Exitation and Output Functions

a2

(Different Format)

0

a1

1

f. Selected Groups

a1

1

a1

START

(S1 =cr1'. a1'.a2)

c. Flow-diagram (primitive)

START , A+ ,A-

2

0

i Output Table

1

0

a2A+

b. Basic Block Diagram

- -

h States Assignment

--

1

g. Merged Flow-table

d.1. Primitive Flow-table

0

(R1 = cr1.a1.a2')

R1 = a1

a. Sequence

e. Merge Diagramj. Relays Ladder Diagram

CONTROL

1

cr1

START

-

-

A+ = cr1'

A+ = START.a1 + a1'.cr1'

a1

1

(S1 = cr1'.a1'.a2)

3

4

1

A+

e. Merge Diagram

i. Output Tables

SYSTEM

A+

A+

START

-

f. Selected Groups

cr1

0

SYSTEM

3

CONTROL

h States Assignment

01

A-

1


a2

Fig. 5-22 : Sequence A+,A- (Huffman Method)

-

d.1 . Primitive Flow-table

-

(R1 =cr1. a1.a2')

cr1

{1,2) , (3,4)

1

(With Returned Springs)

a1

a1cr1

(Without Returned Springs)

S1 = a2

A- = cr1A+ = START.a1

A+ = cr1'R1 = a1

Fig. 5-21 : Sequence A+,A- (Huffman Method)

-

-

-

-

-010

0-

- ----

0- - ---

-

-

0

0

0

-

c. Primitive Flow-diagram

1


-

5-7START , A+ ,A-

1 10/1

24

3

00/1

01/0

00/0

A+

01 110010

01 110010

01 110010

a1,a2

a1,a2a1,a2

0

1

CR1

A+

CR1

1

2

3

4

1

2

3

4

a1,a201 110010CR1

a1,a201 110010CR1

a1,a201 110010CR1

0

1

0

1

0

1

a1,a201 110010

a1,a201 110010CR1

1

0

A+ A-

START 1 10/1

24

3

00/1

01/0

00/0

A+

A-

CR1

4

21

3

3

1 -

-

4

21

3

4

2

1

3

10

-0

01

0-

-

2

- -

-

3

4

1

- -

-

4

1

2

3

0100 11a1,a2

10

1 2 3 -

1 34 -

3

1 -

-

10

1

11

0

CR1 00a1,a2

01

4

21

3

-

10 00 1101a1,a2

-

-

4

-

3

-32

2

-

1

- -41

01 110010a1,a2

-

2

- -

-

3

4

1

- -

-

4

1

2

3

,1

,1

,0

,0

a. Sequence

-

-

-

START

START

START

a. Sequence


e. Merge Diagram


h. States Assignment

i. Output Table

j. Exitation and Output Functions

cr2

cr3

cr1


A+a1a2

STARTCONTROLSYSTEM


Fig. 5-23 : Sequence A+,A-,A+,A- (Huffman Method)

A+


-

-

1 1

0 0

-

-

-

-

1 1

0 0

-

-

A+ = cr1 + cr3A+ = START.cr1.a1 + cr1.a1' + cr3

a2cr1 cr3

cr4a1cr2

cr3 cr1a2

cr2

cr3

cr4

a1

a1 cr2 cr3

cr1

cr1 a1f . Selected Groups{1,2) , (3,4) , (5,6) , (7,8)

START , A+ , A- , A+ , A-

S1 = cr4.a1S2 = cr1.a2S3 = cr2.a1S4 = cr3.a2

R1 = cr2R2 = cr3R3 = cr4

S1 = a1(cr2+cr3)' = a1.cr2'.cr3'

(R1 = cr2.a2)(R2 = cr3.a1)(R3 = cr4.a2)(R4 = cr1.a1)R4 = cr1

(With Returned Springs)

cr2

cr3

cr1

A+ , A-

10 -0

0- 01

-

A+ = cr1 + cr3A+ = START.cr1 + cr3

a2cr1 cr3

cr4a1cr2

cr3 cr1a2

cr2

cr3

cr4

a1 cr2 cr3

cr1

10 -0

0- 01

A+ A-

0

0

0

1

0

1

1

00

1

00

A- = a2

a2

-2

3

4

5

8

1

6

7

a. Sequence




e. Merge Diagram

f. Selected Groups

g. Merged Flow-table h. States Assignment

i. Output Tables

j. Exitation and Output Functions


a1a2

STARTA+A-

3

5

-

7

1

-

--

-

- -----

- -------

-------

- - ---

Fig. 5-24 : Sequence A+,A-,A+,A- (Huffman Method)

(Without Returned Springs)

---

- -

- -

- -

--

- -

--

--

--

--

-

1

5

3

7

-START , A+ , A- , A+ , A-

{1,2) , (3,4) , (5,6) , (7,8)

S1 = cr4.a1S2 = cr1.a2S3 = cr2.a1S4 = cr3.a2

R1 = cr2R2 = cr3R3 = cr4

S1 = a1(cr2+cr3)' = a1.cr2'.cr3'

(R1 = cr2.a2)(R2 = cr3.a1)(R3 = cr4.a2)(R4 = cr1.a1)R4 = cr1

CONTROLSYSTEM

5-8

1110 0100a1,a2

1110 0100a1,a2

CR1

CR2

CR3

CR4

1110 0100a1,a2

CR1

CR2

CR3

CR4

CR

1110 0100

CR1

CR2

CR3

CR4

CR 1110 0100a1,a2

CR1

CR2

CR3

CR4

CR

1110 0100a1,a2

CR1

CR2

CR3

CR4

CR1110 0100a1,a2

1 2

34

5

8 7

6

3

5

7

1

1 2

34

5

8 7

6

1

2

3

4

56

7

8

1

2

3

4

56

7

8

CR1

CR2

CR3

CR4

A+

CR1

CR2

CR3

CR4

A+

A-

110/1

2 00/1

3 01/0

00/04

5 10/1

600/1

01/0 7

800/0

START 110/10

2 00/-0

01/013

00/0-4

8

6

01/01

5

00/-0

10/10

7

00/0-

101

-02

301

40-

510

6-0

017

80-

01 110010

a1,a2

a1,a2

-2

3

4

5

8

1

6

7

---

- -

- -

- -

--

- -

--

11

21

30

40

51

16

70

08

0010 1101

a1,a21110 0100

a1,a2

CR1

CR2

CR3

CR4

CR

1 2

34

5 6

78

--

-

1

5

3

7

-1 2

34

5 6

78

Lcr2

cr2

CR2

M

F

CR1

Tmr

cr1

START

D

L

cr1

H

cr3

CR3

cr2

cr1

T

cr3

cr3

cr2

00 10 11 01

00

01

11

10

L.H

5

1

44

6

6

3

2

5

2

3

1

1 2

6

4

5

3

00 10 11 01

00

01

11

10

L.H

00 10 11 01

00

01

11

10

L.H

00 10 11 01

00

01

11

10

L.H

cr3

00 10 11 01

00

01

11

10

L.H

START , F ,

1. Sequence starts by pressing START buttom. This opens FIll valve.

M'

Level SwitchL (Low)

Level SwitchH (High)

MMixer Motor

DDrain Valve

D'

Fill ValveF

F'

M

TMR

D(H) (T) (L')

M'START

TMR

DF'

M, F ,

I I I I I I VI

a. Process presentation and requirements definitions

b. Process Sequence

c. Groups Partition

d. Cascade Contacts Circuit

2. Liquid fills tank until HIGH level switch is operated.

,,

3. At that time FILL valve is closed, mixing motor is turned on, and a timer is activated4. On timeout, motor is turned off, and DRAIN valve is opened.5. When tank is empty, LOW level switch is opened, and DRAIN valve is closed.

Cascade Method

Fig. 5-26 : Automatic Mixing System

Huffman Method

5

4

6

-

CR

3

000 100 110 111 101

1

0

2

F D M Ymr

- - -

---

- -

-

-

- -

-- -

-

-

-

1

1

1 1

1 1

1

1

0 0 0

000

0 0

0

0

0

0

0

0

0

5 3

4

26

{1 , 2 , 3} , {4 , 5 , 6}

-

-1

4

000 100 110 111 101

1

4

- -

-

-

-

--

-

a. Process definitions

Process is same as defined ai Fig. 6-25/a .

b. Primitive Flow Table

c. Merge Diagram

d. Selected Groups Partition

f. "Path" Map

e. Merged Flow Table

M TMR

F D

g. Output Tables

0-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

- -- -

- - - -

1 1 0

0

0 0

(0)

-

-

-

-

-

-

-

-

0 0 0

1

1 1-

0 0 1

0

0 --

(0)

0 0

0

0

1

1

(1)

(0)

0

START START

S = L'.STARTR = tmr

F = H'.CRD = L.CR'

M = HTMR = H

h. System Functions

, D'

Fig. 5-25 : Automatic Mixing System

1

MIXINGSYSTEM

TMR

FLH

DM

Timer

T

LHT

LHT

1

CR,T

A mixing system requires filling a tank with liquid, mix it for aspecific time and then drain the liquid out.

An automatic process is represented as follows :

Start

CR,T

CR,T CR,T

5-9

CR,T

01 11 1000

a1,a2

CR1

CR2

CR3

CR4

CR01 11 1000

a1,a2

CR1

CR2

CR3

CR4

CR a1 a2

A+ A-a1 a2

1

2

3

4

1

a1 a2

3

A+ A-

4

2

a1.b1 a2.b1 a2.b2 a1.b2

a1 a2 a1 a2

1 2 3 4 5 6 7 8 1 1 2 3 14

a. Sequence Inputs b. Ignore Input 00

a1

a2

----

1

1

a1.a2'.F a1.Fa1'.a2.F a2.F

Column 00 not requiredColumn 11 merge

a. Column 11 Merge b. Reduced Columns

c. Pseudo Map

Fig. 5-27 : Full/Partial Input Stream (A+,A-,A+,A-)

Fig. 5-28 : Full/Pseudo Karnaugh Maps

a. Primitive Flow Table b. State Assignment

2

3

4

1

1

1

1

1

0

0

0

0

CR1

CR2

CR3

CR4

Fig. 5-29 : Pseudo Map For A+,A-,A+,A-

0

01

4

2

1 0

1

1

3 0

1

b1

b2

a1

a2

CR1

CR4

CR2

CR3

b1 b2

a1 a2 a1

CR1

R3 = CR4.a2

-

-

1

A+ = CR1+CR3

d. A- Map

S2 = CR1.a2

-

0

CR3

R1 = CR2.a21 -

1

1A- = a2CR4

R4 = CR1.a1

S1 = CR2'.CR3'.a1.Start

0

- -R2 = CR3.a1

S3 = CR2.a1

e. System Functions

0

CR2S4 = CR3.a2

0

-

c. A+ Map

Fig. 5-30 : Pseudo Map For 2 Cylinders & 4 States

d1

CR5

CR6

CR8

CR7

d2

c2c1 c1

b1 b2

CR4

CR2

CR1

CR3

a1 a1a2

Fig. 5-31 : Pseudo Map For 4 Cylinders & 8 States

CR4

CR2

CR1

CR3

10 00 01 00 10 00 01 00 10 100110 10015-10

0*

* Assigned "0" to "rest" state

a2.b1.c1 a1.b1.c1 a1.b2.c2 a2.b2.c1 a1.b1.c2 A+ A- B+ B- C+ C-

1

4

5

6

7

8

2

3

1

37

5

28

6 4

a2.b1.c1 a1.b1.c1 a1.b2.c2 a2.b2.c1

CR1

a1.b1.c2

CR2

CR3

1 2

3 45 6

8 7

78

6 5 4 3

2 1 CR1

CR2

CR3

CR1

CR2

CR3

CR1

CR2

CR3

CR1

CR2

CR3

CR1

CR2

CR3

CR1

CR2

CR3

CR1

CR2

CR3

CR1

CR2

CR3

CR1

CR2

CR3

CR1

CR2

CR3

CR1

CR2

CR3

CR1

CR2

CR3

CR1

CR2

CR3

CR1

CR2

CR3

1 2 3 4 5 6 7 8 1a2a1b2b1c2c1

START , A- , C+ ,, A- ,B-B+

C+ C-

A+C- , A+

a. Sequence Inputs

4

2

3

5

6

7

8

1

- - ------

--

--

--

-

---

-

--- -

-

1

1

1

1

1

1

1 1

11

0 0 0

000

0 0 0

000

0 0 0

000

0 0 0

000

- --

---

- -- -- -

- -

{1,2},{3,4,5,6},{7,8}{1,2},{3,7,8},{4,5,6){1,2,3},{4,5,6},{7,8}


c. Merge Diagram

3

d. Merge Options

Selected

1

7

-

--

-

e. Merged Flow Table

- ----

--

---

--

-

- --

-

-

- --

-

-

--

-

-

--

-

- --

--

--

-

-

- --

-

-

- --

-

-

--

-

-

--

-

- --

--

--

-

-

-

---

------

- -

-

A+ A-

B+ B-

C+ C-

1

0 0

00 --

1

1 00

0

----

--

1 0

0

00

0 0 0

0

0

0

0

1 --

---

--

--

1

1

1

1

0

0

0

0

0 0

0

0

0

---

----

--

A+ = CR3.c1+b2

B+ = CR1.a1A- = a2.b1

B- = a2

C+ = a1.b1(CR1+CR2)C- = c2

S1 = Start.a2.CR2'

S2 = b2S3 = b1.c2

R1 = b2R2 = b1.c2R3 = CR1.a2

(b2.c2) (a2.b2)

g. Output Mapsh. System Functions

a1

-

-

-b2

f. Path Map

-

c2

-7

-

b1

-

--

1

a1

-

-

3a2

--

Fig. 5-32 : Pseudo Karnaugh Map Example

b2b1

a2 a1a1

c2

b2b1

a2 a1a1

c1

b2b1

a2 a1a1

c2

b2b1

a2 a1a1

c1

b2b1

a2 a1a1

c1

b2b1

a2 a1a1

c2

b2b1

a2 a1a1

c1

b2b1

a2 a1a1

c2

b2b1

a2 a1a1

c2

b2b1

a2 a1a1

c1

b2b1

a2 a1a1

c2

b2b1

a2 a1a1

c1

b2b1

a2 a1a1

0

0

1

-

5-11

(a2.b1)(b2.c1)

(b1.c2)

c1

2

3

4

5

1Wait

F

F' M Ytmr

M' D

D'

START - L'

H

Ytmr

L'

Valve D is Closed

A1

A2

ZA1

ZA2

Xi-P

XA1

XA2

i+1 Zi+1

Aj ZAj

XAj

XAJ-1

....

.

Xi-P

ZB2B2

ZB1

XB1

XB2

B1

ZBk

XBk

Bk

XBk-1

....

.

END

Fig. 5-33 : GRAFCET forAutomated MixingSystem (Fig. 5-25)

"Ready" Signal

Zii

Xi+1

Fig. 5-34 : GRAFCET forAlternate Parallel Paths

A1

A2

ZA1

ZA2

Xi

XA1

XA2

i+1 Zi+1

Aj ZAj

XAJ-1

....

.

ZB2B2

ZB1

XB1

XB2

B1

ZBkBk

XBk-1

....

.

Zii

Xi+1

Fig. 5-35 : GRAFCET forSimultaneous Parallel Paths

XAj.XBk

5-1

2

2

3

4

5

1Wait

F

F' M Ytmr

M' D

D'

START - L'

H

Ytmr

L'

Valve D is Closed

A1

A2

ZA1

ZA2

Xi-P

XA1

XA2

i+1 Zi+1

Aj ZAj

XAj

XAJ-1

.....

Xi-P

ZB2B2

ZB1

XB1

XB2

B1

ZBk

XBk

Bk

XBk-1

.....

END

Fig. 5-33 : GRAFCET forAutomated MixingSystem (Fig. 5-25)

"Ready" Signal

ZB1i

Xi+1

Fig. 5-34 : GRAFCET forAlternate Parallel Paths

A1

A2

ZA1

ZA2

Xi

XA1

XA2

i+1 Zi+1

Aj ZAj

XAJ-1

.....

ZB2B2

ZB1

XB1

XB2

B1

ZBkBk

XBk-1

.....

Zii

Xi+1

Fig. 5-35 : GRAFCET forSimultaneous Parallel Paths

XAj.XBk

5-12

\

Plate Rotated

1

2

Start AND Initial Conditions

Loader Retracted Drill Down

Gauge Down AND T<2s

Wait

9

12

Wait

Fig. 5-37 : GRAFCET for Drilling Station

Gauge Up

RetractLoader

AdvanceClamp

DiscendDrill3

14

5

6

Wait

(From Telemechanique TSX T607 Manual)

DiscendGauge

RaiseGauge

RetractClamp

Gauge Up

AdvanceLoader

11

8

Drill Up

167

13 RetractEjector

Piece Loaded

Piece Ejected

10

AdvanceEjector

Piece Unclamped

RaseDrill

RaiseGauge

Ejector Retacted

RotatePlate

15

17

4

Piece Clamped

=1

T=2s

T>2s

Manual Reset

5-13

CHAPTER 6

SEQUENTIAL SYSTEMS WITH RANDOM INPUTS

Random Signals Examples Design as Input to PLC System

1

X2

00 10 11 01X1,X2

2

00/01

CR

Z

4

10/02

4

1

11/03

3

1

01/04

2

5

3

5

X1

X2

01/15

Z

5

CR1

2

X1

3

CR

4

THOCKNESSDETECTORSYSTEM

Photocell 1

Photocell 2

X1

X2T Reject Door

{1,2,5},{3,4}

b. System Block Diagram


c. Primitive Flow Diagram

d. Primitive Flow Table

e. Merge Diagram

f. Merge Options

g. Selected Options

h. Merged Flow Table

1. Different size elements are transferred on a conveyor belt.2. All elements that are below specific thickness must be rejected.3. Reject is performed by opening a reject door - Z=1.4. Photocells X1 and X2 are placed in specific locations.5. X2 is covered by all sizes. X1 is covered by elements over

2

3

- 4

1

1

-

-

-

-

0

0

1

5

-

0

-

-

-

{1,5},{2,3,4}

{1,5},{2,3,4}

specific thickness.X2X1

0

2

1

5

34

1

2 -00 10 11 01

i . State Assignment

1

2 -0

1

X1,X2

00 10 11 01X1,X2

CR

(S = X1.X2')R = X1'.X2'

CR 00 10 11 01

1

-0

X1,X2

0

0 0 0

1(0)

(0)

j. Output Table

Z = X2.CR'

k. System Functions

S = X1

S

R

Q

Q'

X1

X2

Z

Fig. 6-1 : Thickness Detector System Design

l . Relays Implementation

m. Gates Implementation

(CR = Q)

6-1

40

1

CR1

2

4

00 01 11 10

0

1

CR1

AB

1 2

3

1

00/0

4

31

21

3 11/1

10

2 01/1401/0

5 01/1

51

5

3

00 01 11 10AB

00 01 11 10

1 2

34

00 01 11 10

5

5

c. Flow-diagram (primitive)

2

3

4

1

-

- -

5

--

- -


e Merge Diagram

h. Merged Flow-table

3

i . States Assignment

j. Output Table

0 1

0 1

S1 = ABR1 = B'

A

L = A + CR1'.B

B

CR1

LA

B

CONTROL

S Y S T E M


Fig. 6-2 : Traffic-Light Control System Design

L

- 3-

g. Selected Groups

{1,2,5) , (3,4)

{3.,4,5) , (1,2)

One of the tracks is connected to common node (Ground), while the other track is splitted - within the junction area - into 3 sections, that are physically joined, but electrically isolated from the tracks outside the junction area.Mid-section is also isolated from the other 2 sections (that are connected electrically).

When the junction area is empty (no trains inside) all 3 sections are disconnected from common track, thus providing"0" signal on each section.

Junction Area

A B

When the train crosses a track section, it connects it electrically to the common track, thus changing its signal into "1".Signal returns to "0" as soon as last waggon leaves the appropriate section.Signaling control system senses A and B signals, and turns red light on or off, accordingly.

Trains may go in two direction, but the following assumption are known :

* Only a single train crosses the junction area, at a time.* Train doesn't changes direction within the junction area.

a. System description

k. Control Functions

l. System circuit

AB/L

CR1

AB

L

L

L

L

RAILWAY

RO

AD

A red light signal is placed in the junction of road and raillway.

Junction Area

3

1

AB

0

1

CR1

B

A

L

(R1' = B)

f. Merge Options

{1,2,5) , (3,4)

1 5

5

1

B

(1)

(0)(0)

6-2Train must operate red light as soon as it enters "junction area", far from the junction, and turn it off as soon aslast waggon leaves the railway (near junction).

1

600/10

3

2311/01

4

CR3

3

410/01

5

4

5

6

CR3

CR2

6

CR1 CR1

100/00

CR2 CR2

CR3

210/10

1

CR1

501/00

2

ALARMSYSTEM

Danger Signal

Confirmation

X1

X2

Z1

Z2

ALARM SIREN

ALARM FLASH

2

3

4

5

6

5

31

1 3

52

-

-

-

-

-

-

1

1

1

0 0

0

0

0

0 0

0

1

2

3

4

5

6

{3,4,5} {2.6} {1}

{1,5} {2.6} {3,4}

{1,5} {2.6} {3,4}





e. Merge Diagram

f. Merge Options

g. Selected Options

2 3

5

1

3

h. Merged Flow Table &

5

00 10 11 01 z1 z2

1. External alarm sets X1=1. It must activate siren Z1, until

2. Operator confirms by pressing X2 buttom. This de-activates siren.3. If alarm signal still exists, flash light is activated.4. After confirmation, flash also is de-activated.

operator confirmation

States Assignment

00 10 11 01

00 10 11 01

(0)0

00

0

1 1

-

-

(0)

(0)

(0)

00 10 11 01

0 0

0 0

1 1

(0) -

- (0)

- -

i. Output Table of Z1 j. Output Table of Z2

S1 = X1'.X2'.CR2' + X1'.X2 = X1'(X2 + CR2')

S2 = CR1.X1.X2'S3 = X1.X2

R1 = CR2.X1.X2' + X1,X2 = X1(X2 + CR2)R2 = X1'.X2 + X1.X2 = X2R3 = CR1.X1'.X2' + CR1.X1'.X2 = CR1.X1'

Z1 = CR2.X2'Z2 = CR3

k. Exitation & Output Functions

Fig. 6-3 : Alarm System Design

*

1

6-3

3

6

73

4

1

8

2

5

00 01 11 10

A B00 01 11 10

A B

6

210/0

311/0

401/0

5

100/0

600/1

811/1

2

501/1

D

3

7

8

1

4

710/1

00 01 11 10

AB

1

7

6

5

28

4

g. Merged Flow-table &State Assignment

6

7

2

3

1

5

4

8CR1

CR2

CR3

CR4

CR1

CR2

CR3

CR4

h. Output Table

D

S1 = CR4.A.B' + CR2.A'B'

S2 = CR1.AB' + CR3.A.'B'

S3 = CR2.A.B + CR4.A.B'

S4 = CR1.A.B + CR3.A'B

O

O

O

O

1

1

1

1

(0)(1)

(0)

(1)(0)

(1)

(1) (0)

D = CR1.B + CR2.A' + CR3.B' + CR4.A

R1 = CR2.A.B' + CR4.A.B

R2 = CR1.A'B + CR3.AB

R3 = CR2.A'.B' + CR4.A'B

R4 = CR1.A'.B' + CR3.AB'

j. Corrected System Initialization

S1 = A'B'.CR2'.CR3'

At that state, Flip-flop 1 must be set, with no confilict later,

Initially, while A=B=0, and all Flip-flops are in resetstate (CRi=0).

that is to say, while CR1 and CR2 are not set.

Fig. 6-4 : Motor Direction Detection System Design

i. Exitation and Output Functions

B

5

O

c. Contro,l System Block Diagram

- 4

A

e. Primitive Flow-table

5

a. Disk Partitions ans Sensors Arrangement

4

1

7

2

d. Primitive Flow-diagram

CONTROL

2

- O

1

7

SYSTEM

-

-

- 1

3

O8

-

D

-

-

O

1

6

6

B

1

3

8

1

A6-4

B

A

ChangeDirection 360

0

900

b. Encoder Code Waveforms for Both Directions

"UP" direction "DOWN" direction

(A leads B) (B leads A)

f. Merge Diagram

610/1

100/0

911/0

701/1

410/0

801/0

210/0

1010/0

311/0

511/1

T

1

2

3

4

5

6

7

8

9

10

7

3

21

9 108

6

4

5

c. Primit ive Flow Diagram

X2

1. A security door is controlled by two input switches : X1 and X2 .

Actually, door is opened when latest 5 inputs satisfy the sequence 00 , 10 , 11 , 10 , 11 , and closed as soon as

2. The door is opened and closed, by entering the following sequence :

X1,X2 = 00 , 10 , 11 , 10 , 11 ..... 00

Switch

TX1

a. System Definit ion


OpenDoor

Open (T=1) Close (T=0)

input becomes 00.

SwitchCombination Lock

Proper SequenceImproper Sequence


2-

-

-

-

-

-

-

-

-

-

3

4

67

10

8

8

8

5

5

5

1

1

1

1

1

1

9

9

0

0

0

0

0

0

0

1

1

1

00 01 11 10

2

1

5

3

e. Merge Diagram

6

4

10

9

7

8

5

8 4

00 01 11 10

3

-1

1

1

8

-CR1

CR2

CR3

CR4

CR5

S1 = X1'.X2'

S2 = CR1.X1.X2S3 = CR2.X1.X2'

S4 = CR3.X2

S5 = CR4'.X1'.X2

R1 = CR2.X1.X2 + CR5.X1'.X2

R2 = CR3.X1.X2' + CR5.X1'.X2R3 = CR4.X1.X2 +X1'.X2'

R4 = X1'.X2'

R5 = X1'.X2'CR5

CR2

CR3

CR1

00 01 11 10

CR4

0 0

0

0

0 0 0

1 1 1

- ----

---

- -

T = CR4g. Merged Flow Table& States Assignment

h. Output Tablei. System Functions

Fig. 6-5 : Combination Lock System Design

X1,X2 / T

X1,X2

X1,X2 X1,X2

{1,2},{3},{4},{5,6,7},{8,9,10}f . SelectedMerge Partit ions

6-5

PART 2 Chapters 7 - 12


CHAPTER 7 Pneumatic Control Circuits Fig. 7-1 7-1 Intuitive Design Of Sequence A+,B+,A-,B- Fig. 7-2 7-1 Intuitive Design Of Sequence A+,B+,B-,A- Fig. 7-3 (a-b) 7-1 Cascade Design Of Sequence A+,B+, B-, A-,C+.C- Fig. 7-4 7-1 Cascade Design Of Sequence A+,A-,A+,A- Fig. 7-5 7-1 Multiple Limit-Valves Replacement Fig. 7-6 7-2 Pneumatic Cascade Basic Concept Fig. 7-7 (a-c) 7-2 Pneumatic Cascade Group Configurations Fig. 7-8 (a-g) 7-3,4 Pneumatic Cascade Design Process Steps Fig. 7-9 7-5 Pneumatic Cascade Example 1 Fig. 7-10 7-5 Pneumatic Cascade Example 2 Fig. 7-11 (a-b) 7-6 Flip-Flop Valve & Steering Valve Fig. 7-12 7-6 Two Steering Valves Providing Three Addresses Fig. 7-13 7-6 Three Steering Valves Providing Four Addresses Fig. 7-14 (a-e) 7-6 Design Sequence A+,A-,A+,A-,A+,A- Fig. 7-15 (a-d) 7-6 Design Sequence A+,B+,A-,B-,(A+/B+),A-,B- Fig. 7-16 (a-e) 7-7 Design Sequence A+,B+,B-,C+,B+,B-,C-,A- Fig. 7-17 7-8 Simplified Input Map Fig. 7-18 (a-d) 7-8 Design a Sequence With Passive States Fig. 7-19 7-9 Examples of Complex Functions Fig. 7-20 7-9 Function Tables Background Fig. 7-21 (a-b) 7-9 Function Tables Arrangement Fig. 7-22 (a-b) 7-9 3/2 Valve Connections yielding Single Output Function Fig. 7-23 7-10 Valve Connections With 2 Separate Outputs, 2-Variables Input Fig. 7-24 7-11 Valve Connections With 2 Separate Outputs, 3-Variables Input Fig. 7-25 7-12 Valve Connections With 2 Separate Outputs, 4/5-Variables Input Fig. 7-26 7-13 Valve Connections yielding Flip-Flop Output Functions Fig. 7-27 7-14 Example 1 Fig. 7-28 (a-f) 7-14 Example 2 (Huffman Solution for Sequence A+,A-,A+,A-) Fig. 7-29 (a-h) 7-15 Solution for Sequence A+,B+,B-,A-,B+,B- Fig. 7-30 (a-c) 7-16 Stop-Restart With Single Button & Separate Buttons Fig. 7-31 7-16 Stop-Restart With Multiple Remote-Control Stop Buttons Fig. 7-32 7-16 Electronic Circuit for Fig. 7-31 Fig. 7-33 7-16 Emergency Stop Modes Definition Fig. 7-34 (a-d) 7-16 Pneumatic / Electric Fig. 7-35 7-17 Fig. 7-36 7-17 Fig. 7-37 7-17 Fig. 7-38 7-17 Fig. 7-39 7-17 Fig. 7-40 7-17

CHAPTER 8 Miscellaneous Switching Elements & Systems Fig. 8-1 (a-h) 8-1 Sequence Chart for Common Timers Modes Fig. 8-2 8-1 - Fig. 8-3 8-1 - Fig. 8-4 8-1 -Delay Off- Fig. 8-5 8-1 - Fig. 8-6 8-1 - linder Retraction Fig. 8-7 (a-b) 8-1 Sequence Charts for Pulse Shaper Fig. 8-8 8-1 Relay Pulse Shaper Fig. 8-9 8-1 Pneumatic Pulse Shaper Fig. 8-10 (a-c) 8-2 Basic Set-Reset Flip-Flop (SR) Fig. 8-11 (a-b) 8-2 Toggle Flip-Flop (T) Fig. 8-12 (a-d) 8-2 T Flip-Flop Implementation - Counters Fig. 8-13 (a-c) 8-2 D Flip-Flop Implementation Shift Register Fig. 8-14 8-3 10-Stage Shift Register Fig. 8-15 8-3 Shift Register With 4 Parallel Tracks Fig. 8-16 8-3 Schmitt-Trigger Response Fig. 8-17 8-3 Schmitt-Trigger Response to Fuzzy Waveform Fig. 8-18 8-3 Truth Table for Error-Checking of BCD code Fig. 8-19 8-4 Truth Table for 2-Out-of-5 Code Fig. 8-20 (a-d) 8-4 Use of Karnaugh Map to Obtain Cyclic Code Fig. 8-21 8-4 Reflected Cyclic Code for Six Numbers Fig. 8-22 8-4 Fig. 8-23 8-5 Binary 8-Section Encoder Fig. 8-24 8-5 Typical 8-Section Encoder Fig. 8-25 8-5 Single-Output Incremental Encoder Fig. 8-26 8-6 Two-Output Incremental Encoder Fig. 8-27 (a-j) 8-6 Motor Direction Detection System Design (Copy of Fig. 6-4) Fig. 8-28 8-6 Simplified Block Diagram of a Closed-Loop NC System Fig. 8-29 8-6 Block Diagram of Open-Loop NC System Fig. 8-30 (a-c) 8-7 Adder for 2-Bit Numbers Fig. 8-31 8-7 Iterative Adder Block Diagram Fig. 8-32 (a-c) 8-7 Iterative Binary Adder Design Fig. 8-33 (a-g) 8-8 Iterative Parity Checker Fig. 8-34 (a-f) 8-8 Iterative 2 Out of n Checker Fig. 8-35 (a-g) 8-9 Iterative Binary Numbers Comparator Fig. 8-36 8-10 Comparison Between Natural-Binary & Reflected Cyclic Code Fig. 8-37 8-10 Iterative Circuit for Translating Natural-to-Reflected Cyclic Code Fig. 8-38 8-10 Iterative Circuit for Translating Reflected Cyclic to Natural Fig. 8-39 8-10 Truth Table for Translating Natural-to-Reflected Cyclic Code

CHAPTER 9 Semi-Flexible Automation Hardware Programmers Fig. 9-1 9-1 Drum Programmer Fig. 9-2 9-2 Drum Programmer Solution Fig. 9-3 (a-b) 9-2 Patch Board & Matrix Board Fig. 9-4 (a-b) 9-2 Fig. 9-5 9-2 Schematic Representation of Programmable Counter Fig. 9-6 9-2 Programmable Counter With a Single-Cycle Start Mode Fig. 9-7 9-2 Sequence A+,B+,C+,A-,(B-/C-),A+,A- - No Return Springs Fig. 9-8 9-2 Sequence A+,B+,C+,A-,(B-/C-),A+,A- - With Return Springs Fig. 9-9 (a-e) 9-3 Programmer Based on 1/n Code Fig. 9-10 (a-e) 9-3 Programmer Based on 2/n Code Fig. 9-11 (a-c) 9-4 Programmable Counter Example 1 Fig. 9-12 (a-c) 9-4 Programmable Counter Example 2 Fig. 9-13 (a-e) 9-4 2/n Stability Cases Fig. 9-14 9-5 1/n Code Programmer for Two Simultaneous Parallel Paths Fig. 9-15 9-5 1/n Code Programmer for Two Alternative Parallel Paths Fig. 9-16 9-5 1/n Code Programmer With Skipped Steps Option Fig. 9-17 9-5 1/n Code Programmer With Repeated Steps Option Fig. 9-18 9-6 Flow Chart for Selecting System Design Method

CHAPTER 10 Flexible Automation Programmable Controller Fig. 10-1 10-1 Block Diagram of Programmable Controller (PLC) Fig. 10-2 10-1 PLC Classifications According to Size Fig. 10-3 10-1 Discrete Input Devices to PLC Fig. 10-4 10-1 Discrete Output Devices Actuated by PLC Fig. 10-5 10-1 Standard Discrete I/O Interface Modules Fig. 10-6 10-1 Type of Electronic Memories Fig. 10-7 10-1 I/O Connection Diagram Fig. 10-8 (a-b) 10-1 PLC- Different I/O Connections Locations Fig. 10-9 10-2 Typical PLC Memory Map Fig. 10-10 10-2 PLC Programming Languages Fig. 10-11 10-2 Ladder Diagram Section Appearing on Screen Fig. 10-12 10-3 PLC Configuration Fig. 10-13 10-3 Typical PLC Control System Fig. 10-14 10-3 PLC Network (Macro) Fig. 10-15 (a-e) 10-4 PLC I/O Variables Assignment Fig. 10-16 (a-g) 10-4 PLC Motor Control System Fig. 10-17 10-5 Forward/Reverse Circuit Fig. 10-18 10-5 Example of Ladder Diagram Segment Fig. 10-19 10-5 I/O Assignment for Fig. 10-18 Fig. 10-20 10-5 Ladder Diagram of Fig. 10-18 in PLC Format Fig. 10-21 10-5 PLC Program for Fig. 10-20 Fig. 10-22 10-5 Use of LIFO Memory Stack Fig. 10-23 10-5 PLC Program for Fig. 10-22 Fig. 10-24 (a-f) 10-6 PLC Cascade Design for sequence (A+/B+),C+,A-,C-,C+,(B-,C-) Fig. 10-25 (a-b) 10-7 Multiple Use of LIFO Stack Fig. 10-26 (a-b) 10-7 Rearrangement of Ladder-Diagram to Simplify Program Fig. 10-27 (a-b) 10-7 Timer Set for 20 Sec

Fig. 10-28 10-7 PLC Program for Fig. 10-27 Fig. 10-29 (a-b) 10-7 Counter Set to Count to 25 Fig. 10-30 10-7 PLC Program for Fig. 10-29 Fig. 10-31 (a-b) 10-7 PLC Light-Flash Program Fig. 10-32 (a-c) 10-7 PLC Up/Down Counter Program Fig. 10-33 10-8 Two-Hand Safety Circuit Using PLC Fig. 10-34 (a-b) 10-8 PLC Design for Sequence 6x(D+,D-),D+,10 sec delay.D- Fig. 10-35 (a-c) 10-8 Ladder Diagram and Program for sequence of Fig. 10-34 Fig. 10-36 (a-d) 10-9 Timers and Counters Fig. 10-37 (a-c) 10-9 Fig. 10-38 (a-c) 10-10 Master-Control-Relay Command (MCR) Fig. 10-39 (a-c) 10-10 Jump Command (JMP) Fig. 10-40 (a-d) 10-10 Fig. 10-41 (a-c) 10-10 Equivalent PLC and Relay Circuits Fig. 10-42 10-11 Effect of Scanning Action on Internal States of Relays Fig. 10-43 (a-b) 10-11 Importance of Proper Rung Order Fig. 10-44 10-11 Trigger Flip-Flop Circuit for PLC Fig. 10-45 10-11 PLC Sequence Chart for Fig. 10-44 Fig. 10-46 10-11 Analog Input Devices for PLC Fig. 10-47 10-11 Standard Analog-Input Interface Modules Fig. 10-48 10-11 Analog Output Devices Actuated by PLC Fig. 10-49 10-12 Standard Analog-Output Interface Modules Fig. 10-50 10-12 Storing an Analog Input Value Fig. 10-51 10-12 Fig. 10-52 10-12 Transferring a Word to Analog Output Module Fig. 10-53 10-12 Fig. 10-54 10-12 Fig. 10-55 10-13 Fig. 10-56 10-13 Fig. 10-57 10-13 Logic Operations Fig. 10-58 10-13 Data Commands Fig. 10-59 10-13 PLC Micro/Macro Definition Fig. 10-60 10-13 Several Possible LAN Topologies Fig. 10-61 (a-f) 10-14 PLC Design of Thickness Detector System Fig. 10-62 (a-e) 10-14 PLC Design of Traffic Light Control System Fig. 10-63 (a-l) 10-15 PLC Design of Alarm System Fig. 10-64 (a-e) 10-16 PLC Design of Motor Direction Detector System Fig. 10-65 (a-i) 10-17 Combination Lock System

CHAPTER 11 Introduction to Assembly Automation Fig. 11-1 11-1 Bladed Wheel Hopper Feeder Fig. 11-2 11-1 Central Board Hopper Feeder Fig. 11-3 (a-c) 11-1 Shape of Centerboard Slot Fig. 11-4 11-1 Rotary Centerboard Hopper Feeder Fig. 11-5 11-1 Design Sheet for Reciprocating Tube Hooper Feeder Fig. 11-6 11-1 Revolving Hook Hopper Feeder Fig. 11-7 11-2 Design Sheet for Tumbling Fig. 11-8 11-2 Magnetic-Disk Hopper Feeder Fig. 11-9 11-2 Vibratory Bowl Feeder Fig. 11-10 11-2 Design Sheet for Vibratory Bowl Feeder Fig. 11-11 11-2 Disk Feeder Fig. 11-12 11-2 Slide Escapement

CHAPTER 12 Robotics and Numerical Control Fig. 12-1 (a-b) 12-1 Cartesian Robot and Coordinate System Fig. 12-2 12-1 Cylinde Robot and Coordinate System Fig. 12-3 12-1 Spherical Robot and Coordinate System Fig. 12-4 12-1 Articulated Robot and Coordinate System Fig. 12-5 12-1 Robot Work Envelope Fig. 12-6 12-1 RCC Device

CHAPTER 13 Simester Exams 13-1 Simester Exam Example - Questions 13-3 Simester Exam Example Responses 13-7 Typical Simester Exam Questions - Questions

CHAPTER 7

PNEUMATIC CONTROL CIRCUITS

Pneumatic Cascade Design Pneumatic Flow Table Design Valves Function Tables Emergency Stop Modes

+ - + -

+ -+ -

+ - + -

+ - + -

+ -

+ -

+ -

+ - + -

+ -+ -

+ -

+ -

+ -

+ -

+-

+ + + +

CYLINDER "A" CYLINDER "B"a1 a2 b1 b2

A- A+ B-

Fig. 7-1 : Intuitive Design forSequence Start , A+,B+,A-,B-

CYLINDER "A" CYLINDER "B"a1 a2 b1 b2

START

A+A- B-

Fig. 7-2 : Sequence Start , A+,B+,B-,A-

B+ B+

START

START (A+) Conflicts With A- Actuation (by b1)More Conflicting States

A+A-

CYLINDER "A" a1 a2

B-

CYLINDER "B" b1 b2

B+

c1CYLINDER "C"

C-

c2

C+

21

III

Fig. 7-3 : Cascade Design for Sequence Start , A+,B+,B-,A-,C+,C-

A- A+

CYLINDER "A"

a1 a2

2

3

41

IIIIIIIV

Fig. 7-4 : Cascade System for Sequence Start , A+,A-,A+,A- (Cascade)

.....

Fig. 7-5: Multiple Limit Valves Replacement

Start , A+ , B+ , B- , A- , C+ , C-

I IIIa. Cascade Groups Partitioning

b. Cascade Circuit

7-1

+ -

+ -

+-

+ -

+ -

+ -

2

3

41

I

II

III

IV

2

31

I

II

III

21

II

I

Fig. 7-7 : Pneumatic Cascade Group Configurations

2 GROUPS

3 GROUPS

4 GROUPS

a. 2-Groups Manifold Lines Configuration

b. 3-Groups Manifold Lines Configuration

c. 4-Groups Manifold Lines Configuration

Pure pneumatic control systemSimplicity and realiabilityLimited to control cylinders with actuation valves that satisfy the following restrictions :

* Valves do not have return springs* Valves are operated pneumatically (no solenoids)

Group Partit ioning differences between pneumatic and relays cascade are :

* There is always an active group, even when not operating(START is also included within a group)

* Last Group may be merged with first group, provided that groups do not conflict

Fig. 7-6 : Pneumatic Cascade Basic Concept

7-2

+ -

+ -

+ -

+ - + -

+ -

+ -

+ - + -

+ -

A- A+ B- B+ C+C-

CYLINDER "A" CYLINDER "B" CYLINDER "C"a1 a2

b1 b2

c1 c2

START

1. System consists of 3 cylinders, each equipped with limit-valves

A- A+

B- B+

CYLINDER "A"

CYLINDER "B"

a1 a2

b1 b2

3. A two-input OR gate for each valve control.

1. cylinder actuated by valves without return springs.

2. A set of two limit valves.

Fig. 7-8 : Pneumatic Cascade Design Process Steps

c. Single-Cycle Cylinder Requirement

d. Two-Cycle Cylinder Requirement

2. Cylinders "A" and "C" perform single cycle (each), and require a single set of limit valves.

3. Cylinder "B" performs two cycles, and requires two sets of limit-valves, and OR valves.

4. A START valve is also required.

e. System Cylinders Requirements

2. Two sets of two limit valves.

1. cylinder actuated by valves without return springs.

START,C+

, B-,B+

A-,

B-

C-

B+

II III IV

A+,START,C+

, B-,B+

A-,

B-

C-

B+A+,

ORIGINAL SEQUENCE SEQUENCE GROUPS

b. Sequence Groups Part ioning

Ia. Process Sequence Definit ion

7-3

+ -

+ -

+ -

+ - + -

+ -

+ -

+ -

+-

+ -

+ -

+ -

+ - + -

+ -

+ -

+ -

+-

1

I

II

III

IV

A- A+ B- B+ C+C-

START,C+

, B-,B+

A-,

B-

C-

B+

II III IV

A+,

I


b1 b2c1 c2

START

2

3

41

I

II

III

IV

A- A+ B- B+ C+C-


b1 b2c1 c2

START

f . System Components

g. Complete System

Fig. 7-8 : Pneumatic Cascade Design Process Steps (Cont'd)

2

3

4

7-4

+ -

+ -+ - + -

+ -

+ -

+ -

+ -

+ -

+ -

+ -+ - + -

+ -

+ -

+ -

+ -

B-

1

START

b2a1

A- C+

CYLINDER "A"

2

II

A+

I

c2b1

CYLINDER "C"

B+

c1a2

C-

CYLINDER "B"

(from semester exam September 2002)

D+

d2CYLINDER "D"

d1

D-

A- ,A+

B+START , , B- ,

C-

D-

D+

C+,

I III

A- ,A+

B+START , , B- ,

C-

D-

D+

C+,

Fig. 7-9 : Pneumatic Cascade Example 1

III

B-

START,

1

I

C+

START

B+,

b2a1

A- C+

CYLINDER "A"

2

II

A+

C-

I

,

c2

3

b1

CYLINDER "C"

B+

A+,B-

III

A-

c1a2

II

C-

CYLINDER "B"

START,C+

B+,C-

,A+,B-A-

(from semester exam July 2002)

Fig. 7-10 : Pneumatic Cascade Example 2

7-5

+-

+-

+-

+-

+-

+-

+-

1

2

3

4

5

6

1

2

3

4

5

6

+- +-

+- +-

1

1

3

5

4

6

7

+-+-

+-

+-

+ +

R S

R S

y'y

c2

c2.y'c2.y

a. Flip-Flop Valve

b. Steering Valve

Fig. 7-11 : Flip-Flop Valveand Steering Valve

R2 S2

c2.y1.y2'

S1

c2.y1'

c2

R1

c2.y1.y2

S2

c2.y1.y2'

R2

R1

c2

S1

c2.y1'

R3

c2.y1.y2.y3'

S3

c2.y1.y2.y3

Fig. 7-12 : Two SteeringValves providing 3addresses

Fig. 7-13 : Three SteeringValves providing 4addresses

a1 a2 A+ A-

1

1

1

1

1

1

R3y1'

R2y3'

R4y1.y2'

S2y3.y4'

S4

a1 a2 A+ A-

R1y3.y4

y1.y2

S3

1

1

1

1

1

1

b. Flow Table c. Complete Flow Table

S1= a2.y3'

R1 = a2.y3.y4S2 = a2.y3.y4'R2 = a2.y3'

S3 = a1.y1.y2'R3 = a1.y1'

S4 = a1.y1.y2R4 = a1.y1.y2'

A+ = a1.y1'.Start+a1.y1.y2'+a1.y1.y2 = a1.y1'.Start+a1.y1A- = a2.y3'+a2.y3.y4'+a2.y3.y4 = a2.y3'+a2.y3 = a2

d. Exitation and Output Functions

S2

a1.y1.y2'

R2

a1.y1.y2

S4

a2.y3.y4'

R4

a1.y1'

S1

a1

R1

a1.y1A+

S3

R4

S4

START

a2.y3'

S3

a2

R3

S1

R2

A-

a2.y3

a2.y3.y4S2R1

R3

e. Control Circuit

Fig. 7-14 : Pneumatic Flow-Table Design forsequences START,A+,A-,A+,A-,A+,A-

a. Process sequence

START,A+,A-,A+,A-,A+,A-

1

A-a1.b1 A+

b. Complete Flow Table

S1 = a1.b2.y3'

R1 = a1.b2.y3 R2 = a2.b1

S3 = a2.b2.y2

R3 = a2.b2.y2'

A+ = a1.b1.y1'.Start+a1.b1.y1 = a1.b1.Start+a1.b1.y1A- = a2.b2.y2'+a2.b2.y2 = a2.b2

c. Exitation and Output Functions

d. Control Circuit

a. Process sequence

START,A+,B+,A-,B-,A+B+

,A-,B-

Fig. 7-15 : Pneumatic Flow-Table Design forA+B+

,A-,B-

y1'

R2

R3y2'

y1 s2

y3' S1

a2.b1 a2.b2 a1.b2

1

1

1

11

1

1

S2 = a1.b1.y1

B+ = a2.b1+a1.b1.y1

B- = a1.b2.y3'+a1.b2.y3 = a1.b2

y2 S3

y3 R1

Sequence START,A+,B+,A-,B-,

(a2.b1)

R3

a1

b1

a1.b1.y1a2.b2.y2'

b2

B-

R3

S1S3

a1.b2

a1

R2

B+

S2

a2

S1R1 R2 S3

a1.b1.y1'

(a1.b1)

R1

S2

b2

a2.b2.y2

A+

a2

A-

a1.b2.y3'

a2.b2

a1.b2.y3

7-6

S1

B+ B-

+-

1

2

3

4

5

6

7

8

+-

+-

+-

+-

a2

b2

c2

a1

c1

b1b1

+

b. Complete Flow Table

S1 = b2.c1

A+ = a1.START

d. Exitation and Output Functions

e. Control Circuit

a. Process sequence

START,A+,B+,B-,C+,B+,B-,C-,A-

Fig. 7-16 : Pneumatic Flow-Table Design for Sequence START,A+,B+,B-,C+,B+,B-,C-,A-

a2

S1

a2.b1.c1

R1

a1.b1.c1

1

a2.b1.c1 a2.b2.c1 a2.b1.c2(a1)

R1

a2.b2.c2(b2.c1) (b1.c2) (b2.c2)

y1'S1

y1.y2' R3

y3'

S3

y3 S2

R2

y1.y2

A+ A- B+ B- C+ C-

1

1

1

1

1

1

1

S2 = b1.c2.y3 S3 = b2.c2R1 = a1 R2 = b2.c1 R3 = a2.b1.c1.y1.y2'

A- = a2.b1.c1.y1.y2

B+ = a2.b1.c1.y1'+b1.c2.y3' B- = b2.c1+b2.c2 = (b2)

C+ = a2.b1.c1.y1.y2' C- = b1.c2.y3

(b1.c2)

b1

c1

S3R3

(b1.c1)

c2

B+ R3

a2.b1.c1.y1.y2'

A-

S2R2

a2.b1.c1.y1.y2

C+

a2.b1.c1.y1'b1.c2.y3'b1.c2.y3

C-S2

b2

c1

(b2.c1)(b2.c2)

S3 R2S1 B-

a1

A+ R1

c2

X X XXX

a1 b1 c1 a1a2 b2 c1 b2 a1a2 b1 c2 b1 c2a2 b2 c2 b2 c2

c. Simplifiying Input Map

7-7

1

1

3

4

5

6

7

8

9

10

11

12

a2

b2

c2

a1

c1

b1b1

c1d2

d1

a2

b2

c2

a1

c1

b1b1

c1d2

d1

+ -

1

A-a1 A+

Fig. 7-18 : Design a Sequence With Passive States

y1'

P

Py4'

S1

a2 a3 a4

1

1

1

y1.y2' S4

y4 S2

S3

y3 R1

R3R4

y3'

R2

y4' P

y3' P

y3' P

y3' P

y1.y2

S1 = a4 S2 = a3.y4 S3 = a1.y1.y2R1 = a2.y3 R2 = a4 R3 = a1.y1'

S4 = a1.y1.y2'R4 = a1.y1'

A+ = a1.y1'.START+a2.y1 = A- = a4+a3.y4+a2.y3

START,A+,(a4),A-,A+(a3),A-,A+,(a2),A-

1

1

X X X X

X

X

a1 b1 c1 d1 e1 a1

a1 b1 c1 d1 e2 a1 e2

a2 b1 c1 d1 e2 a2 b1 c1 d1

a2 b2 c1 d1 e2 b2

a2 b1 c2 d1 e2 c2

a2 b1 c1 d2 e2 d2

Fig. 7-17 : Simplifiying Input Map for Sequence

START,E+,A+,B+,B-,C+,C-,B+,B-,D+,D-,A-,E-

e1 e2

a1 a2 a3 a4

a. Cylinder Type

b. Required Sequence

c. Simplified Flow-Table

d. System Functions

7-8

= a1.START+a2.y1

+ -

+ -

+ -

+

+

+

+ -

+ -

+ . ..

1

2

3

4

5

6

7

8

9

YES

NOT

AND

AND

OR

OR

INHIBITION

IMPLICATION

SELECTOR

T = A+B

Function Name

T = A

T = AC+AC'

T = A'

T = AB

T = AB

T = A+B

T = AB'

T = A+B'

A 1 0

A 0 1

B A 0

B A B

B 1 A

B B A

B 0 A

B A 1

C A B

LineNo.

BooleanFunction P 2 3

32

P

T

Efficient Use of Directional-Control

Valves in Fluid-Logic Circuits

Various types of directional-control valves have been systematically analizedto determine the logic output functions obtained for different input-signalcombinations. It was found that a surprisingly large variety of fairly complexlogic functions can be obtained with a single valve.The results are summarisedin five tables which include 186 (i.e. all the significant) input-signal combinations.Several examples are presented, il lustrating how the tables can be used toimplement given fluid-logic functions with a minimum number of valves.It thus becomes possible to exploit the logic capacity of these valves to their

D.W. PessenAssociate ProfessorDept of Mechanical Engineering,Technion - Israel Institute of Technology,Haifa, IsraelMem ASME

1 A 0

B

A+B AB

1A0

B

A+B'A.B'

AA

C

B

AC'+BCAC+BC'

Fig. 7-19 : Examples ofComplex Functions

b. Tables List

Fig. 7-20 : Function Tables Background

a. 3/2 Valve , Single Output Function

b. Two Separate Output Function, 2 Input Variables

c. Two Separate Output Function, 3 Input Variables

d. Two Separate Output Function, 4/5 Input Variables

e. Two Separate Flip-Flop Output Function

a. Function Search Order

1

2

3

4

5

6

7 SELECTOR

INHIBITION

OR

YES

NOT

AND

IMPLICATION

Fig. 7-21 : Function Tables Arangement

7-9

2 3

P

P

2 3 4

T1 T2

2 3

S

T T

R

32 4

T1 T2

S R

Fig. 7-22 : 3/2 Valve Connections yielding Single Output Functionand Valves Pins Assignment

b. 3/2 Valve Connections yielding SingleOutput Function

3/2 Valve Gate 3/2 Valve Flip-Flop

5/2 Valve Gate 5/2 Valve Flip-Flop

6/2 Valve Gate 5/3 Valve Gate

a. Valves Pins Assignment

32 432 54

P

fullest extent, which can result in considerable reduction in the number of valves.

P1 P2

Note : U

se of shuttle valves is uaually less expensive.

No. FUNCTION NAME BOOLEAN

FUNCTION 1 BOOLEAN FUNCTION 2

Valve 5/2 P 2 3 4

Valve 6/2 P 2 3 4 5

Valve 5/3 P1 P2 2 3 4

59 60 61 66 70 73 75 79 81 84 85 86 87 90 91 94 95 96 97 99 100 101 103 104 105 107 109 110 112 113 114 115 117 118 119 120 121 122 127 128 129 131 132 133 134 135

YES/SELECTOR NOT/SELECTOR AND/OR AND/AND AND/INHIBITION AND/IMPLICATION AND/SELECTOR AND/SELECTOR OR/OR OR/OR OR/INHIBITION OR/INHIBITION OR/IMPLICATION OR/SELECTOR OR/SELECTOR OR/SELECTOR OR/SELECTOR INHIBITION/INHIBITION INHIBITION/INHIBITION INHIBITION/IIMPLICATION INHIBITION/IIMPLICATION INHIBITION/SELECTOR INHIBITION/SELECTOR IMPLICATION/IMPLICATION IMPLICATION/IMPLICATION IMPLICATION/SELECTOR IMPLICATION/SELECTOR SELECTOR/SELECTOR AND+AND/AND+AND AND+AND/AND+ AND+AND/INHIBITION AND+AND/IMPLICATION AND+INHIBITION/AND+INHIBITION AND+INHIBITION/INHIBITION+ AND+INHIBITION/OR AND+INHIBITION/AND AND+INHIBITION/INHIBITION AND+INHIBITION/IMPLICATION AND+/AND+ AND+/INHIBITION AND+/IMPLICATION INHIBITION+/INHIBITION+ INHIBITION+/OR INHIBITION+/AND INHIBITION+/INHIBITIOM INHIBITION+/IMPLICATION

T2=C

T2=AB T2=AC T2=AC T2=AC T2=BC T2=AC T2=B+C T2=B+C T2=B+C T2=B+C T2=A+C T2=A+C T2=A+C T2=B+C T2=B+C

T2=AB+AC T2=AB+AC T2=AB+AC T2=AB+AC

T2=A+BC T2=A+BC T2=A+BC T2=

T1=B+C T1=BC T1=BC

T1=A+C T1=A+C

C

T1=AC+BC T1=A+BC

T1=B+C T1=BC

T1=C+AB

T1=B+C T1=BC

B A B C C A 0 B C A B 0 C B 1 A C 1 A B C C A B C 0 A B C A B 1 C A B A

C A B 1 0 C A B 0 1 C A 0 B 0 C A 0 B 1 C A B A 0 C 1 B 1 A C C B C A C 1 B 0 A C C B 0 A C 1 B A B C C B A B C 0 A 0 B C 0 A B 1 C 0 B A B C A 1 B 1 C A B A 1

B C 0 A 0 B C 0 A 1 B C 1 A 1 C A A B C C A A B A C A A B 0 C A A B 1 B C A 0 A B C A B A B C A B C B C A 0 B B C A B 0 B C A 0 1 A C A B C A C A B 0 A C A B 1 C B A 1 A C B A 1 B C B A B C C B A 1 0 C B A B 1

Fig 7-24 : Valve Connections Yielding 2 Separate Output Functions, 3 Variables

7-11

3/2 Valve 5/2 Valve No. Output 1 Output 2 2 3 2 3 4 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186

No Input Variables T=y

T1=y

One Input Variables

T=Ay

T1=Ay T1=Ay T1=y

T=A+y T1=A+y

T1=A+y

Two Input Variables T1=Ay

T1=A+y

nput VariablesThree I

T2=y

T2=Ay

T2=A+y T2=y T2=A+y

T2=Ay

T2=B+y T2=By

1 0 A 0 0 A A 1 1 A A B

0 1 0 1 0 1 0 A 0 A 0 A A 0 1 1 0 A 1 A 1 A 1 A A 1 0 0 1 A 0 A 1 1 A 0 A 0 B A 1 B A B 0 A B 1 0 A B 1 A B A B A A B C

Fig. 7-26 : Valve Connections Yielding Flip-Flop Output Functions

7-13

+-

1

2

+-

+-

162

166

+ -

180

+-

166

S1

S2

R1

R2

A+

S2 R2

a1

R1

S1

y1y1'

y1.y2'+y1'.y2

a1.y2

a1.y2'

S1 R1

a2

A-

R2 S2

a2.y1a2.y1'

Start.a1.y2'

S1=Start.a1.y2'

S2=a2.y1

R1=a1.y2

r2=a2.y1'

A+ = y1.y2'+y1'.y2

START,A+,A-,A+,A-

a. Process Sequence

C. Huffman Method Solution

CONTROLSYSTEMa1 A+


Start

a2

a1 CONTROLSYSTEM

d. System Solution Block Diagram

Start

a2

S

R

Y

Y'

S

R

Y

Y'

S1

R1

S2

R2

Y1

Y2

* Function that contain internal variables (y)

variables, so they are to be searched in fifth table* In current system, all functions contain internal

f. System Valve Circuit


Required Functions

F1 = X1.X2'F2 = X1.X2 + X2'.X3

F1 is Inhibition Function

Search in 3-variables tableFound Functions 101 and 103

1 X1

X2

F2 = X1.X2 + X2'.X3F1 = X1.X2'

F2 is Selector Function

Only 101 satisfies requirements

* S1,R1,S2,R2 are Set/Reset of those flip-flops

* Functions that contain only external variablesare to be searched in first 4 tables

e. Design Considerations

* y1 ,y2 are outputs of internal flip-flops

* Start , a1, a2 are external signals

are to be searchedfirst in fifth table

Fig. 7-27 : Example 1X3

A- = a2

7-14

A+

(Huffman Method Realization)

A+ A-

1

3

2

4

5

6

B+ B-

b2

a2

1

b1

0

a1a1

1 6

5 4 3

+-

180

+ - +-

166

2

166

b2

a2

1

b1

0

a1a1

b2

a2

1

b1

0

a1a1

b2

a2

1

b1

0

a1a1

b2

a2

1

b1

0

a1a1

b2

a2

1

b1

0

a1a1

b2

a2

1

b1

0

a1a1

1

1

1

1

0 0

00

0 0

00

---

-


1

4

6

5

a1b1 a2b1 a2b2 a1b2

3

-

2 --- -

-

- ---- -

0 01-0- 10

1

2

3

4

5

6

c. Merge Diagram

{1,2,6} {3,4,5}

d. Selected Option

3

6

e. Merged Flow Table &States Assignment

y

y

1 - 0 0

0 0 0-

A+ = Start.b1.y'

0 00

1

---

A- = b1.y

1 -0 0

-0 11

--

0 -

0

1

0

B+ = a2.y'+a1.y B- = b2

-

R = a1.b2S = a2.b2

0 0 1 0

- - - 0

- - -0

0 0 0 1

f. Exitation Functions

g. Output Functions

h. System Valve Circuit

a1

b1.y'

(a1.b2)

a2

Fig. 7-29 : Solution for Sequence START,A+,B+,B-,A-,B+,B-

(a2.b2)

b2

a2 c1

R S

b1

b1.y

A+A-B+

a2.y'+a1.y

B-

a. Process Sequence

START,A+,B+,B-,A-,B+,B-

R S

7-15

0

+-

RESTART

STOP

STOP

STOP

CR1

++

STOP STOP STOP RESTART

CONTINUE

Fig. 7-31 : STOP-RESTART With MultipleRemote-Control STOP Buttons

CONTINUE

cr1

cr1

Fig. 7-32 : Electric STOP-RESTARTSystem With Multiple Remote-ControlSTOP Buttons

No Change

Cylinder at rest must remain at rest.Cylinder in motion must complete its stroke, andremain at rest.

No Motion

Cylinder at rest must remain at rest.Cylinder in motion must be disconnected from pressureand move until stopped by friction (or end stroke).

Lock Piston

Cylinder in motion must be locked at its current position.Cylinder at rest must remain at rest.

Cylinder must be moved to its either (+) or (-) position,which been pre-definrd as "Safety Position".

Safety Position

Fig. 7-33 : Emergency Stop Modes Definition

Combination of No-Change and No-Motion modes.

No-Change/No-Motion

No-Change/Lock-Piston

Combination of No-Change and Lock-Piston modes.

No-Change/Safety-Posit ion

Combination of No-Change and Safety-Position modes.

To limitvalves

a. No-Change ModePneumatic Actuation

b. No-Change ModeElectric Actuation

C

To cylinder valves

c. No-Motion ModePneumatic Actuation

d. No-Motion ModeElectric Actuation

To limitvalves

To cylinder valves

Fig. 7-34 : No-Change & No-MotionCircuits

C

CC

a. Target & Definition

STOP

RESTART

CONTINUE

STOP

b. Single STOP-RESTARTbutton

RESTART

EMERGENCY STOP

c. Separate STOP/RESTART buttons

Stop process due to emergency condition

Fig. 7-30 : STOP-RESTART Single/Separate Buttons

Easy accessible buttonsSafety continuation Restart (Continue)

CONTINUEDifferent modesAdd-on

7-16

+ -

+-

+-

+

+-

a1

a2

A-

C

+-

+-

a1

a2

A+

C

+ -+ -

+ -

+ -

+ +

++

++

A- A+

Fig. 7-35 : "Lock-Piston" Mode Circuit

VA- VA+=A+

A-

C

C'C

from controlcircuit

To all shuttle valves

from controlcircuit

air supply tocontrolcircuit

continuecycle

A+

one valve for thewhole system

one valvepercylinder

Fig. 7-37 : "Safety-Position" Mode Circuit(Applied to Entire System)

A- A+

C

a1 a2

a1+a2

Fig. 7-38 : "No-Change/No-Motion" ModeCircuit

- - - ---

- - - ---

0 0 0

0

0 0 01

1

1

1 1 1

1

1

0

00 0

0

VA+ = C(A+) VA- = C(A-)+C'.a2'

Fig. 7-39 : Karnaugh Maps for"No-Change/Safety-Posit ion"Circuit

VA- VA+A- A+

Fig. 7-36 : "Safety-Position" Mode Circuit

(Applied to an Individual Cylinder)

VA- VA+

C

A- A+

Fig. 7-40 : "No-Change/Safety-Position" Mode Circuit

C

C

C C

a2'

Cylinder "A"

Cylinder "A"

Cylinder "A"

Cylinder "A" Cylinder "A"

7-17

CHAPTER 8

SWITCHING ELEMENTS AND

SYSTEMS

Timers Flip-Flops (FF) FF Implemntation for Binary Counters FF Implemntation for Shift Registers Endocers Iterative Circuits Binary Codes

+

+

+ -

+ -

+ -

START

+

+

+

Control

OutputDelay

a. On-Delay

Control

OutputDelay

b. Off-Delay

Delay

c. Interval

Control

Output

d. Monitored Interval

Control

DelayOutput

irrelevant

Control

Output

Delay A

e. On-Delat Off-Delay

Delay B

f. Delayed Interval

Control

Delay AOutput

irrelevant

Delay B

Control

OutputDelay A Delay B

g. Monitored Delayed Interval

Output

Control

Fig. 8-1 : Sequence Chart of Common Timer Modes

h. Repeat Cycle

Volume

Output

ControlSignal

Fig. 8-9 : Pneumatic Pulse Shaper

Volume

Output(Output)'

ControlSignal

Fig. 8-3 : Pneumatic "Off-Delay" Timer

Volume

Output(Output)'

ControlSignal

Fig. 8-4 : Pneumatic "On-Delay Off-Delay" Timer

Volume

Output

ControlSignal

Fig. 8-5 : Pneumatic "On-Delay" Timer Using Bias Pressure

Bias Pressure (frompressure regulator)

Fig. 8-6 : "On-Delay" Timer forAutomatic Cylinder Retraction

A+

Volume

A-

ASTART

Y1

Y2y1

y1 y2Output

Fig. 8-8 : Relay Pulse Shaper

Output

Input

1

0

1

0

Fig. 8-7 : Sequence Chart for a Pulse Shaper (Monostable, One-Shot)

Output

Input

1

0

0

1

a. Pulse Shorening b. Pulse Stretching

Fig. 8-2 : Pneumatic "On-Delay" Timer

Output

ControlSignal

(Output)'

Volume

8-1

NeedleValve

Check Valve

1

23

1

23

1

23

1

23

1

23

1

23

2

31

2

31

1

23

1

23

2

31

2

31

1

23

1

23

1

23

1

23

1

23

1

23

1

23

1

23

1

23

a. Basic Logic Circuit

Q

Q'

b. Master-Slave Type

Q0Q1Q2Q3

CLOCK

Q3

Q2

Q1

Q0

S (Set)

R (Reset)

Q

Q'

b. Short Symbol

a. Delay Flip-Flop (D)

IN

CP

OUT

Fig. 8-10 : Basic Set-Reset Flip-Flop (SR)

b. "UP" Counter Timing Waveforms

S

R

Q

Q'

c. Clocked SR Flip-Flop

S (SET)

R (RESET)

Q

Q'

a. Logic Circuit

Clock

Fig. 8-11 : Toggle Flip-Flop (T)

Fig. 8-12 : T Flip-Flop Implementation - Counters

b. Master-Slave Type

Q

Q'T

T

Q

Q'

Q

Q'

DD

CP

CP

Fig. 8-13 : D Flip-Flop Implementation - Shift Register

c. Shift Registerr Based on D Flip-Flops

Q0Q1Q2Q3

CLOCK

a. "UP" Counter c. "DOWN" Counter

T

UP

DOWN

RESET

d. "UP/DOWN" Selector

T

Q

Q'

FF0

Q

Q'T

FF1

Q

Q'T

Q

Q'T

FF2FF3

Q

Q'T

FF0

Q

Q'T

FF1

Q

Q'T

FF2

Q

Q'T

FF3

Q

Q'T

Q'R

S Q

Q'R

S Q

Q'R

S Q

Q'R

S Q QS

Q'R

Q'R

S Q

Q

Q'

D

CP

Q

Q'

D

CP

Q

Q'

D

CP

Q

Q'

D

CP

Q

Q'

D

CP

Q

Q'

D

CP

Q

Q'

D

CP

8-2

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

0 1 1 1

1 1 1 1

0 0 0 0

0 0 0 1

.

.

.

.

Q3 :Q2 :Q1 :Q0 :

.

.

.

.

.

.

.

.

1 0 0 1 1 0 1 1 0 1Input x

Shift

Fig. 8-14 : 10 Stages Shift Register

Fig. 8-16 : Schmitt-Trigger Response

Fig. 8-17 : Schmitt-Trigger Responseto Fuzzy Waveform

X1

Fig. 8-15 : Shift Register With Four Parallel Tracks

Shift

InputsX2

X3

X4 0

0

1

100

1

1

01

0

1

1

11 0

01 10

0

00

0

1

10

0

1

0

0

0 1

0

00

1

1

1

1

Weight

Number

00

1

2

3

4

5

6

7

8

9

8

0

4 2

0 0

1

0

P

0 0 0 1 1

1 10 0 0

01 100

10 01 0

1 0 10 0

01 00 1

1 10 1 1

0 101 0

1 0 1 00

Fig. 8-18 : Truth Table for an Error Checking BCD Code

8-3

LO (0.3V)

HI (3.4V)

OutputVoltage

InputVoltage

0.95V 1.8V

P = Parity Bit

(Even Parity Check)

A

B

C

DC

A

B

C

A

B

C

A

B

Weight

Number

10

1

2

3

4

5

6

7

8

9

7

1

4 2

0 0

1

0

P

0 0 0 1 1

1 10 0 0

01 100

10 01 0

1 0 10 0

01 00 1

0

1

0

1

0

1 0 1 00

Fig. 8-19 : Truth Table for 2-out-of-5 Code

P = Parity Bit

(Even Parity Check)

1 1

0 00

Fig. 8-20 : Use of Karnaugh Map to Obtain Cyclic Codes

(a) (b) (c) (d)

1 1 1 1

1 1 0 01 1 1 0

1 1 0 11 0 0 11 0 0 01 0 1 0

0 0 1 1

0 0 0 00 0 0 10 1 0 10 1 0 00 1 1 00 1 1 10 1 1 10 1 1 0

1 0 1 1

0 0 1 0

1100

Fig. 8-22 : Construction of "Reflected" Cyckic Code

1 1 01 0 01 0 10 0 10 0 00 1 0

Fig. 8-21 : Reflected Cyclic Code for 6 Numbers

8-4

101

000

001

010

011 100

110

111

A

B

C

D E

F

G

H

100

101110

111FGE

H

OKOKWRONG

WRONG

Fig. 8-23 : Binary 8-Sections Encoder

a. Encoder Plate

c. Sections Border Problem

b. Encoder Photo-Cells

Absolute Coordinates

101

000

001

010

011

100

110

111

A

B

C

D E

F

G

H

100110

FG OK

OK

a. Encoder Plate

c. Border Problem Solved

b. Encoder Photo-Cells

Fig. 8-24 : Typical 8-Sections Encoder

Absolute Coordinates

No Sense for Direction

c. Incremental Encoder Output

Fig. 8-25 :Single Output Incremental Encoder

8-5

a. Encoder Plateb. Encoder Photo-Cells

1

5

37

2

46

8

6

73

4

1

8

2

5

00 01 11 10

AB

00 01 11 10

AB

600/1

2

D

6

311/0

501/1

100/0

811/1

4

710/1

7

3

00 01 11 10

AB

210/0

5

8

401/0

1

d. Merge Diagram

e. Merged Flow-table & State Assignment

6

7

2

3

1

5

4

8CR1

CR2

CR3

CR4

CR1

CR2

CR3

CR4

f. Output Table

D

S1 = CR4.A.B' + CR2.A'B'

S2 = CR1.AB' + CR3.A.'B'

S3 = CR2.A.B + CR4.A.B'


O

O

O

O

1

1

1

1

D = CR1.B + CR2.A' + CR3.B' + CR4.A

R1 = CR2.A.B' + CR4.A.B

R2 = CR1.A'B + CR3.AB

R3 = CR2.A'.B' + CR4.A'B

R4 = CR1.A'.B' + CR3.AB'

h. Corrected System Initialization

S1 = A'B'.CR2'.CR3'

At that state, Flip-flop 1 must be set, with no confilict later,

Initially, A=B=0 and all Flip-flops are in reset state (CRi=0).

that is to say, while CR1 and CR2 are not set.

Fig. 8-27 : Motor Direction Detection System Design (Copy of 6-4)

g. Exitation and Output Functions

a. Control System Block Diagram

b. Primitive Flow-diagram

-

a. Disk Sensors Arrangement

O

1

2

7-

8

O5

2

B

1

-

O

-5

A

7

O

-

6

1

-

3

B

18

D

-

4

CONTROL

SYSTEM

1

-

1

Program DigitalComparator

D/AConverter

AmplifierServo Motor

Load

Tachometer

Encoder

orServo Valve

PositionBinary Signal

Error

Fig. 8-28 : Simplif ied Block Diagram of a Closed Loop NC System (One Control Axis)

Program ControlLogic Direction

PulsesStepMotor

Load

Fig. 8-29 : Block Diagram of an Open-Loop NC System (One Control Axis)

36

4

8-6

c. Primitive Flow-table

A

Fig. 8-26 : Two Output Incremental Encoder

(1)

(1)

(1)

(1)

(0)

(0)

(0)

(0)

B

A

ChangeDirection 360

0

900

b. Encoder Code Waveforms for Both Directions

"UP" direction "DOWN" direction

(A leads B) (B leads A)

4

56

4

56

FA

1

23

1

23

1

23

4

56

FA FA FAFA

C=0 C=1 Si

Ci+1

b. FA Truth Table

Xi

0 0 0 0 0Xi

Xn-1

0 1 0 0 1

Ci+1 = Xi.Yi+ Ci (Xi + Yi)

Y1

C0=0

Ci+1

Si

Cn-1

Y0

C2

Ci

Yi

1 1 1 1 1

Yi

Yn

1 0 0 0 1

Ci

0 0 1 0 1

Si = (XI) xor (Yi) xor (Ci)

Sn-1

Cn+1

S1

Ci+1

X1 X0

Yi

Yn-1

Xi

Xn

0 1 1 1 0

Si

Sn

Cn

S0

Ci

c. FA Logic Circuit

Fig. 8-32 : Iterative Binary Adder Design

0000000011111111

111

0

1

000

1

0

0

0

0

1

1

1

0

0

0

1

1

0

1

1

0

1

0

0

00

1

0

00

0

1

1

1

0

1

0

11

0

1

1

0

10

1

0

0

0

0

1

110

1

0

0

10

0

0

1

1

1

0

1

1

0

X1 X0 Y1 Y0 Z2 Z1 Z0

1111

0000

11

11

00

00

1

1

1

10

0

0

0

Z2 = X1.Y1 + X1.X0.Y0 + X0.Y1.Y0

Z1 = X1'X0.Y1'Y0 + X1.X0.Y1.Y0 + X1.Y1'Y0' +

+ X1.X0'Y1' + X1'Y1.Y0' + X1'X0'Y1

Z0 = X0.Y0' + X0'Y0

a. Truth Table

b. Sum Output Minimized Functions

Fig. 8-30 : Adder for 2-Bit Numbers

* 3-Bit Numbers Adder requires 6-Variable Map* 4-Bit Numbers Adder requires 8-Variable Map* 32-Bit Numbers Adder requires 64-Variable Map* Karnaugh Map Metode Is Limited to 4-Bit Numbers

c. Karnaugh Map Methose Limitation

01/0

00/1

11/0

a. General Cell (FA) Flow Chart

Fig. 8-31 : Iterative Adder Block Diagram

10/011/1

01/110/1

00/0 Xi,Yi/Si

8-7

1 0 1 1 01 1 0 1 0

C1

P=1P=0

Pi-1 PiXi

4

56

N=0 N=1 N>2N=2

Bi-1Ai-1 BiXi Ci DiDi-1 AiCi-1

Pi = Pi-1.Xi' + Pi-1'.Xi = Pi-1 xor X

g. General Cell Logic Circuit

Fig. 8-33: Iterative Parity Checker

0

1

d. General Cell Flow Chart

X (Vector) P

DESIGN OF A PARITY CHECKER

vector, is odd or even.

a. Requirements Definit ion

b. Simplif ied Block Diagram

c. Iterative Block Diagram

f. General Cell Function

Checker detects if number of "1" in a binary

It produces a single output line P, where :

P=1 denotes odd parityP=0 denotes even parity

Xn

Pn+1 Pn

Xi

Pi

0

P0Pi-1 P1

0

1

0 0

0

0

1

1

1 1

1

1

0

0

e. General Cell Truth Table

Pi-1 Pi

Xi

X (Vector) Z

A specific code consists of vectors that contain

a. Requirements Definit ion

b. Simplif ied Block Diagram

exactly two "1"'s, and all other bits are "0".

(11000000, 00101000, 010000001 etc).

Design a circuit that checks vectors and announces

Z=1 when detected vector been found valid.

Fig. 8-34 : Iterative 2-Out-of-n Checker

CB

0

1 1

c. General Cell Flow Chart

D

1

A

0 0

C1

A0

Bn

Di

Ci

Bi

Ai-1

*

"1"

D1

C0

Ai

Cn+1

Dn+1

A1

Xn

Bn+1

d. Iteratice Block Diagram

X0

An

Dn

"0"

Xi

"0"

"0"

B0Bi-1 B1

Ci-1

D0

Cn

An+1

Di-1

1

0

1 0

1

11

-

0

00

0

-0

00

1-1-

0

0

1

0

--

-

0

-1- 0

--

1

0

1

-

0

-

-

-

0

1

11


1

-1

0

01

0--

1

-

-

-

1

0

00-

0

0

-

-

Di =Ci-1.Xi +Di-1

f. General Cell Function

Ci =Bi-1.Xi + Ci-1.Xi'

Ai = Ai-1.Xi'Bi = Ai-1.Xi + Bi-1.Xi'

0

10 0

8-8DESIGN OF 2-OUT-OF-5 CHECKER

0 1

A<B

A=B

4

56

A>B

CiBiAiYiXiCi-1Ai-1 Bi-1

Yi

Ai-1

Ai = Ai-1 + Bi-1.Xi.Yi'

Xi

g. General Cell Logic Circuit

Fig. 8-35 : Iterative Binary Numbers Comparator

01

d. General Cell Flow Chart

X (Vector)

Y (Vector)

(X>Y)(X=Y)(X<Y)

ABC

Xn Yn Yn-1Xn-1

An+1

Bn+1

Cn+1

An

Bn

Cn

Bn-2

Cn-2

An-2

YiXi

Ai-1

Bi-1

Ci-1

Bi

Ci

Ai A1

Y0

B1

X0

C0

A0

C1

B0

DESIGN OF A BINARY COMPARATOR

Comparator compares 2 binary numbers X,Y (of equal length), and produces 3 output signals:

Line A : A=1 if X>YLine B : B=1 if X=YLine C : C=1 if X<Y

Design refers to positive numbers of n+1 bits, where n may vary according to case.

a. Requirements Definition

b. Simplified Block Diagram

c. Iterative Block Diagram

Bi-1

Ci-1

Ai

Bi

Ci

-10

1

1

1

1

1

1

0 0

0 0

0

0

0

0

0

0

0

0

0 0

0

0

1

1

1 1

- -

--

1 0 0

10 0

10 0

10 0

1 0 0

10 0


Ci = Ci-1 + Bi-1.Xi.'Yi

Bi = Bi-1(Xi.Yi+Xi'.Yi') = Bi-1(Xi xor Yi)'

f. General Cell Functions

-

00 11AB

8-9

0

1

0

0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 0

1 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

0 0 0 00 0 0 10 0 1 10 0 1 0

0 1 0 00 1 0 1

0 1 1 00 1 1 1

1 0 0 0

1 0 1 01 0 1 1

1 1 1 0

1 1 0 11 1 0 0

1 0 0 1

1 1 1 11 0 0 1

0123456789

101112131415

DecimalValue

NaturalBinaryCode

ReflectedCyclicCode

Fig. 8-36 : Comparison BetweenNatural-Binary and Reflected-Cyclic Code

Fig. 8-37 : Iterative Circuit for Translating Natural-Binary into Reflected-Cyclic Code

N(m)

N(m-1)

N(m-2)

N(m-3)C(m-3)

C(m-2)

C(m)

C(m-1)

Fig. 8-38 : Iterative Circuit for TranslatingReflected-Cyclic into Natural-Binary Code

N(i)

0 0 0

0

0

0

1 1

11

1 1

N(i-1) C(i-1)

N(i-1)C(i-1)= N(i)N(i-1)= N(i) C(i-1)

Fig. 8-39 : Truth Table for Translating Natural-Binary into Reflected-Cyclic Code

8-10

N(m)

N(m-1)

N(m-2)

N(m-3)

C(m)

C(m-1)

C(m-2)

C(m-3)

CHAPTER 9

SEMI-FLEXIBLE AUTOMATION HARDWARE PROGRAMMERS

Drum Programmers Programmable-Counter 1/n Programmable-Counter 2/n

&

&

>1 >1

&

>1>1 >1

+ -

x1y2+ -

y1 x2

X2X1

21 3

X3

Z1 Z2 Z3

4

X4

Z4 Z5

5

X5 X6

6

Z6 Zn

n

Xn

---Connectedto Module 1

31 2

X1 X2 X3

Z1 Z2 Z3 Z4

4

X4

5

Z5

Xn

n+1

NotUsed

---

START

n

Xn-1

Zn

Connectedto Module1

Fig. 9-5 : Schematic Representation ofProgrammable Counter

Fig. 9-6 : Programmable Counter WithSingle-Cycle START mode

3

Start

1 2

a2 b2

B+

4

c2 a1

5 6

a2

Fig. 9-7 : Programmable Counter Circuit forSequence With Parallel and Repeated Events(Actuating Valves Without Return Springs)

7

a1

8

c1b1

NotUsed

C+A+ A-B- C-

START , A-, A- ,B+, C+C-

B-, A+, , A+

5

Start

6

c2 a2b2

1

Fig. 9-8 : Programmable Counter Circuit forSequence of Fig 9-7, While Actuating ValvesHave Return Springs

3

a2 a1

42 7 8

a1

c1b1

NotUsed

NotUsed

A+ B+C+

1 / Start

X2 A+ a2 X

X3 b2B+XB- b14

XXC+5 c26 C- c1 X

XD+ d2 X7a1A-8

9 E+ e2 f2 X X

Xf110 F-f2 X11 F+

XF- f112XF+13 f2

14D-

X Xd1 e1 f1 X

GoHome

/15-24 X

A+ B+ C+ D+ D- E+ E- F+ F- Motor

F+

E-F-

StepDesiredEvent

SignaltoAdvance

Connected toI II III IV V VI VII VIII IX X

Switches

PROGRAMMABLE COUNTERS (SEQUENCERS)

Fig. 9-2 : Drum Programmer Solution

, A+, B+,STARTE+

F+B-, C+, C-, D+, A-, F+, F-,, F-, F+,

F-E-D-

X+Y+ Y-

XY

Cylinders A,B,C TypesCylinders D,E,F Types

DRUM PROGRAMMER (STEPPING SWITCHED)

A

B

C

D

1 2 3 4A

B

C

D

1 2 3 4

Fig. 9-4 : Matrix Board

a. With Sneak Path b. Without Sneak Path

1

2

3

4

5

6

7

8

9

10

431

C

2

D

B

A

E

MATRIX BOARDS

Fig. 9-3 : Boards

a. Patch Board b. Matrix Board

9-2In Out

+-

+-

+-

+-

+-

+-

+-

+-

+-

+-

RESETSET

y y'

RESETSET

y y'

RESETSET

y y'

RESETSET

y y'

& & & &

RESETSET

y y'

&

+-

RESETSET

y y'

+-

+-

RESETSET

y y'

& &

+-

RESETSET

y y'

&

+-

&

RESETSET

y y'

RESETSET

y y'

&

X1 X2 X3 X4

Z1 Z2 Z3 Z4

Xi

Zi

Si+1

Si

Si

Ri

Z1

X1X2

Z2 Z3 Z4

X3 X4

Zi

Xi

From Zi-1

To Zi-1 RESET

From Zi+1

Z2 Z3 Z4Z1

X2

Xi

To Zi-1 RESET

X1

X4

From Zi-1

Z3

X3X1

Zi Z1

Si+1

X4

Z4

X2

From Zi+1

Z2

X3

Ri

Si

Zi

Xi

To Zi+1 SET

a. Actual General Cell b. Actual Counter Configuration

c. Equivalent General Cell d. Equivalent Counter Configuration

Fig. 9-9 : Programmer Based on 1/n Code

a. actual General Cell b. Actual Counter Configuration

d. Equivalent Counter Configurationc. Equivalent General Cell

Fig. 9-10 : Programmer Based on 2/n Code

To Zi+1 SET

9-3

y1 y2 y3 y4

y1 y2 y3 y4

1 1 0 0 00 1 1 0 00 0 1 1 00 0 0 1 11 0 0 0 1

y1 y2 y3 y4 y5

12345

step

1 0 0 0 00 1 0 0 00 0 1 0 00 0 0 1 00 0 0 0 1

y1 y2 y3 y4 y5

12345

step

e. Counter cycle states

e. Counter cycle states

>1

>1

&

S RQ

FLIP-FLOP

>1

&

>1

>1

&

B-

(B+)

(B+)

(C-)

D+

2 7

Fig. 9-11 : Programmable Counter Example 1

b1

FLIP-FLOP

(Both B and C require f l ip-f lops)

(With ReturnSprings)

4

7

c1

B+

c1

(B+)

(b)

c2

FLIP-FLOP

b2

RESET

B+ ,

FLIP-FLOP

start

d1

a1

Fig. 9-12 : Programmable Counter Example 2

B+

c. 2/n Programmable Counter Circuit

Fig. 9-13 : 2/n - Different Stability Cases

c2

(A-)(C+)

start

A- ,

6

4

Start

B+

A+

(B-)

31

8

a2 b1

B+

c1

A+ , D+ ,START ,

(d)

(B+)

C- ,

B+

a1

b1

4

b1

C+

A+

b. 1/n Prog.rammable Counter Circuit

A+

a1

a1

SET

D- ,

31

(B+)

(D-)D+7

5

c2

START , A+ , A- , B+ , C+ , B- . C- , C+ ,

B-

(B-)

b2

OR

2

2 3

a2 c2

Start

B+

c. 2/n Programmable Counter Circuit

C+

c2

C+b2

a. Sequence

a1

b2

C+

B+

(B+)

7

b. 1/n Prog.Counter Circuit

(B+)

c2

b2

a1

4

2

B+

(B+)

d1

9-4

6

5

A+

b2

A+

a. Sequence

d2

SET

OR

(a)

d2

(e)

a2B+

C+Start

c1

RESET

D+

6

b2

c1b2

(B-)

1

6

(B+)

A+

RESET

5

3

a1

C+

C+ ,

D+ B+

(C+)

C- ,

(A-)

SET

8

1

a1

C+

A+

(D-)

- - - -

a2

- - - -

C+

B+

a2

A-

(c)

5



B+

A-, ,B-C+

A2A1

21 3

An

ZA1 ZA2 ZAn

---

1

ZB1

2

B1

ZB2

B2

1

ZC1

2

ZC2

CkC2

ZCk

k---

---

B m

m

ZBm

B3

ZB2

2

1

ZD1

2

D1

ZD2

DpD2

ZDp

p---&

Fig. 9-14 : 1/n Programmer fot Two Simultaneous Parallel Paths

1

ZA1

2

A1

ZA2

AnA2

ZAn

3---

1

ZB1 ZB2

2

1

ZCk

C2 Ck

ZC1

--- k

ZC2

2

m

ZBm

---2

ZB2

ZD1

D2D1

21

ZDpZD2

p

Dp

--->1

Fig. 9-15 : 1/n Programmer for Two Alternative Parallel Paths (Parallel)

&

P

&

P'

An

21

A2

ZA2 ZAn

3---

ZA1

A1

ZB2

2

B1 B2

ABm

1

ZB1

B m

--- m

ZC1P

P'

&

&

>1

ZC2

C2C1

1 ---2

ACk

Ck

k

ZA2

2

A1 A2

ZAn

1

ZA1

An

--- 3

ZB2

---1

ABm

B mB1

ZB1

m

B2

2

C1 C2

ACkZC2

--- k1

ZC1

P'

2

Ck

&>1

&

Fig. 9-17 : 1/n Programmer for Program With Repeated Steps Option

Fig. 9-16 : 1/n Programmer for Program With Skip Steps Option

P

9-5

B1 B2 B mB3

Path B for P=1Path C for P=0

Skip for P=0

Repeat for P=0

tablemethod

Operation-

counterProgrammable

counterProgrammable

counterProgrammableFlow-Table

method

Flow-Tableor Huffmancascade

method

Pneumaticcascademethod

Pneumatic

Relay

methodcascade

methodHuffman

Is design

requested?

used?relaysAre

simplicity moreIs design

used?valves

Are

used?valves

Are

element econpmy?

More than

cylinders?

repeatedAre there

events?

events?repeatedAre there

4 or 5More than

cylinders?

YES

YES

YES

YES

YES

YES YES

YES

YES

NO

NO

NO

NO

NO

NO NO

NO

NO

Fig. 9-18 : Flow Chart for Selecting Sequence-Control System Design Method 9-6

important than

flexibility

4 or 5

method

CHAPTER 10

PROGRAMMABLE LOGIC CONTROLLER

Introduction PLC Configuration PLC Programming Implementation in Ladder Diagram Implementation in Huffman Metode

Memory Size (Words) I/O Capacity (Modules)

Micro PLCSmall PLCMedium PLCLarge PLC

Up to 64Up to 128Up to 512> 512

Fig. 10-2 : PLC Classification According to Size

Fig. 10-3 : Discrete Input Devices to PLC

Limit SwitchesProximity SwitchesPhotoelectric SwitchesSensor Switches (Level, Pressure, Temperature etc)Push-Button SwitchesSelector SwitchesRelay Contacts

Fig. 10-4 : Discrete Output Devices Actuated by PLC

Contact Relay CoilsValve SolenoidsPneumatic or Hydraulic Cylinders and MotorsLightsAudible Alarms (Bells,Buzzers,Sirens)Fans

Motor StartersHeaters

Fig. 10-1 : Block Diagram of Programmable Controller (PLC)

Central ProcessingUnit (CPU)

Memory

InputModules

OutputModules

Control ledSystem

ProgrammingUnit

PLC

PLC CONSTRUCTION

Fig. 10-5 : Standard Discrete I/O Interface Modules

12, 24, 48, 120, 230 Volt AC

5V DC (TTL Level)Conract Relay Output

12, 24, 48, 120, 230 Volt DC

Fig. 10-6 : Type of Electronic Memories

RAMROM

PROMEPROMEEPPOM

Random-Access MemoryRead-Only MemoryProgrammable Read-Only MemoryErasable Programmable Read-Only MemoryElectrically Erasable Programmable Read-Only Memory

000

001

002

003

004

Start PB1

Reset PB2

Temp TS3

Level FS4

Level FS5

PLCProgramCoding

n

000

001

002

003

004

m

InputModules

OutputModules

......

...

......

...

F ig. 10-7 : I/O Connection Diagram

Control led System Control led System

I/O Modules (PLC Mounted)

PLC PLC

I/O Modules (Field Mountedwith Multiplexer)..........

..........

..........

Fig. 10-8 : Different I/O Connection Location

a. PLC-Mounted I/O b. Remote-Mounted I/O 10-1

PL1 Rdy

Set 1 Open

PL2 #1

Set 2 Open

PL3 #2

10036 10047

10124 10107

04

10118

10054

10112

10113 08114

10113

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Word Adress (Octal)

0000

0007

(8 Words)

0010

00170020

0027

0427

0030

(8 Words)

(8 Words)

(256 Words)

0430

7777

(3816 Words)

Input Table - 128 Bits

Output Table - 128 Bits

Internals - 128 Bits

Registers

User Memory

Fig. 10-9 : Typical PLC Memory Map

1. Ladder Diagramms or Graphic Programing - entered either by drawing the Ladder diagram on screen, or by Boolean Mnemonics.2. Boolean Mnemonics or Logic Instruction Set.3. GRAFCET or Function Chart -

Used by : Telemechanique, France (GRAFCET)

5. Computer Language such as BASIC, with additional commands.4. Enhansed Ladder Diagrams (Ladder Diagrams with "Instruction Blocks").

Allen Bradley, USA (SFC = Sequential Function Chart)Siemens, Germany (Graph 5)

Programming the PLC

Fig. 10-10 : Programming Languages

TIMER ON

0.1 SECONDPR = 3200AC = 520

ADDR

T 0045TP0045TA0045

(EN)

(TC)

12 16

03 86 82

86 10

01

83

16

86

O0033

O0034

O0034

14

02

17

17

15

15

T0045

T0045

O0075

Fig. 10-11 : Ladder Diagram Section Appearing On Screen(Allen Bradley Co. PLC)

10-2

( )

( )

( )

( )

+ -

+ -

a2a1START

INPUTMODULE 1

PLC

LOGICLEVEL

HIGH/LOWVALUES LOAD 1

(LOGIC LEVEL)

Y1

Ym

X1

Xn

CR1

CRk

Fig. 10-12 : PLC Configuration

OUTPUTMODULES

INPUTMODULES

CPU OUTPUTDEVICES

INPUTDEVICES

INPUTMODULE 2

X2 Y2

INPUTMODULE 2

OUTPUTMODULE 1

PLC SYSTEM

CPU

CYLINDER SYSTEM

Fig. 10-13 : Typical PLC Control System

HOST

PLC 6

PROCESS 3

PROCESS 2

PROCESS 1

PROCESS 9

PROCESS 8

PROCESS 5

PROCESS 6

PROCESS 7PROCESS

4

PROCESSOR

Fig. 10-14: PLC Network (Macro)

LOAD 2

LOAD m

SENSOR 1

SENSOR 2

SENSOR n

LOGICLEVEL

Start

a2

a1

X0

X1

X2

Y1

Y2

A+

A-

PLC 6

PLC 4

PLC 7

PLC 8

PLC 1

PLC n

PLC 9

PLC 3

PLC 2

PROCESS n

HIGH/LOWVALUES

INPUTMODULE N

LOGICLEVEL

LOGICLEVEL

HIGH/LOWVALUES

HIGH/LOWVALUES

LOGICLEVEL

LOGICLEVEL

HIGH/LOWVALUES

HIGH/LOWVALUES

OUTPUTMODULE 1

OUTPUTMODULE M

OUTPUTMODULE 2

10-3

INPUTMODULE 3

INPUTMODULE 1

OUTPUTMODULE 2

CR1

D-

Y13

Y8

Stop AND NOT X18

b2

MOTOR

A+

X8

PLC

A- ,

A-

B-

Y5

Start

c. I /O Assignment Table

OUT Y13

c1

(NO RETURN SPRING)

Y1

B+ ,

C-

D+

g. PLC Program

Y6

T.S.AND NOT X19

c2

A+ ,

C+

CR1

Y7

(WITH RETURN SPRING)

OUTPUTMODULE

Y4

d1

X18

C+ ,

D-

B+

a. Process sequence

b. Block Diagram

T.S.

X0

Y7

d2

Y13

M O T O R

InputModule

CR1

B- ,

B-

Y3

InputModule

X1

Y3INPUT TABLE

X18

e. PLC "Internal" Ladder Diagram

X19

D- ,

D+

Y2

InputModule

X2

Fig. 10-16 PLC Motor Control System

Y2

A-

Start

b. Input Table

X17

X5

B+

Stop

A+

START

X3

Start

Y1

X18

X6

A+

10-4

C+

X0

X4

a1

T.S.

Y8

c. Output Table

MOTOR

X19

X7

(Motor current must be isolated from sensors)

OUTPUT TABLE

X1

START ,

a2

X17

Y5

OutputModule

(no return springs)

CR1

e. PLC and I/O System

X18

X8

D+

X2

D+

b1

Y13

OUTPUT TABLE

MOTOR

PLC

f . Simpli f ied Ladder Diagram

START

B+

X3

X17

C+

d. Output Table

b2

CR1

INPUTMODULE

Y6

(Temperature Switch)

(no return springs)

X19

Y3

X4

Y13

Start

A+ ,

(with return springs)

c1

T.S.

C-

a1

d. PLC Ladder Diagram

a. Relay Ladder Diagram for Motor Control

STOP

Y2

X5

C-

Fig. 10-15 PLC I-O Variables Assignment

c2

C+

Motor

a2

(No isolation problem since allI/O are isolated by modules)

Stop

Y4

X6

A-

d1Y4

X17

Y1

System

CR1

OR Y13

b1

X19

STORE X17

Y1

X7

Motor

, C- ,

d2

000

001

003

Stop

Reverse

030

cr1

cr2

a2 cr3CR2

cr6

b2

d2 B+

C+

X3X4X5

Input Module Output Module Connected to

Y12Y13

a2b2d2B+C+

Fig. 10-19 : I/O Assignment Table for Fig. 10-18

cr1

cr2

cr3CR2

X5Y12

Fig. 10-20 : Ladder Diagram of Fig. 10-18 in PLC Format

Y13

x3

cr6

cr2 x4

STORE NOT

CR2

X1

ORCR1

CR2X4

AND

STOREOUT Y12AND

123456789

10

AND NOT CR3OUT

X5CR2

0

ANDOR CR6

Y13OUT

Fig. 10-21 : Program for Fig. 10-20

X4

cr10X2

cr11

Y5

Fig. 10-22 : Use of LIFO Memory Stack

STORE NOT1

Y5

CR10

4 OR

AND

3

X2

2

OUT

0

X4STORE NOTAND CR11

STORE5

Fig. 10-23 : Program for Fig. 10-22

...

002Forward

...cr1

004cr2

M1

f

032

M2

r

031

Forward PL1

033

Reverse PL2

000 001 002 032 003 030

000 001 002 031

000 001002 032

000 001002 033

004

034034

OL1 Fault PL2

035OL2 Fault PL2

003

035

030 004

030

030

032

032

Fig. 10-18 : Ladder Diagram Segment Il lustratingRepeated Actuation of Solenoid C+

Fig. 10-17 : Forward/Reverse Circuit(Using Two Motors M1 na M2, and Overload Switches OL1 and OL)

10-5

CR1

A+

B+C+

B-

C-A- C-START

I II III IV

C+

START

a1

a2

b1

b2

c1

c2

x1

x2

x3

x4

x5

x6

x0

A+ Y1

A- Y2

B+ Y3

Y4B-

Y5C+

C- Y6

STOREAND NOTAND NOTORAND NOTOUT

AND NOTOUT

ANDORAND NOTOUT

X0CR3Y4Y1

Y2Y1X6Y2CR3Y2

CR3X5

Y4CR3

ORAND

ANDX5

X6

Y4

X3

AND

STORE NOTOR NOT

OUT

Y1Y3OUT

STORE

X2ANDX4ANDCR3ORY5OUT

Y2STOREAND X1

Y4ORY6OUT

Fig. 10-24 : PLC Cascade System Design

a. Process sequence Groups partitining

b. Relays Cascade Circuit e. PLC Cascade CircuitAssignment

f. PLC Programd. Optimize CRRelays

Y1 = CR1

Y2 = CR2

Y4 = CR4

Y4OR

10-6

cr3' cr4' cr2'

cr1

cr1

cr1

cr1

cr2

cr2

cr2

cr2

cr3

cr3

cr3

cr4

cr4

cr4

c. PLC Variables

cr1

cr3'

cr4'

c2

c2

c1

b1

c1

a2 b2

a1

A+

A-

B+

B-

C+

C-

CR2

CR3

CR4

START

X0 cr3' y4' y2'

y1

y1

y1

y1

y2

y2

y2

cr3'

y4'

X6

X6

X5

cr3

cr3

y4

y4

X1

X2 x4

cr3

X3'

X5'

Y2

Y1

CR3

Y4

Y3

Y5

Y6

STORE

X2=1 Counter Enabled X2=0 Counter is Reset

OUT

STORE NOT

CR6

OR

200

TIMERS AND COUNTERS

(n)

Y1

X2

X1

X2= O-->1 One count

X1

X1 determines UP or DOWN mode

120

X2

STORE NOT

X4

F1(Up/Down)

OUT

X1= O-->1 One count

X2

c. Programmable of (a)

X3

5

10-7

X3

X1

STORE

TMR

CTRi

(Reset)

STORE

TMR2

CR11

X2

TMR1

TMR2

(0.5 Sec)

LOAD NOT

F1

CTR3

STORE

X3

AND

X2=1 Timer Enabled X2=0 Timer is Reset F2=1 Timer Enabled F2=0 Timer is Reset

AND

F2=1 Counter Enabled F2=0 Counter is Reset

X2

CR1X2

OUT

CR10

X1

STORE

OUT

AND

AND NOT

X1=1 Timer Run X1=0 Timer Stops

X4

(200)

LOAD

OR

X3

CR1

CTR1

X4

CR1

STORE

empty

STORE

STORE

OUT

X1

CR5

CR6

F2

Y2

b. General Case

(Reset)

TMR1

LOAD NOT(Event)

Fig. 10-32 : UP/DOWN Counter (General Electric PLC)

Fig. 10-26 : Rearrangement of LadderDiagram for Simpler Programming

CR1OR

AND NOT

X3

OR

STORE

LOAD NOT

X3

F1 determines UP or DOWN mode

TMR

CR1

(n)

empty

OUT

TMR1

F1=1 Timer Run F1=0 Timer Stops

STORE

b. General Case

X2

TMR2

CTRi

TMR1

CR1

CR3

OUT

a. Specific Case

(120)

Y1

STORE NOT

X2

LOAD NOT

AND NOT

X1

LOAD

X1

X1

F2

AND

Fig. 10-30 : Program for Fig. 10-29 (a)

(Up/Down)

CR5

CTR

X1

F1

(Event)

CR2

a. Original Circuit

(n)

a. Ladder Diagram

X3

X2

LOAD

AND

CR1

Fig. 10-28 : Program for Fig. 10-27 (a)

X4

CR11

b. PLC Programming

X1

Fig. 10-25 : Multiple Use of LIFO Stack

CR1

X3=1 Counter Enabled X3=0 Counter is Reset

F3=1 Counter Enabled F3=0 Counter is Reset

TMR1

STORE25

TMR1

F3

F2= O-->1 One count

X2

CR1

AND

CR1

(25)

5

b. Programmable Simplified Circuit

Fig. 10-27 : Timer Set for 20 Seconds (Texas Instruments PLC)

a. Ladder Duagram

Y2

CR10

AND

STORE

(Light Valve)

X2

CR1

TMR2

STORE

Y1

Fig. 10-31 : Making Light Flash While X=1 (General Electric PLC)

X1

F2

X1

X2

F1= O-->1 One count

OUT

OUT

a. Specific Case

OUT

X1

b. Programmable of (a)

CR2

CTR3

CR1

b. General Case

CTRi

CR3

STORE

a. Specific Case

CTR3

STORE

CTR

X4 TMR1

(0.5 Sec)

Fig. 10-29 : Counter to Count 25 (Texas Instruments PLC)

X3

X5

X3

X5

CR1

X3 X3CR1

Y1y1

d2d1

+ -

Y1

Y0

X0 (d1)

X1 (d2)

CR7

X1 (d2) CR3

CR6

CR6

CR5

CR5

X12 (Start)

X0 (d1)

CR3

CR6

CR7

CR7

CR5 X1 (d2) Y0

TMR

(0.3 Sec)

(5)

Fig. 10-33 : Two-Hands Circuit Using PLC

Fig. 10-34 : Process Definition

START,(D+,D-) repeat 6 t imes,D+,10 Sec DELAY,D-

D- D+

D

X0X1X12

Input Modules Output Modules

Y0Y1

Connected tod1d2STARTD-D+

a. Assignment Table

(6)

COUNTER 1

(100)(10 Sec)

TIMER 1

STORE

AND NOT

OUT

OUT

AND

OUT

X0

CR5

Y1

CR7

Y0

X1

CR3

OR

CR5STORE NOT

X0STORE

STORE NOT X12

CTR1

6

(NOT USED)

X1AND

CR6OUT

CR6STORE

CR7OUT

TMR1

100

(NOT USED)

c. PLC Programm

b. Ladder Diagram

Fig. 10-35 : Design PLC Program for Sequenceof Fig.10-34

10-8

b. Cylinder Type

a. Required Cycle

CR2

TMR1

(100)O U T

C O U N T

R E S E T

CR1

Y1

CR0

Y0

MOTOR

1st

2nd

3rd

4th

5th

MOTOR

X1

TMR1

TMR1

(120)O U TC O U N T

CTR1

X3

CTR1

(120)O U T

U P / D O W N

R E S E T

E V E N TX2

X1

TMR1(120)

O U T

C O U N T

R E S E TX2

CR1

CR1

X1

CR1

X1

X2

CR1CTR1

(120)O U T

E V E N T

R E S E T

X1

X2

X3

X4

X5

CR2

X1

CR1

CR0

CR1

CR0

CR0

CR0

X5

CR2

CR2

Fig. 37 : "Saturday" Elevator

An elevator exists in a 5-floor building.Elevator runs automatically (without human control),from 1st floor to 5th floor, and vica versa, while stoppingfor 10 seconds in each floor.Each floor is equipped by a unique contact, that is closedwhen the elevator reaches that floor. These contacts areimplemented as input sensroes for PLC control system.

X1

PLCY1X2

INPUTM O D U L E

b. PLC System Configuration

X3

INPUTM O D U L E

INPUTM O D U L E

O U T P U TM O D U L E

INPUTM O D U L E

X5

INPUTM O D U L E

X4

UP

O U T P U TM O D U L E

Y2

DOWN

a. System Description

c. PLC Ladder Diagram

Notes : CR2 control elevator directionY1 - Up directionY2 - Down direction

120

OUT TMR1

a. General-Electric PLC Timer

LOAD X1

120

COUNTER (GE)

OUT CTR1

LOAD X3

LOAD X2

LOAD X1

b. General-Electric PLC Counter

TMR1

STORE X2

(empty)

STORE X1

OUT CR1

120

c. Texas-Instruments PLC Timer

120

CTR1

STORE X2

STORE X1

(empty)

OUT CR1

d. Texas-Instruments PLC Counter

Fig. 10-36 : PLC Timers and Counters

10-9

CR1

CR2

CR1

CR2

CR1 CR1

If X6=0, then the next (3) outputs are kept at logic "0" (shut off)

MCR(3) STORE X6MCR 3

X6

......

A. Ladder Diagram b. Programming Lines

c. Command Definition

Fig. 10-38 : Master Control Relay (MCR) Command

If X6=0, then the next (3) outputs are frozen, and the PLCcontinues its scan at the rung following the third output

JKP(3) STORE X63

X6

......

A. Ladder Diagram b. Programming Lines

c. Command Definition

Fig. 10-39 : Jump (JMP) Command

Fig. 10-40 :Differences Between Relay and PLC Ladder DiagramSneak Path

X1 X2

X3 X4

X5

a. Relay Ladder Diagram

X1 X2

X3 X4

X5

c. PLC Ladder Diagram

No Sneak Path

CR1 = X1.X2 + X3.X4.X2

CR2 = X3.X5 + X1.X4.X5

b. Boolean FunctionUn-expected Sneak Path - X1.X4.X5

CR1 = X1.X2 + X3.X4.X2

CR2 = X3.X5

d. Boolean Function

X3

X1

X2 X4

X1

X3

X2

X2

X3

X5

X1 X5 X4

X2 X5 X3

a. Relay Ladder Diagram b. PLC Ladder Diagram

c. Boolean Function

CR1 = X1.X3+X2.X4+X1.X5.X4+X2.X5.X3

Fig. 10-41 :Differences Between Relay and PLC Ladder DiagramMultiple Contacts

JMP

10-10

x4

Y1

Y1

1 - 5 volt DC

PLC Scan

CR2

CR5

Y1

X1

OUT +/- 5 volt DC

cr4

y7

Y7=0 , CR2=0

CR4=1 , CR6=1

X1

CR1

+/- 10 volt DC

CR6

cr6

I/O Update

Y1

AND NOT

STORE

cr1

x4

Y8

Y7=1 , CR5=1

CR6=1 , Y8=1

AND NOT

Rung 1 : CR1

Next Scan

X4=1 , CR4=1

VariablesStates

a. Proper Rung Order

X1

cr2

Fig. 10-48 : Analog-Output Devices Actuated by PLC

Rung 3 : CR2

CR4=0 , CR6=0

CR6=0 , Y8=0

Fig. 10-42 : Effect of Scanning Action onInternal States of Relay Coils

Y1

STORE

cr2

Analog Valves

at Beginning of Scan

X1

OUT

X1

y1

4 - 20 mA

Pneumatic or Hydraulic Cylinders or Motors

Electric Motors

X4=1 , Y7=1

Y1

OUT

Fig. 10-44 : Trigger (Toggle) Flip-Flop for PLC

Recorders

Rung 1

CR1

b. Improper Rung Order

STORE

CR1

0 - 1 volt DC

Rung 2

Fig. 10-45 : PLC Sequence Chart for Fig. 10-44

This Scan

Fig. 10-43 : Importance of Proper Rung Order

Humidity Transducers

Fig. 10-47 : Standard Analog-Input Interfaces Nodules

Rung 3

X1 cr1 STORE

X1

USE OF PLC WITH ANALOG I/O

0 - 5 volt DC

Y7=1 , CR2=1

Y1

cr1

X1

X1

Pressure TransducersTemperature Transducers

0 - 10 volt DC

1 2 3 4 5 6 7 8 9 10 11 12 13

X1

CR1

y1

Flow Transducers

Fig. 10-46 : Analog Input Devices to PLC

Rung2 : Y1

X1

CR1

CR1

OUT

X1

Load Cells

Y7

Scan Period

X1

CR1

Potentiometers

10-11

y7

CR4

CR1

X1 (Input)

(Output)

Fig. 10-49 : Standard Analog Output Interface Modules

4 - 20 mA

10 - 50 mA

0 - 5 volt DC

0 - 10 volt DC

+/- 5 volt DC

PID Controller

AnalogTransducer

Voltage Signal

Return Line A/D

12 bits Register holding analog value

Analoginstructionused

Analog input module

Word locationor

Register Storagelocation

0 0 0 0 0 01 1 1 1 1 1

0 0 0 0 0 01 1 1 1 1 1

Data Table

Since A/D converters are expensive, they are often shared by several4 to 8 channels. One channel is read and stored on every scan.

Fig. 10-50 : Storing an Analog Input

Rack oSlot 03Number of channels 8Destination register 200

(Rack with 8 slots)(Slots 0 to 7 per rack)

(Octal code 200 = 128)

Fig. 10-51 : Typical "Analog In" Instruction Block

8 8

12 bits Register holding analog value

0 0 0 0 0 01 1 1 1 1 1

10 0 1 1110 01 00

Data Table

Word locationor

location

Fig. 10-52 : Tranferring a Word to Analog Output Module

Rack 4Slot 05Number of channels 4Source register 300

(Rack with 4 slots)(Slots 0 to 7 per rack)

(Octal code 300 = 192)

Fig. 10-53 : Typical "Analog Out" Instruction Block

1. Controlled Variable

Fig. 10-54 : Typical "PID Controller" Instruction Block

2. Controller Output(Given by analog input module)

3. K (P-control)

4. R (I-control)

6. Set Point5. T (D-control)

Control(Enables Outputs)

Track(Tracks incomingvariables, even if"Control" is off)

(Sent to analog output module)(Active loop control)

(High alarm limit)

(Low alarm limit)

In some PLC's, the PID Controller is implementedby a special output module, i.e. by hardware. Inothers, it is programmed using a special InsrtuctionBlock, such as shown here.

Analoginstructionused

D/AVoltage Signal

Return Line

Analog Output module+/- 10 volt DC

ANALOG IN

ANALOG OUTPUT

PID CONTROLLER

10-12

0000

Not Used

Register Storage

AnalogTransducer

(Since there are 8 channels, the 8 slots would be assigned theDestination Register 200 to 207 )

Connected to Register

Fig. 10-55 : Typical "ADD" Instruction Block

(Enhanced ladder diagram instructions are handeled very differently in differentPLC models. Therfore, only a few typical examples are shown here.)

LATCH (UNLATCH)

GOTO

ADD

Register X+

Register Y=

Register Z

ADDControl(Enable)

OverflowOutput

ENHANCED LADDER DIAGRAM INSTRUCTIONS

Fig. 10-56 : Typical "COMPARE" Instruction Block

MULTIPLICATION

DIVISION

SQUARE ROOT

Control(Enable)

SUBTRACT

COMPARE

COMPARE

>=<

Register X

Register Y

(or correcponding bits of two specified registers)

AND

OR

XOR

NAND

NOR

NOT

Data Conversion

These change the contenta of a specified register.

BCD to Binary

Typical Conversions :

Binary to BCDAbsolute ValueComplement (multiplied by -1)

Invert (inverts all bits)

Logical Shifts : Moves all bits of a register to right or left

Data Transfer Instructions : There are many suchinstructions, used to move datawithin the PLC

Fig. 10-57 : Logic Operations

Macro-automation makes use of a LAN (Local-Area-Network), which linksthe various stations or automation islands with the central supervisingcomputer or PLC. The use of a LAN provides :

(This course deals with Micro-Automation).

The LAN can be organized according to any one of a several possible LANTopologies (arrangements), such as "Common Bus", "Star" or "Ring".

Macro-Automation : Automation of a large plant, consisting of manyindividual automation islands. Uses a largecomputer or a large PLC, that coordinates theoperation of the individual automation islands.Each automation island is uusually controlled by itsown control system, such as a small ormedium-sized PLC ("Distributed Control").

10-13

RING

Micro-Automation :

2. Centralized Data Aquisision

STAR

Automation of a single machine, or asmall group of machines, also calledan "Automation Island".

Fig. 10-60 : Several Possible LAN Topologies

MICRO-AUTOMATION versus MACRO-AUTOMATION

1. Distributed Control

BUS

Fig. 10-58 : Data Commands

Fig. 10-59 : PLC Micro/Macro Systems Definition

X2

00/01

CR1

10/02

11/03

01/04

X1

X2

01/15

Y1

CR1

X1

CR1

CR1

CR1

Y1

b. Primit ive Flow Diagram

1. Different size elements are transferred on a conveyor belt.2. All elements that are below specific thickness must be rejected.3. Reject is performed by opening a reject door - Z=1.4. Photocells X1 and X2 are placed in specific locations.5. X2 is covered by all sizes. X1 is covered by elements over

specific thickness.X2X1

S = X1.X2'R = X1'.X2'Z = X2.CR1'

c. System Functions (See Fig. 6-2)

(S = X1)

e. PLC Ladder Diagram

STORE X1OR CR1

CR1STORE NOT

123456789

STOREX2ORX1

CR1OUTSTOREAND

X2ANDOUT Y1

X1X2

Y1

X1X2

Z

PLC I/O

d. PLC Variables Assignment

f. PLC Program

A B

CR1

b. System Relay Ladder Diagram

CR1

B

A

L

B

a. System Configuration

See Fig. 6-3

Y1 L

BX2X1 A

I/OPLC

c. PLC Variables Assignment

CR1

X1

CR1

X2

d. PLC Relay Ladder Diagram

X1 X2

X2

Fig. 10-61 : Thickness Detector System

CR1

5

7

X1

6

9

STORE NOT

OUT CR1

X2AND

OUT Y1

e. PLC Program

Fig. 10-62 : Traffic-Light Control System

1 STOREAND X24

CR13 ORAND X24

OR X18

Railway

Roa

d

10-14


1

600/10

3

2

4

CR3

3

410/10

5

4

5

6

CR3

CR2

6

CR1 CR1

100/00

CR2 CR2

CR3

210/10

1

CR1

2

311/01

501/00

ALARMSYSTEM

Danger Signal

Confirmation

X1

X2

Z1

Z2

ALARM SIREN

ALARM FLASH

2

3

4

5

6

5

31

1 3

52

1

1

1

1

0 0

0

0

0

0 0

0

1

2

3

4

5

6

{3,4,5} {2.6} {1}

{1,5} {2.6} {3,4}

{1,5} {2.6} {3,4}

a. System Block Diagram (According to Fig.6-1)

c. Primit ive Flow Diagram

d. Primit ive Flow Table

e. Merge Diagram

f. Merge Options

g. Selected Options

2 3

5

1

3

h. Merged Flow Table &

5

00 10 11 01 z1 z2

States Assignment

00 10 11 01

00 10 11 01

0

00

0

1 1

-

-

00 10 11 01

0 0

0 0

1 1

-

-

- -

i . Output Table of Z1 j. Output Table of Z2

S1 = X1'.X2'.CR2' + X1'.X2 = X1'(X2' + CR2')

S2 = CR1.X1.X2'

S3 = X1.X2

R1 = CR2.X1.X2' + X1.X2 = X1(X2 + CR2)R2 = X1'.X2 + X1.X2 = X2

R3 = CR1.X1'.X2' + CR1.X1'.X2 = CR1.X1'

Z1 = CR2 Z2 = CR3

k. Exitation & Output Functions

Fig. 10-63: PLC Design of Alarm System

b. Different Considerations in Relay/PLC Systems

* Cannot ignore multiple input changes "simultaneously"* No race or hazards. Action depends on commands Order

2

3

1

5

3

5

-

- -

-

STORE NOT CR2 STOREOR NOT X2AND NOT X1OR CR1

X2STORE NOTCR2

OR NOT X1AND STOREOUT CR1

X1AND

X2AND NOT

OR X1CR1STORE NOT

OUT CR2

X1AND X2OR CR3

X2OR CR2

AND STOREOUT CR3

OUT Z2

CR2STOREZ1OUT

123456789

1011121314

15161718192021

22

2423

l . PLC Program

-

-

AND NOT

AND NOT

X1,X2

X1,X2/Z1,Z2

X1,X2 X1,X2

X1,X2

10-15

See Fig. 6-4

Fig. 10-64 : Motor Direction Detector

Y1 D

BX2X1 A

I/OPLC

c. PLC Variables Assignment

S3 = CR2.X1.X2 + CR4.X1.X2' = X1(CR2.X2 + CR4.X2')

S2 = CR1.X1.X2' + CR3.X1'X2' = X2'(CR1.X1 + CR3.X1')

S4 = CR1.X1.X2 + CR3.X1'X2 = X2(CR1.X1 + CR3.X1')

S1 = X1'X2'.CR2'.CR3'

d. PLC System Functions

Y1 = CR1.X2 + CR2.X1' + CR3.X2' + CR4.X1

R1' = X1' + (CR2'+X2)(CR4'+X2')

R2' = X2' + (CR1'+X1)(CR3'+X1')

R3' = X1 + (CR2'+X2)(CR4'+X2')

R4' = X2 + (CR1'+X1)(CR3'+X1')

X1STORE NOT

STOREAND

STORE

AND NOT X2AND NOT

OR

X2ORCR2STORE NOT

CR2CR3AND NOTCR1

CR4OR NOTSTORE NOT

X2

X1OR NOTAND STOREOUT CR1

OR

X1CR1

AND X1STORE

AND X2OR CR4

AND STORE

CR1ORSTORE NOT

X1

X1STORE NOT CR3

CR4OUT

STORE

OR

X1CR3

AND

X1AND NOTSTORE

AND NOT X2CR2OR

STORE NOT

STORE

CR2

STORE NOT

X1

CR1

OR NOT

ORCR3

OUT

X1

AND

OR X2STOREAND

STORE

OR

X2CR4

AND

X2AND NOTSTORE

AND X1CR3OR

STORE NOT

STORECR3

STORE NOT

X2

CR2

OR NOT

ORCR4

OUT

X2

ANDX1ORSTOREAND

AND NOT

CR1STOREAND X2

CR2STOREX1

AND

AND NOTOR STORE

X2CR3STORE

AND NOTOR STORE

CR4X1STORE

STORE

ORY1OUT

e. PLC Program

Set 1

Set 2

Set 3

Set 4

Reset 1'

Reset 2'

Reset 3'

Reset 4'

X2OR NOTAND STORE

Y1

R1 = CR2.A.B' + CR4.A.B

R2 = CR1.A'B + CR3.A.B

R3 = CR2.A'.B' + CR4.A'B

R4 = CR1.A'.B' + CR3.A.B'

S2 = CR1.A.B' + CR3.A'B'

S3 = CR2.A.B + CR4.A.B'


S1 = A'B'.CR2'.CR3'

D = CR1.B + CR2.A' + CR3.B' + CR4.A

b. System Original Functions (from 6-4)

Set Functions

Inverted Reset Functions

Output Function

BA

10-16


= A(CR2.B' + CR4.B)

= B(CR1.A' + CR3.A)

= A'(CR2.B' + CR4.B)

= B'(CR1.A' + CR3.A)

OR NOT

610/1

100/0

701/1

410/0

801/0

210/0

1010/0

311/0

511/1

T

1

2

3

4

5

6

7

8

9

10

7

9 108

6

4

5

911/0

3

1

2


X2

1. A security door is connected to a combination lock, that is controlled by two input switches : X1 and X2 .

Actually, door is opened when latest 5 inputs satisfy the sequence 00 , 10 , 11 , 10 , 11 , and closed as soon as

2. The door is opened and closed, by entering the following sequence :

X1,X2 = 00 , 10 , 11 , 10 , 11 ..... 00

Switch

TX1



OpenDoor

Open (T=1) Close (T=0)

input becomes 00.

SwitchCombination Lock

Proper SequenceImproper Sequence


2

3

4

67

10

8

8

8

5

5

5

1

1

1

1

1

1

9

9

0

0

0

0

0

0

0

1

1

1

00 01 11 10

2

1

5

3

e. Merge Diagram

6

4

10

9

7

8

5

00 01 11 10

1

1

1

CR1

CR2

CR3

CR4

CR5

S1 = X1'.X2'S2 = CR1.X1.X2'S3 = CR2..X1.X2

S4 = CR3.X1.X2'S5 = CR4.X1.X2

R1 = CR2.X1.X2'+CR6.X2R2 = CR2.X1.X2+CR.'.X2+X1'.X2'R3 = CR3.X1.X2'+CR6.X1'+X1'.X2'

R4 =CR5.X1.X2+CR6.X2+X1'.X2'R5 = X1'.X2'

CR5

CR2

CR3

CR1

00 01 11 10

CR4

0

0

0

0 0 0

1 1 1

- -

------

- -

T = CR5

g. Merged Flow Table& States Assignment

h. Output Table i. System Functions

Fig. 10-65 : Combination Lock System

X1,X2 / T

X1,X2

X1,X2 X1,X2

8

1

6

10

7

1

1

8

8

9

{1},{2},{3},{4},{5,6,7},{8,9,10}

f. Merge Selection

8 4

2

3

8

1 8

9

1

8

CR6

0

----

CR6

S6 = CR1.X1.X2 +CR5'.X1'.X2 R6 = X1'.X2'

10-17

CHAPTER 11

INTRODUCTION TO ASSEMBLY AUTOMATION

Nonvibratory Feeding & Orienting Devices Vibratory Feeding & Orienting Devices Parts Transfer

CHAPTER 12

ROBOTICS AND NUMERICAL CONTROL

Basic Robot Definitions Basic Geometry Numeric Control (NC) Systems

CHAPTER 13 APPENDIX

Simester Exam Example Simester Exam Solution Typical Simester Exam Questions

1 2 3 4

5 6 7 8

01.07.2003 - QUESTION 1

T = CDE'F + B'C'D'E'G + A'BDF + A'B'CD'E' +

+A'BC'DE + B'CDEF + A'B'E'FG + A'C'DE'F

13-3

00 011110 A

1

2

3

4

5

3

4

5 -

-

-

-

-

-

-

-

1

0

0

0

01.07.2003 - QUESTION 2

210/0

7

2 -

1

FLOW DIAGRAMPRIMITIVW FLOW TABLE

100/1

0

1

2

3

{1,4,5},{2,3}A

B

511/001/0

4

00/0

34

4

5

4

MERGED FLOW TABLE (A)

1 00

0 0

00 011110

4

523

1 2 5

{2,3,5},{1,4}

*

MINIMAL MERGE OPTIONS

13-4

01.07.2003 - QUESTION 3

(IV)

B+

X4

c2

X2

X5

Y3

a1

Y1

b1b2

X1

X3

c1

C+Y2

A+

X6

START

a2

X0

B+

A+

START , , ,C-C+ , C+ ,

B-

,

A-

C-

I I I II I

cr2

cr2

c1

CR2

cr1

cr2

cr1

cr3

cr2

x3'

cr1

Y1

cr3'

cr1

B+

cr2'CR1

cr3

cr2

x0

cr1 cr1

cr3'

cr3'START

cr1

C+

cr2

x2

cr3'

CR3

cr1

CR3

A+

c2

cr3

a1

x6

x1'

Y2

CR1

c1 x5

Y3

CR2

cr3

x6'

x5cr2'

c2

a2 b2

cr3

b1

x4

cr3

X6

X0

CR2

X5OR

CR1

OUT

CR2

AND

OUT

AND NOT

CR3OUT

CR3

AND NOTCR1

AND

STORE

CR2

OR

ORAND NOT

CR3

Y1

OUT CR3

STORE NOT X1OR NOT X3AND STORE

OR

OUT

CR1

Y2

X6AND NOT

Y3

CR1

OUT

STORE

X5AND

AND X2X4AND

PLC BASED DIAGRAMRELAY BASED DIAGRAM

OR CR2

CR3OR

13-5

2 3 4 5 6 7

&

1 8

C+

SEQUENCE

1/n

01.07.2003 - QUESTION 4

,C+ ,

B+

A+ , D-

A-

START , , D+ , ,C- ,B-

start a2 c1

A+

a1

B+

b2 c2 d2 d1

C+ D+ (D-) (B+) (B-)

b1

A+ D+

(B+) (B+)

(C+)

OR

OR

B+

2 3 4 5 6 7

&

1 8

start a2 c1

A+(B+)

a1

FLIP-FLOPSET RESET

A+

B+(A-)

b2 c2 d2 d1

FLIP-FLOPSET RESET

FLIP-FLOP

RESETSET

D+B+ C+

(A-)C+ D+

(B+)(C+)

(D-) (B+) (B-)

b1

2/n

Cell 1 : Unknown length of START.

Cell 2 : A- function opens a2

May cause pulse on A+

Causes pulse on B+

Cell 5 : D- function opens d2Causes pulse on B+ and C+

13-6

INDUSTRIAL AUTOMATION 1 - אוטומציה תעשייתית 1

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