Abrupt Current Switching due to Impact Ionization Effects in Ω-MOSFET on Low Doped Bulk Silicon

Kirsten E. Moselund, Vincent Pott, Didier Bouvet and Adrian M. Ionescu Laboratory of Micro and Nano-Electronic Devices, Ecole Polytechnique Fédérale de Lausanne (EPFL)

1015 Lausanne, Switzerland

Abstract—In this paper, we report very abrupt current switching and hysteresis effects due to saddle point and impact ionization in low doped n-channel Omega-Gate MOSFET (Ω-MOSFET). The Ω-MOSFETs are fabricated on low-doped (8x1014cm-3) bulk silicon by bulk silicon isotropic etching and sacrificial oxidation. A specific abrupt impact ionization and hysteresis of ID(VDS) are observed at high drain voltage (VDS>11V) on transistors that have short channel effects (L=0.9-10um). This is explained by the accumulation of a hole pocket under the gate due to the formation of a saddle point region. An outstanding feature is that this effect can be exploited to abruptly switch from low to high current (2 decades of current) states of ID(VGS) characteristics with ultra-abrupt slopes of 5 to 10mV/dec. Moreover, the hysteresis window ΔVGS~500mV is suitable for DRAM memory. Dynamic switching characteristics and a retention time of up to tens of seconds are originally demonstrated. The proposed Ω-MOSFET stands as a very promising alternative to I-MOS devices, being more scalable and integrable on a standard (low cost) bulk-Si Multi-Gate FET platform. Its experimental performances are promising for both small-slope switches and dynamic RAM memories.

I. INTRODUCTION In recent years there has been increased interest in small slope switches (better-than-60mV/decede MOSFET switch limit) for low stand-by power applications, such as I-MOS [1], Tunnel-FETs [2] and NEM-FET [3,4]. These new devices generally require a relatively large effort for CMOS process modification. In this paper we propose the exploitation of some physical effect found in short channel Ω-MOSFET in order to achieve both abrupt switching and hysteresis effects. It is worth noting that our approach demonstrates that, for some applications the effects that we are trying to suppress in front-end devices, might actually present advantages in other domains. This will be the case for the hysteresis characteristics in a body-tied Ω-gate device presented in this paper. The body of the device is very low doped, which means that even if the devices are fairly long only a moderate VDS is required to achieve punch-through and impact ionization conditions. The geometry of the device results in

an excellently controllable and repeatable hysteresis characteristic, which can be exploited for memory applications. In the following we will first present the fabrication of the devices and their DC characteristics, then a discussion of the abrupt switching and hysteresis phenomena, and finally we will show the dynamic properties, which are of great interest for DRAM memory applications.

II. Ω-MOSFET DEVICE FABRICATION The Ω-MOSFET devices are fabricated according to the process flow depicted in Fig. 1. The substrate is low doped (high-resistivity: 15-25Ω⋅cm) p-type Si-bulk. A silicon rib of 1μm depth is first dry-etched using fluorine chemistry and a hard mask of 15nm SiO2 and 80nm Si3N4.

Figure 1. Process flow showing a cross-section through the channel. 1) Anisotropic rib etching with hard mask. 2) Sacrificial oxidation. 3) Nitride spacer. 4) Oxidation. 5) LTO deposition. 6) CMP planarization and BHF oxide etch to liberate Ω-device. 7). Gate oxide growth (10nm) and poly silicon deposition. 8) Poly-Si patterning and As implantation.

This work was partially funded by the Swiss CCMX program

1-4244-1124-6/07/$25.00 ©2007 IEEE. 287

A sacrificial oxidation of 300nm is performed in order to smooth the sidewalls (to attenuate etching non-uniformity), and to reduce the horizontal dimensions in a controllable fashion. The sacrificial oxide is removed in a BHF bath and 35nm thick nitride spacers are deposited. An isotropic silicon etch is used to partially underetch the nanowire, as illustrated in Fig. 1.3. The nitride hard mask is removed along with the oxide in a HF-bath. A second oxidation follows to repair any etching damage and reduce the dimensions even further. The thermal oxide is removed and replaced by a deposited LPCVD low temperature oxide (LTO). The LTO is planarized in a chemical-mechanical polishing (CMP) step, and partially removed to expose the silicon Ω-structure in the regions where the MOSFET is implemented. An oxide is maintained on the Si bulk surface to isolate the device. A gate stack consisting of 10nm thermal oxide and 100nm poly-silicon (reduced to approximately 90nm, during subsequent oxidation steps) is created. The poly-silicon gate is patterned and isotropically etched, and a self-aligned implantation step of gate, source and drain is carried out (Arsenic, 5x1015cm-2, 40keV, Tilt=7°) using a 40nm thick implantation oxide, which is subsequently removed. The doping is activated by an annealing step at 950oC for 10min. Because of the 3D geometry of the device along with the low diffusivity of arsenic, a part of the gate on the lower concave part of the sidewalls is practically un-doped, as shown in Fig. 2. This results in some high IOFF, which can be controlled by the substrate bias, as explained in the experimental section. Figure 3 shows a SEM view of a Ω-MOSFET.

Figure 2. Finite element cross-section simulation, with arsenic doping in poly-silicon. Inset shows a FIB cross-section of fabricated Ω-gate device on which we modelled the simulation.

III. EXPERIMENT

A. I-V characteristics The fabricated Ω-MOSFET devices show very good ON-current characteristics, but have a relatively high IOFF, due to the un-even doping of the gate. This is a known effect, also observed for other Ω-gate devices fabricated by other groups [5]. By applying a negative substrate bias, this effect can be compensated as shown in Fig. 4, where the IOFF is reduced by approximately three orders of magnitude for VBS=-3V. The

gate leakage is negligible. The threshold voltage of the tested devices is around -200mV. The extracted low field mobility (using the

mD g/I method) is around 400cm2/Vs.

Figure 3. SEM image of an Ω-MOSFET with length L=900nm, and effective width W=2μm. The tilt view is at 45°. The uneven oxide etching is due to the low density deposited oxide, but does not influence device performance.

Figure 4. ID-VGS characteristics for the device shown in Fig. 2. The various curves are monitored by succesively increasign the negative substrate bias VBS, form 0V to -3V in steps of -0.5V.

B. DC abrupt switching characteristics Both ID(VGS) and ID(VDS) very abrupt switching characteristics are observed at high drain voltages, in devices with gate lengths from 0.9 to 10μm. Longer devices do not show such switching. Fig. 5 shows a typical abrupt switching and hysteresis in the breakdown region of the ID(VDS) characteristic, which is also mirrored in the substrate current, IB, albeit at lower current levels. The effect of a negative substrate bias is a shift of the hysteresis curve, but it has negligible influence on the current level. In Fig. 6, the effect of the gate bias on the ID(VDS) hysteresis can be observed; the smaller the VGS, the larger is the hysteresis. This switching effect disappears at VGS of around 1V and applying a negative gate bias has negligible effect. By biasing the device at a drain voltage within the hysteresis characteristic, it is possible to obtain hysteresis in the ID(VGS) curves, which is of greater practical interest. This is shown in Fig. 7. For a VDS of 11.7V a hysteresis spanning about 2.5V is obtained, which gradually disappears when reducing VDS. An outstanding feature is that the abrupt off-on switching can occur for VGS near or below threshold voltage, which suggest

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that this device can be used as a small slope switch, similarly to the I-MOS transistor [6]. In addition, the off-on switching slopes are of the order of 5-10mV/decade, which makes the impact ionization Ω-MOSFET switch similar in performance to I-MOS. Moreover, the structure of our device is simpler and easier to scale down compared to I-MOS. However, in contrast to I-MOS, we observe a large hysteresis between on-off and off-on transitions, essentially controlled by VGS. The understanding of these intriguing characteristics has required systematic measurements and a numerically based physical investigation, which is reported in the next chapter.

Figure 5. Abrupt switching and hysteresis in the ID(VDS) characteristics for both drain and substrate current. The three different characteristics represent different levels of substrate bias. Device with gate length 4.2μm, and effective width 2.0um.

Figure 6. Effect of the gate bias on the ID(VDS) hysteresis, measured on a device of 4.2μm length , and width 2.5μm.

Figure 7. Hysteresis of the gate voltage for high levels of VDS, measured on a device of 4.2μm length, and width 2.0μm.

Figure 8. A) Simulation of the electrostatic potential distribution in the silicon body of a device of channel length 1um. NA=8x1014cm-3. The device is biased in weak inversion: VGS=-0.4V, VDS=11V, VBS=0V. B) Cut through channel center. C) Cut along channel at a depth of 0.1μm.

IV. SIMULATIONS AND DISCUSSION 2D simulations have been carried out using a commercial TCAD program [7] to understand and explain the experimental abrupt switching. It is worth noting that the low doping of the Ω-MOSFET is key to physically explain the device operation. Fig. 8 shows the distribution of the electrostatic potential along the MOS (short) channel. In [8] it was shown that under conditions of channel punch-through, there exists a potential pocket close to the channel, bordered by a saddle point in the channel as shown in Fig. 8.B. The simulation also suggests that the depth of the substrate under the gate has an impact on the position of the saddle point, which shifts towards the source with increasing substrate depth. This may partly explain the very good hysteresis in our body-tied Ω-MOSFET, since the edge part corresponds to a simulation with a fairly shallow substrate. With the existence of the potential saddle point under the gate and close to the surface of the Ω-MOSFET, the phenomena of abrupt switching and hysteresis can be explained similarly to [9]. When the drain bias is increased, the electric field at the drain side of the channel increases, eventually the junction will break down and give rise to a rapidly increasing avalanche current. The avalanched holes will accumulate in the potential pocket close to the interface, see Fig. 8, which suddenly modify the potential near the surface (this being very significant and only possible in a low doped substrate). This corresponds to the very abrupt “pull-up” in the switching characteristics When the carrier concentration reaches the level of the doping, the current becomes space-charge limited. This situation corresponds to the “high” plateau in the hysteresis characteristics. As for the descending direction and the “pull-down”, this was explained in [9] as a redistribution of the potential in the channel, when the free

A

B C

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charge density again becomes less than the ionized acceptor density, which will cause the current to drop to the level of the subthreshold current. However, when comparing with characteristics observed in short channel devices [10] and SOI [11], this resembles more a parasitic bipolar action, which is turned off, when the surface potential is reduced and the source-channel junction reverse biased. Thus, while the pull-up is well understood, further simulations are required to establish the exact model of the abrupt pull-down. Finally, it is essential to note that the condition of punch through requires the use of low doped substrates, and short channels. This is perfectly consistent with the work presented here where we did not observe the hysteresis for devices longer than 10μm. By proper tailoring of low doping levels and device length, it should also be possible to reduce biasing levels and make such an abrupt switch in nanometer scaled Ω−MOSFETs or multi-gate devices.

V. HYSTERESIS AND TRANSIENT EFFECTS The experimental large static hysteresis of ID(VGS) characteristics suggests the use of the saddle-point impact ionization Ω-MOSFET as an elementary 1T DRAM cell. Fig. 9 depicts a typical large experimental hysteresis width (ΔVGS=480mV) around VGS=0.25V (voltage used for reading out the memory cell information) while VDS is maintained at 11.6V. The pull-up voltage is VGS=540mV and the pull-down one is VGS=60mV.

Figure 9. Gate switching ID(VGS) hysteresis measured in a 4.2um long Ω-gate device. VDS is 11.6V and VBS=0. The abrupt pull-up voltage is VGS=540mV while the pull-down occurs at VGS=60mV. Device threshold voltage is VT~0V.

The device is programmed in the low and high state with VGS=-1V (low state logic ‘0’) and 1.5V (high state logic ‘1’), during 30s, respectively. We observe that ''logic 0'' is always stable. Fig 10 shows that the high state (logic 1) is a mono-stable value, with limited retention for the high logic state. The experimental drain current time relaxation from high to low state depends on VGS bias (Fig. 10), the stability of the high state ranges from a few seconds up to tens of seconds. Such retention duration fully demonstrate the potential of this device for DRAM applications. The dynamic ID(VDS) switching response of the Ω-MOSFET was tested up to 100 kHz.

Figure 10. Experimental retention time in impact ionization Ω-MOSFET, corresponding to hysteresis in Fig. 9. The high drain current (logic 1) is measured after programming the device at VGS=1.5V during 30s. – and then applying VGS in the hysteresis region.

VI. CONCLUSION We have reported very abrupt static switching and significant hysteresis characteristics in an Ω-MOSFET, both in VDS and VGS, when a low doped device is operated near breakdown. The current level can be switched 2 decades with slopes of 5 to 10mV/dec, and the hysteresis window can range from 0.5-2.5V depending on biasing conditions. The switching is due to impact ionization and hole pocket formation under the gate, which can be controlled by device doping and biasing. A new 1T DRAM memory operation has been demonstrated.

REFERENCES [1] K. Gopalakrishnan, P.B. Griffin and J.D. Plummer, “I-MOS a novel

semiconductor device with a subthreshold slope lower than kT/q”, Tech. Dig. IEDM, pp. 289-292, 2002.

[2] K. Boucart and A.M. Ionescu, “ Double gate Tunnel FET with ultrathin body and high-k dielectric”, Tech. Dig. ESSDERC, pp. 383-386, 2002.

[3] H. Kam, D.T. Lee, R.T. Howe and T.-J. King, “A new Nano-electro-mechanical Field Effect Transistor (NEMFET) design for low-power electronics”, Tech. Dig. IEDM, pp. 463-466, 2005.

[4] N. Abelé et al., “Suspended-gate MOSFET; Bringing new MEMS functionalityinto solid-state MOS transistor”, Tech. Dig. IEDM, pp. 479-481, 2005.

[5] T.-S. Park, E. Yoon and J.-H. Lee, “A 40nm body-tied FinFET (OMEGA MOSFET) using bulk Si wafers,” Physica E, vol. 19, pp. 6-12, 2003.

[6] K. Gopalakrishnan, P.B. Griffin and J.D. Plummer, “Impact Ionization MOS (I-MOS) – Part I: Device and circuit simulations”, IEEE Trans. Electron Dev. Vol. 52, No. 1, pp. 69-76, 2005.

[7] ISE TCAD tool: http://www.synopsys.com/products/tcad/tcad.html [8] J. R. Brews, “Geometrical Factors in Avalanche Punchthrough Erase”,

IEEE Trans. Electron Dev., Vol. ED-24, No. 8, pp. 1108 – 1116, 1977. [9] A. Boudou and B. S. Doyle, “Hysteresis I-V effects in short-channel

silicon MOSFET's,” Electron Device Letters, vol. 8 (7), pp. 300-302, 1987.

[10] V. R. rao, F. Wittmann, H. Gossner, and I. Eisele, “Hysteresis Behaviour in 85nm Channel length Vertical n-MOSFET’s Grwon by MBE”, IEEE Trans. Electron Dev. Vol. 43, No. 6, pp. 973-976, 1996.

[11] G. A. Armstrong, J. R. Davis and A. Doyle, “ Characterization of Bipolar Snapback and Breakdown Voltage in Thin-Film SOI Transistors by Two-Dimensional Simulation”, IEEE Trans. Electron Dev. Vol. 38, No. 2, pp. 328-336, 1991.

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