Behavioral Modeling of Switched CapacitorIntegrators with Application to kAModulators

George Suairez, Manuel Jimenez and Felix 0. FernandezElectrical and Computer Engineering DepartmentUniversity of Puerto Rico, Mayaguez Campus

Mayaguez, Puerto Rico 00680-5000Email: george.suarez @ece.uprm.edu, mjimenez @ece.uprm.edu, fofernandez@tamu.edu

Abstract- This paper presents two accurate behavioral mod-els for switched-capacitor integrators with application to themodeling of low-power high-speed IA modulators. The firstmodel is based on the integrator transient response and in-cludes the effects of the amplifier transconductance, and outputconductance. The second model is based on a symbolic nodeadmittance matrix representation of the system. VHDL-AMS andMATLAB Simulink were used to implement the first and secondmodel, respectively. Simulations for a GSMIWCDMA second-order multibit YA modulators model were performed, exhibitingless than 5.0% of error in the signal-to-noise plus distortion ratio(SNDR) when compared to experimental data.

I. INTRODUCTION

Sigma Delta Modulators (YAMs) are widely used in mixed-signal interfaces as the essential elements of oversampled dataconverters. Such types of converters are essential in applica-tions where signals with low to medium bandwidth need to beconverted with a high resolution and low dependency on thefactors that typically affect the analog front end. Moreover,the advances in VLSI technology and the ongoing researchon these devices shows the potential of YA converters as apromising candidate for high-speed, high-resolution, and low-power mixed-signal interfaces.

The performance of YAMs is highly dependent of theirembedded switched-capacitor (SC) network [1]. Therefore,detailed behavioral models of SC integrators become necessarywhen modeling YAMs. The increase in frequency on high-resolution, high-speed discrete-time (DT) YAMs, has madethe incomplete settling of SC integrators one of the mostlimiting factors in the performance of YAMs. Although adetailed settling of the integrator is not strictly necessaryfor the modeling of YAMs, a robust model is convenientand becomes crucial in high frequency applications [2]. Theneed for such model arises from the relationship betweenthe degrading effects of harmonic distortion and their powerconsumption.

This paper presents two behavioral models for SC integra-tors with application to the modeling of low-power, high-speedYAMs. The first model is based on the integrator transientmodel including the effects of the amplifier transconductanceand output conductance relation, while the second model is

This work was supported in part by Texas Instruments through the TI-UPRM Collaborative Program.

based on a symbolic node admittance matrix representationof the integrator. The models were developed in VHDL-AMSand MATLAB Simulink, respectively, and used to simulatea GSM/WCDMA second-order multibit YAM. The paper isorganized as follows. Section II introduces the two behavioralmodels for SC integrators. Validation and simulation resultsare discussed in Section III. Finally, concluding comments aremade in Section IV.

II. CONSIDERATIONS IN SWITCHED-CAPACITORINTEGRATORS

One of the main limiting factors in the performance ofdiscrete-time (DT) YAMs is the incomplete settling in SCintegrators [1] [3]. The defective settling of the SC integratoris mainly caused by the operational transconductance amplifier(OTA) characteristics such as the finite DC gain, finite gain-bandwidth (GBW), and slew-rate (SR) limitations. Conse-quently, a detailed settling model of the integrator becomesessential in the analysis of high speed YAMs. To illustrate theintegrator settling model consider the stray insensitive doublebranch SC integrator schematic shown in Fig. 1.

Cint

Vik~~~~~~~~~~~ciC01~~~~~~~~~~~~~0 C, 21

02 V01 +

CP +4, C, 2 C ~ Ct 42

02

Fig. 1. Typical stray insensitive double branch SC integrator

For the integrator settling model, the OTA is assumed to bea single-pole amplifier with small-signal transconductance gm,output capacitance CO, and output conductance g, as illustratedin Fig. 2. In addition to the OTA characteristics, the relevantparameters for the SC integrator model are the sampling ca-pacitors Ci and Cr, the integrating capacitor Ci,t, the amplifierinput parasitic capacitance CP, the load capacitance CL dueoutput node capacitance C0 plus the integrating capacitance

1-4244-0173-9/06/$20.00 ©2006 IEEE.709

bottom plate capacitance Ci,tp, the maximum amplifier sup-plied current I, and the next stage capacitance Cin,t. Formost designs it is assumed that gm >> g, which may not bethe case for low-power designs where the transconductanceturns out to be smaller. Consequently, as gm becomes smallerand the frequency increases, this assumption can introducedisagreement among established models. To include theseeffects, this work introduces two behavioral models for the SCintegrator. One of the models is based on the SC integratortransient response including the OTA output conductance,while the other is based on the symbolic representation ofthe system node admittance matrix.

Moreover, the amplifier response relies on the relationbetween Vai,j, Il/gm, and the slewing time to. Depending onthe initial voltage Vai,i three cases are described:

1) (Linear) Vaij i < I,/gm

Vo,eq (geq Vo,eVaf,i = Vai,i + exp -eq (2)() A)ewng Ceq) A

2) (Slewing) Vaji, > Io/gm, and t < to

Vaf,i [Vai,i + Vo,eqI+y7

ova+so}w(s-vaV0-0 V +

Fig. 2. OTA model

A. Switched-Capacitor Integrator Behavioral Model IncludingOTA Output ConductanceThe limitations introduced by the defective settling in the

SC integrator are better described by its transient model [4].Table I illustrates the parameters used in the transient model. Inaddition to those mentioned in the previous section, the mostrelevant are the sampling time Ts, and the voltages stored atthe input and reference capacitors vi and Vr. Furthermore, thevoltages v' and v' are said to be the voltages stored at the inputand reference capacitors, respectively, including the resistanceR effect of the switches during the sampling phase.

Let Va,n-I and vo,n1I be the amplifier input and outputvoltages from the previous sampling phase, respectively. Thecharge conservation law at the beginning of the integrationphase states that the initial voltage at node va is given by

Vai,i = CI( + Co,e ( Vi,eq)

+ LCp+Co,eq I + CPn Van(1)

TABLE I

SC INTEGRATOR TRANSIENT EQUATIONS PARAMETERS.

Parameter ] Integration Sampling I units

Ci,eq Ci + Cr + Cp Cp FCo,eq _ CO + Cirtp CO + Ci7tp + cit VF

Vi_eq vICi + V/ Cr 0 V_F_ Ci,eq ICin_t

A 1+gm g0g+U __Ceq Ci eq + YCoeq FCslew Co,eq + (Ci,eqCint) (Ci,eq + Cint) F

to IVai Cslew Io Ceq/g s

geq gm+ go (1+ Ci,eq ICint A/go,eq go (1+ Ci,eq Cint) A/VVo,eq _ Vo,n-1+Vi,eq Cint V

.exp ( e t)Ceq

Vo+eq Iosgn (vai,i)I + 7 go,eq

(3)

3) (Partial Slewing) Ivaji,i > I/gm and t > to

)I+ voVaf,i=

sgn (vai)i g Ao]e* exp -geq (t-to)2 AVoeq.e

Ceq A (4)

At the end of the integration phase the amplifier output atthe node v, is given by

Vof,i Vo,eq - I+ C Va,n-I + I1+ C ) Vaf,i (5)

Notice that a similar analysis can be applied for the sam-pling phase but using the respective parameters from TableI. Thus, the charge conservation law states that the initialvoltages at the sampling phase is given by

CinxtVai,s =Vafi-Ci vtf (6)

eq

A similar analysis applies for the amplifier response depend-ing on vai,s and the slewing time to for the sampling phase.To avoid any confusion lets replace vai,i and Vaf,i with Vai,sand Vaf,s during the sampling phase. Consequently, Vaf,s iscalculated from equations (2), (3) and (4). The output voltageat the end of the sampling phase is given by

Vof,s Vof,i + Q + CP ) (Vaf,s- Vaf,i)Cint(7)

Unlike other models, the ratio between the slewing andnon-slewing amplifier loads is considered when modeling thesettling time to as proposed in [5]. Taking in account this effectin addition to the gm/go relationship, the proposed model isexpected to provide a more reliable behavioral model of thedegrading effects of settling errors on high-speed YAMs. AnVHDL-AMS implementation of this model based on equations1 to 7 was completed [6]. It calculates an output sample is foreach system clock phase, namely sampling and integration,providing the advantage that computations are only made atthe points of interest, thus reducing the simulation time.

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Iosgn (v,i,i)go,eq

B. Switched-Capacitor Integrator Behavioral Model based onSymbolic Node Admittance Matrix

In addition to the nonidealities mentioned in the previoussubsection a limiting factor in elaborate YAM designs is theeffect of the non-zero resistance of the sampling switches[7] [8] [9]. Fig. 3 shows the schematic for the SC integratorduring the integration phase including the switch resistance.Considering this resistance in the model influences the gainand pole errors. This is due the fact that the charge transfer isnow also determined by the RC time constant of the samplingnetwork. This effect is included in a model based on thesymbolic representation of the system node admittance matrix.It takes advantage of developments in speed of symbolicmathematical software. The symbolic representation of a linearintegrator during integration can be expressed by Equations (8)and (9).

si

G=

V = [

,Ci+gs 0o sCi+gsgs gs -o o

Civi (0)CrVr(°)

- (Cint + Cinp)Va(O)-VOCx + VaC

-gs 0-gs 0

-2g- s (Cint + Cp) sCintsCint- gm g -SC"

+ CintVo],int

I (8)

In this model, C, Ci + Citp +CO, vo, vi, and vr are therespective node voltages of Fig. 1, R is the switch resistance,and gs= 1/2R. The OTA model used for this derivation isshown in Fig. 2. The slewing integrator can be described inthe same manner for both sampling and integration phase.

These equations are determined for a voltage controlledcurrent sources (VCCS) and an independent current sourcefor the OTA model. We use these equations to determinethe inverse Laplace function to determine the transient nodeequations. This process is fully automated and there is no needfor hand calculations. These equations are then used as inputsto the flowchart in Fig. 4 [10].

The first step in the model algorithm is to determine whetheror not the integrator is slewing. The threshold voltage between

Cint

Fig. 3. SC integrator including the finite switch resistance during theintegration phase with lumped resistance parameter.

these two regions (Vth) is said to be IlIgm. If the OTA is saidto be slewing, the time (t02) at which it stops slewing is foundusing a numerical method. This is the left side of the flowchartin Fig. 4. If t02 exists, only the initial conditions are needed tocalculate the final values of the node voltages. From this pointon it is said that the system is linear implying a change in themodel equations from slewing to linear. The final values ofthe node voltages at time to2 are used as the initial conditionof the linear system.As before, the system is said to be linear if the initial input

voltage Va is lower than Vth, this is the right hand side of theflowchart in Fig. 4. The next step is to determine whether atsome point in time the system will begin to slew or not. To doso the maximum value of Va (Va,max) during the current phaseis determined. vma. is equivalent to the inflexion point of theVa first derivate. If at some point in time va,max is greater thanVth, then from this point on the system is said to be slewing.Otherwise the system is said to be linear. If such a point intime is found (tol), the node voltages at tol are found andthese are used as the initial conditions for the development ofa slewing system as before. If Va,max never reaches the value ofVth then the system is said to be linear all through the currentphase and its node voltages are found.From this description, a MATLAB model was developed.

The MATLAB platform was chosen because it provides asymbolic toolbox based on the Maple kernel and also providesa wide range of DSP functions allowing for information post-processing. This also allows for a fully integrated designanalysis tool to be developed on the same software interface.

Fig. 4. Flowchart of the admittance matrix SC integrator behavioral model.

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III. SIMULATION RESULTS

A. Validation

Simulations were carried for a multibit second-order YAMfor the GSM (200kHz) and WCDMA (2.0MHz) bandwidths.The block diagram of the multibit second-order YAM isshown in Fig. 5. Additional noise and considerations suchas jitter noise, thermal noise, DAC mismatch, and individuallevel averaging (ILA) behavior were included as presented inprevious works [6].

x(n) f f ADyn

< Integrator < < Integrator 5-levels '3 bits

| | ~~~~~4bits 4 bitsl ILA 0 DECODER1

Fig. 5. Second-order Multi-bit SAM

Simulations for the GSM mode (200kHz) were carried foran input signal of 33kHz and -6dB amplitude, and oversam-pling ratio of 65. Fig. 6(a) shows the power spectral density(PSD) obtained with the VHDL-AMS model while Fig. 6(b)shows the PSD obtained with the symbolic node admittance

m50-=

w

00.

FREQUENCY (Hz)

(a)

matrix model. A signal-to-noise plus distortion ratio (SNDR)of 76.57dB was found with the VHDL-AMS model includingthe g, giving a 2.78% of error when compared to the experi-mental data SNDR of 74.5dB. Moreover, an SNDR of 77.59dBwas obtained with the symbolic node admittance matrix modelturning into a 4.15% of error. One important detail is thepresence of third harmonic around 100kHz for the VHDL-AMS behavioral model including g,.

In a similar way, simulations were performed for theWCDMA bandwidth (2.0MHz). For this case an input signalof 300kHz and -ldB of amplitude was used, and samplingfrequency of 46MHz. The PSD plots for the WCDMA sim-ulations with the model including the g, and the symbolicnode admittance matrix model are shown in Fig. 7(a) andFig. 7(b), respectively. For these plots the third harmoniccan be distinguished around 300kHz. Moreover, for thesesimulations a peak SNDR of 47.82dB and 41.02 dB wereobtained. These results yield a 2.41% and 16.29% of errorfor the VHDL-AMS and MATLAB models when comparedagainst the experimental data peak SNDR of 49dB.

B. Speed

As mentioned, the presented model including the OTA out-put conductance used VHDL-AMS and Ansoft SIMPLORERas the modeling language and simulation platform, respec-tively. The symbolic node admittance matrix model used MAT-

_-50 ....

w

0_00-~

FREQUENCY (Hz)

(b)

Fig. 6. Power spectrum for behavioral models validation in GSM mode: (a) model including g, and (b) symbolic node admittance matrix.

a0 -60

. -80

L.

a:S -60

w¢: -80

0-lOop

FREQUENCY (Hz)

(a)

FREQUENCY (Hz)

(b)

Fig. 7. Power spectrum for behavioral models validation in WCDMA mode: (a) model including g, and (b) symbolic node admittance matrix.

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LAB Simulink. Given the commercial nature of these simula-tion tools, the information needed to make an algorithmic-levelanalysis of the time and space complexity of these approachesis not readily available. Despite this limitation, running timesof both methods were recorded for identical test cases, in anattempt to shed some light on the time requirements of bothmethods.

Simulations were carried for 8192, 16394, 32768 and 65536clock cycles in both cases. Table II summarizes the recordedtime results for each simulation and the corresponding modelt.Note the difference between the times for the transient modelincluding the OTA output conductance versus the admittancematrix model. The transient model in VHDL-AMS exhibits anaverage of 0.002 sec/cycle in resolution while the admittancematrix model in Simulink was limited to 0.24 sec/cycle.

TABLE II

SIMULATION TIME FOR THE PRESENTED MODELS.

Cycles II Admittance Matrix Model VHDL-AMS Transient Model8192 31 min 42 sec 15 sec16384 1 hr 4 min 42 sec 30 sec32768 2 hr 12 min 8 sec 1 min65536 4 hr 13 min 5 sec 2 min II sec

IV. CONCLUSION

Accurate modeling of essential blocks, such as the switched-capacitor (SC) integrator, is crucial for the design of YAmodulators. This paper presented two models for SC integra-tors. One of the models is based on the transient responseof the SC integrator including the effects of the amplifiertransconductance and output conductance while the other isbased on the symbolic node admittance matrix representationof the integrator. Both models provide a proper representationof the SC integrator including the effects of capacitive loadchanges, parasitic capacitances, the amplifier transconductance(gm) and output conductance (go) and their relationship, andslew rate limitations. Furthermore, the system representationbased on symbolic admittance matrix includes the effect ofthe finite switch resistance. The transient response modelwas implemented using VHDL-AMS while the symbolicnode admittance matrix model was implemented in MATLABSimulink. Simulation results of a second-order multibit YAMfor the GSM (200kHz) bandwidth exhibited 2.78% and 4.15%of error, for the proposed transient behavioral model andthe symbolic node admittance matrix model, respectivelywhen experimental data was used as reference. Moreover,simulations results for the WCDMA (2.0MHz) bandwidthshowed 2.41% and 16.29% for the transient behavioral modeland the symbolic node admittance matrix model, respectively.In addition, the time requirements for both models werecompared suggesting a possible time advantage for VHDL-AMS models.

REFERENCES

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[2] R. Naikanaware and T. Fiez, "Power optimization of sigma-delta analog-to-digital converters based on slewing and partial settling considera-tions," IEEE International Symposium on Circuits and Systems, vol. 1,pp. 360-364, 1998.

[3] V. Dias, G. Palmisano, P. O'Leary, and F. Maloberti, "FundamentalLimitations of Switched-Capacitor Sigma-Delta Modulators," IEEE Pro-ceedings Circuits, Devices and Systems,, vol. 139, pp. 27-32, 1992.

[4] Sansen, W., "Transient Analysis of Charge Transfer in SC Filters: Gainand Error Distortion," IEEE Journal of Solid State Circuits, vol. 22, pp.268-276, 1987.

[5] F. Fernandez and M. Jimenez, "Behavioral Modeling of DynamicCapacitive Loads on Sigma-Delta Modulators," Seminario Anual deAutomatica Electronica Industrial e Instrumentacion, vol. 1, pp. 119-122, 2002.

[6] G. Suarez and M. Jimenez, "Behavioral modeling of IA modulatorsusing VHDL-AMS," IEEE 48th Midwest Symposium on Circuits andSystems (MWSCAS), pp. 704-707, 2005.

[7] A. Robertini and W. Guggenbuhl, "Errors in SC Circuits Derived fromLinearly Modeled Amplifiers and Switches," IEEE Transactions onCircuits and Systems, vol. 39, pp. 93-101, 1992.

[8] A. Robertini and H. Guggenbuhl, "Modeling and Settling Times ofAmplifiers in SC Circuits," IEEE Proceedings on Circuits, Devices andSystems,, pp. 131-135, 1992.

[9] U. Chilakapati and T. Fiez, "Effect of switch resistance on the SC settlingtime," IEEE Transactions on Circuits and Systems II: Analog and DigitalSignal Processing, vol. 46, pp. 810-816, 1999.

[10] F. Fernandez and M. Jimenez, "Behavioral Modeling of Switched Ca-pacitor Integrators Based on Symbolic Admittance Matrix," SeminarioAnual de Automatica Electronica Industrial e Instrumentacion (SAEEI,vol. 1, 2003.

tSimulations were carried on a Pentium 4 PC with 2GB memory runningat 3.0GHz.

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