11.3 A 1.W digital A/D Converter in 0.18pm CMOS

Christoph J. Braun, Bemhard H. Engl Infineon Technologies AG

Balanstr. 73, D-81541 Munich Munich, Bavaria, Germany

Phone: +49 89 234 26074 Fax: +49 89 234 713159 E-mail: christoph.braun@infineon.com

Abstract

A digital AID converter (DAD) for audio applications is presented. The whole converter consists only of digital CMOS logic and some resistors and capacitors. No linear amplifier is needed. This kind of AD converter is mostly a pure digital design, hence the name and title. A prototype for 20KHz audio applications with a 80dB dynamic range and 44.1KHz output sample rate was designed and processed in 0.18-pm CMOS.

Introduction

The continued scaling of VLSI technology results in a reduced power supply voltage for analog and digital systems on chip. For the digital part, it is no big effort to adapt older designs for future CMOS processes with low supply voltage, because it can be done with automatic tools. In contrast to this, the analog parts, such as in ADCs, require high design effort when migrating to low voltage processes, and face fundamental problems for supply voltages around IV or less.

To overcome these problems and to save time and money, a Digital AD converter (DAD) \vas deve- loped. The main difference to previous ADC is that this digital concept needs no linear amplifier and no precision components, all active devices are CMOS digital logic. Therefore it leads to a pure digital design, except for a few resistors and capacitors. Most of the design can be described with VHDL and migration is almost automated. The DAD principle works with all future supply voltages, as long as a threshold comparator with sufficient gain can be realized and SNR requirements fit to ihe supply voltage range. Because of its reuseable design, a one time development effort fits for all future processes.

Principle of Operation

The DAD principle is based on a linear pulse modulation with constant impulse amplitude [l]. The analog input signal is compared with a sinewave carrier and evely signal crossing point leads to a single output impulse (Fig. I ) . Sm(t) is the analog input signal and S(t) is the carrier, and the crossing points can be seen as a kind of sampling yielding a pulse sequence P(t).

Fig. I Sampling the signal crossings

In the idealized case, the pulses are Dirac impulses and the linear part of the frequency function of this sequence P(t) is G(f) (Fig.2).

.....

LP-Rrnd

Fig. 2 Frequency spcctruni of P(t), G ( f )

The analog lowpass (LP) signal Sm(t) with its maximum frequency Fm is transferred into a bandpass (BP) signal with the frequency fo of the carrier S(t) as the middle frequency, and there is only a signal independent DC level in the LP band. In order to prevent aliasing, the frequency fm of the analog input signal must be exactly not greater than the third part of the carrier frequency f0:

To recover the input signal Sm(t) from the pulse sequence, P(t) has to be multiplied with the sine wave carrier S(t). Then a LP filter with the cutoff frequency fm has to separate the distorted higher spectrum from the LP output signal. As derived from the frequency function G(0, phase errors conceming the sinewave carrier result only in linear distortion. For a DAD, the time intervals between the signal crossings (Fig. 1) have to be digitized and the pulse sequence P(t) has to be filtered by a digital FIR filter for decimation and reconstruction of the input signal.

144 0-7803-7310-31021517.00 02002 IEEE 2002 Symposium On VLSI Circuits Digest of Technical Papers

Implementation

The schematic of the DAD is shown in Fig. 3.

D,g,fal OVlP",

Fig. 3 Schematic of the the DAD

In order to get a pure digital design with no precision components, the sinewave carrier is generated in a digital way with third order Mismatch Noise Shaping [2]. A multibit stream of one period of the sinewave is stored in a ROM and an address counter repeats these samples for every period. The 512 samples are derived from a 3 bit ZA modulator and for reducing the effect of mismatch of the seven DAC resistors, the samples were Mismatch Noise Shaped. The DAC resistors are driven by CMOS gates. A passive LP filter suppresses the high frequency components of the digitally generated sinewave carrier. The analog input signal is superimposed with the carrier and the signal crossing points are detected by a CMOS gate acting as a threshold comparator, or slicer. The output of the CMOS gate controls two high frequency (HF) counters (a,b) for measuring the time intervals. The 2 GHz clock of the HF counters is generated from a free running ring oscillator made up from inverters. In order to make the time interval measurements independent from fluctuations of the ring oscillator frequency, the counting results are normalized to a stable low frequency crystal timebase by another counter and therefore no PLL circuit is needed. The counter results are processed by a FIR filter for decimation and reconstruction. In order to minimize the interference between the analog input signal and the noise from the digital part a digital differential concept was devised: the DAD is implemented twice and the entire digital output signal is derived from the difference between the outputs of the two singlc-etided DADS, each one according to Fig. 3

Measurement Results

Thc complete differential DAD w i t h the FIR deci- n~ation filters was fabricated in a digital 0.18 pm CMOS process. All active deviccs are CMOS logic standard cells and RAM and ROM macros.

The only limiting factor for the supply voltage is in the digital part. mainly the static RAMS, which were specified for 1.8V and did not work with a supply voltage less than 1.2V. Both FFT (Fig. 4) and THD+N ratio (Fig. 5) were measured with a supply voltage of only 1.25V. A dynamic range of 80dB and a THDiSNR of 73dB is achieved. Active area is 1.05m" including the digital FIR filters. An audio amplifier was connected with the digital output of the DAD, and the perceived sound quality was excellent with no discemible inter- ference.

TABLE OF PERFORMANCE

Teclmology : digital 0.18p111 CMOS Active nren : 1 . 0 5 n d Supply voltage : 1.25 V-I .95V Power cot~sumpriori : 7.2mW@ 1.8Volt supply Input baridwidth : 0-20Kf i i Osrpfrt sample rare : 44. IKHz @ I6Bir Dynamic range : 80dR THD+SNR : 73dR PSRR : 48dB

4k 8k 12k 16k 20k

HZ

Fig. 4 FFT 4KHz input signal

kudo Premm A-AFFI SPECTRUM ANALYSIS W12W 17 1541

a I I API

2002 Symposium On VLSl Circuits Digest of Technical Papers 145

1 1 I I I I I I

~ 7 0 4 0 -50 40 -10 .?U .,o to (81

Fig. 5 THD+N-ratio vs inpui level

Conclusion

Digital techniques tradin!: time resolution against analog signal processing show significant potential for ADC and DAC in deep submicron processes.

References

[ I ] C. Braun. "Verfahren zur Analog-Digital-Wand- lung," Patcntschrift DE 43 33 90s C2. October [2] C. Braun. Infincon Technologics AG, "Lincarized Multihit DigitallAnnlog Convxtcr ...," US Patent Appli- ciltion PCTIDE99IO1979, J u l y 1999.

1993.