TRNG I HC VINH KHOA CNG NGH= = = 0o0 = = =

Hng dn s dng DXP Mn : ng dng CNTT cho TVT

Sv : L Vn Vnh Lp : 49KTVT Mssv : 0851080337

A . Ci t DXP 2004 :Ta vo Crack DXP sau lm theo cc bc sau : Nhp p chut vo biu tng setup.exe ci t.

Click chut v o NEXT tip tc ci t :

Tip theo chn I accept the license agreement ri click vo NEXT ci tip:

Mn hnh s hin ra nh sau : (chn NEXT)

Tip tc chn NEXT,

Mn hnh s hin ra nh th ny :

Cui cng click Finish hon tt vic ci t :

B . S dng DXP : Khi khi ng chng trnh ca s thit k s hin ra nh sau :

1.

To mt Project mi : - to mt project mi trn mn hnh khi ng chn : +Creat a new board level project

+ Hoc FILE

NEW

PCB Project

to mt ti liu schematic : + vo File New Schematic + Click chut phi vo project chn New Schematic Ti liu Schematic mi to c tn l xxx.schDoc , c lit k di mc Schematic sheet. - Mt s lnh trong cc menu ch Schematic Editor : +File : cha cc lnh con lien quan n vic to mi, qun l cc tp tin thit k s mch in. +New : Hin khung thoi Select Document Type thit k vin chn th loi i tng thit k s mch in. +Open : Hin th hp thoi Open Document lit k danh sch cc tp tin s mch in c lu trong chng trnh thit k vin chn hin ln trang thit k x l. +Close : ng khung ca s thit k hin hnh ca chng trnh protel v khung mn hnh trng ca khung mn hnh Protel Design System t y thit k vin c th v s mch in mi vi lnh New hoc m tp tin c vi lnh Open +Close Project : ng khung ca s hin hnh ca chng trnh Protel v khung mn hnh trng ca khung mn hnh Protel Design Sytem t thit k vin c th v s mch in mi vi lnh New hoc m tp tin c vi lnh Open +Save : lu bng thit k s mch in theo tn c +Save As : Hin th khung thoi Save Document As lu bng thit k s chi tit mch in theo tn mi cng vi ngun cha tu chn +Save all : lu li ton b i tng vi tn c +Save project : lu li ton b i tng trong trang thit k theo tn c-

+Edit : cha cc lnh lin quan n vic x l cc i tng trong ti liu Schematic hin thi +Cut : ct i tng trong trang thit k hin hnh sau dn sang trang thit k mi , sau khi ct i tng b ct khng cn trang gc +Copy : sao chp i tng trang thit k hin hnh sang trang thit k khc hoc cng trang thit k to thm cng mt phin bn hoc nhiu phin bn hoc dn sang chng trnh khc. Sau khi copy, i tng vn hin din ngay v tr gc.

+Paste : Dn i tng c Cut hoc Copy vo v tr no bt k trong trang thit k hin hnh hoc trang thit k mi hoc sang chng trnh khc minh ho theo dng ba chiu. Lnh ny cho php to mt mng i tng t mt i tng ban u Thc hin nh sau : Sauk hi Cut hoc Copy con tr tr thnh hnh ch thp, t Menu Edit

,chn Paste Array , mn hnh hin khung thoi Setup Paste Aray, khi cn thay i cc tham s cho thch hp trong khung thoi (sau khi thay i click OK ).

Mun chuyn i tng n v tr bt k trong trang hin hnh th click chut tri vo v tr Mun dn i tng sang trang thit k khc cng mt chng trnh , click menu File chn Close thot. T menu File , chn New ,chn th loi i tng va click OK m trang mi. Click con tr mouse vo v tr bt k dn i tng + Clear : Xo i tng chn trong trang thit k. Lnh c chc nng tng t nhn phm Delete trn bn phm + Find Text : hin khung thoi Find Text thit k vin nhp cc i tng k t mun tm x l. +Replace Text : Hin khung thoi Find Text and Replace thit k vin nhp v thay th cc i tng k t

mun tm trong trang thit k hin hnh .

+Select : Hin menu cha cc lnh lin quan n vic chn i tng trong trang thit k hin hnh

+nide Area : Chn cc i tng nm trong vng chn +Outside Area : Chn cc i tng nm ngoi vng chn +All : Chn tt c i tng nm trong trang thit k hin hnh. +Net : ch chn cc ng ni mch gia cc linh kin

+Connection : Ch chn cc im ni mch gia cc ng mch in +Toggle Selection :Chuyn qua li trng thi chn cc i tng trong trang thit k hin hnh bng cch click chut tri hoc nhn phm Enter. Lnh thng c s dng khi thit k vin mun nhanh chng thm v di chuyn i tng . Cc i tng chn s c ng khung theo mu v c xc nh trong khung tham s Options Preferences. +Deselect : Hu b nhng tc v chn trc vi lnh Select +Delete : Xo i tng chn . Lnh c chc nng tng t phm Del trn bn phm. + Duplicate : To ra mt i tng mi l bn sao ca i tng chn. +Rubber Stamp : Chc nng tng t nh Paste Array, sao chp i tng chn thnh nhiu bn, nhng ch trn ti liu Schematic hin thi. Click chn i tng sau chn Rubber Stamp, di chuyn con tr n v tr bt k cn t tip i tng +Change : thay i i tngnh linh kin , thuc tnh hoc k t chn trong trang thit k hin hnh.Th d, thay i linh kin trong bn thit k s mch chi tit xxx.SchDoc, click p vo linh kin mun thay i. Mn hnh hin ca s Property ca i tng.

+Move : di chuyn i tng chn n v tr ph hp

thc hin click vo i tng gi chut ko i tng n ni cn di chuyn sau th chut ra.click chut phi kt thc lnh + Align : Hin menu cha cc lnh lin quan n vic iu chnh v tr ca i tng ang th hin trong bng thit k hin hnh

+Jump: Hin menu cha c thnh phn lnh lin quan ti vic di chuyn con tr ti v tr chn x l.

+ Set Location Marks : Hin menu cha 10 v tr nh du cc im trong trang thit k hin hnh. + View : cha cc lnh lin quan ti vic quan st cc i tng cng nh x l cc khung ca s thit k hin hnh.Fit Document : Dng hin ton b khng gian lm vic ca bn v. Fit All Objects

Hin r tt c cc i tng trong bn v Zoom Area : Phng to vng lm vic la chn Around Point : Phng to vng lm vic quanh im la chn . Selected Object : t i tng chn vo trung tm bn v . Toolbar : La chn cc thanh cng c h tr cho vic thit k bn v. Workspace Panel : Chn ca s tch cc . Cc panel trong Workspace Panel u c sn pha di mn hnh , c th chn bng cc bm trc tip vo cc th . Status Bar : La chn ny s cho php xut hin y mn hnh cc Panel lm vic c th la chn nhanh hn Gird :Hin cc vch li trn bn v , hin cc im bt thit b khi ni vo nhau 3. S dng cc th vin thit k mch: Th vin( Library) l file cha tp cc thit b hoc tp cc mu (model) hoc c hai. Mu (model) : i din cho cc thit b , s dng trong cc lnh vc thc t. C cc loi th vin c nh ngha nh sau : - Model Library : th vin cha tp cc mu thit b . - Component Library : th vin cha tp cc thit b dng logic. - Integrated Library : th vin cha tp cc thit b c dng logic v vt l. Th vin ny l kt hp ca c hai th vin trn. Protel DXP da trn cc th vin trn nh ngha 3 loi th vin s dng : - Model Library : v d nh SPICE : mi mu thit b cha trong mt File, hay PCB footprint : tp nhiu mu vt l ca cc thit b.

- Schematic Library : cha cc lin kt ti cc i tng trong cc Th vin khc, l cc Model Library. - Integrated Library : Cc Th vin truyn thng thng c cu thnh bi cc loi i tng ring l, nh Th vin PCB footprint hay Simulation Model . Schematic Library ch cha cc lin kt ti cc i tng cha trong cc Th vin khc, ch bn thn cc i tng ny khng tn ti trong Schematic Library. Cc lin kt ny c th khng c gi tr khi x l ring l cc i tng trong Schematic hoc PCB footprint. Do , Th vin Integrated Library c dng cha cc i tng thc t trong Schematic. Cc thit b s dng s c tp trung lai mt ch, khng quan tm n ngn gc ban u. Ta s tho lun vn to th vin Integrated Library sau. Cn by gi s cp n vic thit k ti liu Schematic. Sau khi to ra ti liu Schematic, ta s t cc thit b ln ti liu nh sau: Bt Tab Library gc di mn hnh, ca s Library hin ra nh hnh sau :

Miscellaneous Devices.IntLib l th vin mc nh , cha cc thit b c bn nht nh in tr , t , D zener , tranzitor ca s Library cn m t biu tng ca thit b trn bn v v trn mch in thc t (footprint) . C th chn trc tip thit b trong ca s Library t ln bn v . Khi ang ko thit b trn bn v , c th quay thit b bng cch bm SPACEBAR xem thuc tnh ca thit b , bm TAB. tm thit b cn a vo bn v trong th vin hin ti, c th dng b lc (Hp thoi Dropdown th hai t trn xung). VD : mun tm in tr ta g Res1, tm t g Cap Sau khi t cc thit b ln bn v, ta m hp thoi Property kim tra thuc tnh thit b (Kch p trc tip ln thit b).

Gc di bn phi ch ra cc thng s ca thit b, k hiu Footprint ca thit b l AXIAL-03. theo di cc thuc tnh ca thit b c quy nh trong cc th vin, ta c th chn kiu th vin quan tm (Simulation, Signal Integrity, Footprint), sau chn Edit.

Nu chn Simulation, hp thoi m ra l hp thoi SIM Model_General/Generic Editor, gm c 3 Tab : General, Parameter, Pin Mapping. i vi nhng thit b nh in tr hay t in, ch c gi tr (Ohm,P) l cn phi quan tm, v trong Tab Parameter ch cha gi tr ny. Cn trong trng hp i tng l ngun cp, trong Tab ny cha rt nhiu tham s quan trng ca ngun.

i vi ngun hnh Sin : - AC Magnitude : Thit lp tham s ny thnh 1 nu mun u ra bin thin quanh 0. - AC Phase :Pha ca xung AC c gi tr nh. - Delay :Khong thi gian tr hon trc khi ngun hot ng. - Amplitude : Bin tn hiu. - Offset : Thnh phn mt chiu trong xung. - Damping Factor : t cc mc m ti xung b suy gim bin . - Phase : S thay i pha ca xung ti t=0. Ta c th thit dt cc tham s to ra cc xung nh sau :

i vi cc xung khng phi l hnh Sin th cn c mt s thuc tnh ng ch sau: - Initial Value: Trng thi ban u t=0. - Pulsed Value : Gi tr tn hiu lc n nh. - Delay :Khong thi gian tr hon trc khi ngun chuyn t trng thi ban u (t=0) sang trng thi n nh. - Rise Time :Khong thi gian cn thit chuyn t Initial Value sang Pulsed Value. - Fall Time : Khong thi gian cn chuyn t Pulsed Value sang Initial Value - Pulse Width : D rng ca xung Pulsed Value. - Period : Chu k xung. Trong Tab Pin Mapping m t hnh dng Logic ca thit b s c t trn ti liu Schematic. i vi cc thit b c bn nh in tr, t in tt c cc chn u hin trn bn v. Cn vi cc thit b nh cc IC gm nhiu thnh phn c chc nng ging nhau, ta c th ty chn thnh phn no s hin trn hnh v. V d nh trong hnh sau l con IC LM833M gm hai b khuch i thut ton, gm c 8 chn, hai chn 8,4 l hai chn ngun dng chung cho c hai b, cc b chn 1,2,3 v 5,6,7 c vai tr nh nhau, l cc chn IN+, IN-, OUT . Ta c th tu chn dng phn no ca thit b bng cch nhn vo nt >> chuyn qua li.

Trong trng hp ca s Property ta chn th vin Footprint, s hin ca s PCB Model m t chi tit thit b hnh dng thc t. y cng l hnh dng thc t ca thit b s c t trn mch in, v do nh sn xut quy nh. Ta c th thay i hnh dng ny trong mi trng PCB Editor Library , nhng c th lm sai khc i tng. Tt nht l khng thay i hnh dng mc nh ca thit b, ch khi to nhng thit b mi theo yu cu th mi dng mi trng PCB Editor Library. Nu ta cn thm thit b khng c trong cc th vin hin ti ang s dng, ta phi tm kim thit b trong cc th vin ca Protel tm thit b, bm nt Search trong ca s Library m ca s tm kim. Trong ca s tm kim, in cc gi tr cn tm nh tn thit b, loi thit

b Nu tm thy, th vin cha thit b yu cu s hin th, nhn nt Install Library thm th vin vo danh sch cc th vin ang dng. Ngoi ra, nu ta bit tn th vin cha thit b, ta c th trc tip thm vo hay loi i cc th vin ang dng bng cch chn nt Library trong ca s Library. Sau khi t y thit b ln bn v Schematic , ta tin hnh ni cc thit b li vi nhau theo s d thit k. Cc phng tin ghp ni c t trong Menu Place hoc tin dng hn, ta bt Toolbar ca n ln bng cch chn : ViewToolbarWiring. Ta s gii thiu cc lnh trong mt s Menu trong ch Schematic Editor: Design : - Update *.PcbDoc :

Chuyn bn v thit k thnh cc thit b thc t trn mch in . Ca s Engineering Change Order hin ra , yu cu xc nhn cc thit b c chuyn ln mch in . Chn Validate Changes xc nhn la chn. Nu trong qu trnh x l m khng tm ra hnh dng thit b trong Th vin PCB Footprint , thit b s khng c xc nhn . Sau chn Execute Changes thc hin cng vic .

Chn Report Changes xem cng vic s thc hin , cc thit b no s c a ln mch in . Chn Close kt thc cng vic. Kt thc cng vic , trn mch in s xut hin cc thit b vi hnh dng thc t. Ta c th tu sp xp chng trn mch in. - Borrow Library : Bt ca s Library, tng t vic chn panel Library y mn hnh . - Add/Remove Library: Bt ca s thm hoc loi b cc Th vin hin thi ang s dng. - Make Project Library : To Th vin cc thit b hin dng trong bn v di dng File Project.Schlib. Ta c th thay i hnh dng thit b trn bn v , v tr cc chn, biu tng chn trong ca s Library Editor pha di mn hnh. Trong th vin .SchLib, hnh dng cc thit b ch l hnh dng Logic, d thay i n cng khng nh hng g n hnh dng ca thit b trong thc t. Do , ta c th tu thay i cho ph hp vi bn v tng tnh sng sa, r rng. Tuy nhin, khng nn thay i hon ton hnh dng ca thit b, s gy ra nhm ln khi theo di thit k. Bin dch mt Project: Sau khi hon thnh bn v thit k Schematic, ta tin hnh bin dch i tng bng cch chn : ProjectCompile PCB Project. Ca s Compiled xut hin nh hnh sau :

C th bt ca s Compiled bng cch chn Tab Compiled gc di mn hnh. Ca s Compiled lit k cc thit b, cc on dy ni ... trong bn v Schematic. C th la chn trn ca s ny xem chi tit kt ni tng i tng . Ca s Compiled thng c s dng km vi ca s Compiled Object Debugger. Khi ta la chn mt thit b hay mt thnh phn thit b trn ca s Compiled, ni dung ca thnh phn s hin ra chi tit trong ca s Compiled Object Debugger, ng thi, thnh phn cng c nh du v phng to vo gia mn hnh trn ti liu thit k Schematic. Ngoi ra, ta c th s dng ca s Navigator bng cch kch vo Tab Navigate goc di mn hnh theo di thit k, kim tra cc thit b, kim tra tnh ng n ca thit k. Hai tu chn Navigate Nets v Navigate Violations cho php xem cc Net ca thit k, kim tra nhng sai st ca Net nu c.

- Navigate Component : Hin danh mc tt c cc thit b trong tt c ti liu Schematic ca Project hin thi. Khi ta nhp chut tri vo thit b no, thit b s t ng c nh du v chuyn vo trung

tm. Nhp p vo thit b trong hp thoi Navigator s m ca s thuc tnh thit b. - Navigate Nets : Lit k tt c cc Net ca Project, tnh nng tng t nh trn. - Navigate Violate : Lit k tt c cc li ca thit k. Mt s Option m ta c th chn la thun tin cho cng vic : - Mark : Tt c cc thnh phn tho mn yu cu u c nh du trn ti liu Schematic hin thi. V d nh vi truy vn trn, trn ti liu Schematic m ta ang thc hin, tt c cc thnh phn khng phi l Pin u b m i. - Select: Cc thnh phn tho mn yu cu s c chn trong ti liu Schematic, tng t nh khi ta ra lnh la chn cc thnh phn trong thit k. - Zoom : thnh phn c chn s c phng to gia mn hnh thit k. - Graph : V ra trn ti liu Schematic nhng ng minh ho tm thi cc mi thit b kt ni ti thit b ang xt. Cc ng minh ho ny s mt i khi ta chn thit b khc. Ta s gii thiu thm mt s hp thoi lm vic trong mi trng Schematic Editor: Hp thoi List : Ca s ny lit k cc thit b tu . Ta s quy nh cc thit b no c lit k nh vo truy vn trn cng. Nhn vo Helper m ca s h tr to truy vn. V d trong hnh bn ta mun lit k tt cc cc Pin trong thit k, ta chn hm IsPin, nhn Apply, kt qu s hin ra theo yu cu.

Trong ca s ny c mt s tu chn gip ta quan st d dng hn : Cc tu chn Mark, Select, Zoom c tnh cht tng t nh trnh by pha trn. - Clear Existing : Loi b cc thnh phn ang lit k hp thoi pha di khi ta s dng truy vn mi. Nu ta mun tip tc thm cc thnh phn mi vo hp thoi quan st th phi b la chn ny. Hp thoi Inspector: Hp thoi ny m t th loi cng mt s thuc tnh ca i tng ang c chn trn bn v thit k.

Hp thoi Message : Hp thoi Message l ni lit k tt c cc cnh bo(Warning), li(Error) trong thit k khi ta yu cu tin hnh mt cng vic no cn tnh ng n v Logic thit k

Gi lp hot ng ca mch : Ti liu Schematic l cc tp cc thit b lin kt logic vi nhau.Nhng kim tra v thc thi thit k th cn phi chuyn sang mu khc nh Simulation , PCB layout, Signal Integrity Analysis, EDIFChng li cn thng tin v cc thit b, v cch nh x thng tin ny n cc chn thit b trong thit k Schematic. Sau khi hon tt bn v Schematic, ta mun kim tra tnh ng n ca thit k ph hp yu cu mc tiu ra, tc l thc hin c cc chc nng mch mong mun, ta c th gi lp a cc tn hiu vo v quan st dng tn hiu ra tng ng. Trc ht ta s thit t cc tu chn bng cch vo : Design SimulateMixed Sim. Hin ra ca s Analyses Setup :

Phia bn tri l danh mc cc tu chn iu khin, cn quan tm nhiu n mc Transient/Fourier Analysis :

Mc ny ta thit t thi gian bt u, thi gian kt thc,bc thi gian cho vic gi lp. Nu mun dng cc gi tr mc nh, nh du vo Use Transient Defaults, cn nu khng, ta t t ly cc gi tr thi gian khi u, kt thc,cc bc thi gian cho ph hp vi tn s tn hiu a vo. Trong ca s Analyses Setup cn cho php ta thit t nhiu tham s khc trong qu trnh phn tch mch: Tn hiu AC nh, tn hiu nhiu, phn tch Monter Carlo, cc gi tr trong phn tch Spice Sau khi hon tt thit t, nhn ENTER,nu khng c li xy ra, mt ti liu Project.sdf c to ra, cha cc mu sng trong mch m ta mun quan st.

Trong ca s hin sng ny,ta c th thm, bt cc tn hiu ti cc im mun quan st bng cch chn PlotNew Plot( hoc Delete Plot) Protel DXP lkhng ch cho php ta quan st tn hiu n thun ti 1 im trong mch, m cn cho php ta thc hin cc php ton vi 1 hay nhiu tn hiu ri xut dng sng ca kt qu ra Plot.Vic ny c thc hin thng qua ca s Add Wave to Plot :

Ta cng c th thm vo cc trang biu c th c thm khng gian quang st cc sng cn kim tra. S dng lnh ChartNew Chart Ngoi ra ta cn c th thm vo trang m t cc biu FFT ca tn hiu trong thit k. Phn tch Signal Integrity : Phn tch ng truyn tn hiu. Thc hin phn tch ny bng lnh :DesignSimulateSignal Integrity. Hp thoi Signal Integrity Analyses Setup Schematic Mode xut hin

Trong hp thoi ny cho php ta thit t v xc nh nhiu phng thc phn tch ton vn tn hiu m ta mun thc hin trn ti liu thit k hin thi. Hp thoi ny chia lm hai phn chnh: Phn bn tri, vng Analyses, ta thn vo cc trang kt qu phn tch, vi tn New Sim n. Khi ta thm vo y mt i tng mi, th khi hin th kt qu s c thm trang mi ny. t Analyses Type ch Reflect hoc CrossTalk.

Phn Select Analyses cha danh sch cc Net c trong ti liu thit k, ta c th tu chn phn tch mt hay nhiu Net ng thi. Chn qu nhiu Net c th gy mt thi gian cho vic phn tch. Nhp p hc chn > chuyn Net sang danh sch c chn phn tch. Khi chn mt Net phn tch, tn ca Net c t gc trn bn Phi hp thoi , ng thi cc danh sch cc Pin ca Net c lit k gc di ca hp thoi. Trong ch CrossTalk(Nhiu xuyn m), cn thit t mt trong cc Net l Aggressor hoc Victim. Thit t Aggressor cho mt Net ngha l Net sinh ra tn hiu tc ng vo tt c cc Net khc, b nhn nhiu xuyn m t Net . Cn ngc li, thit t Victim cho mt Net ngha l Net b tc ng bi nhiu xuyn m t tt c cc Net khc trong danh sch phn tch. Nt Screening cho php ta thc hin cc hot ng trc khi phn tch trn cc Net c chn. Khi nhn nt ny, hp thoi Screening m ra, cho php ta quan st tng th cc c trng ca cc Net chn, nh l : Net data( tng di cc on ca Net), Impedance Data( Gi tr ln nht, nh nht, trung bnh ca tr khng cc on) Mc ch chnh ca s dng Screening l xem xt xem Net no cn quan tm phn tch, t m t cc yu cu phn tch chi tit Reflect hay CrossTalk. S dng nt Edit Buffer quan st, thay i cc thuc tnh cc Pin. Cc gi tr cha trong hp thoi ny ph thuc vo loi thit b cha Pin ang xt. Theo di sng hiu: Sau khi kt thc tt c cc thit t, nhn OK, trn mn hnh m ra ti liu *.fds m t hnh dng ca tn hiu phn tch, ph thuc vo rt nhiu tn hiu di li t cc ng truyn(Trace) lin quan. Mt vn thng xy ra l Ringing trong thit k PCB bi s khng khp trong phi hp tr khng gia ng truyn v ni nhn, thng l ng truyn tr khng thp trong khi im nhn tr khng cao. Trong cc mch tc cao, tc chuyn mch nhanh hn, do Rise time cng nhanh hn, vn phn x trn ng truyn li cng r rt. c c mt thit k tt, xt v mt ton vn tn hiu, l c cht lng tn hiu tt trn ng truyn, c ngha l loi tr c tn hiu di li (ringing). Loi tr hon ton tn hiu di li trong thc t l khng th, tuy nhin ta c th gim tn hiu ny n mc nh nht bng cch s dng cc Termination.

Protel cung cp mi trng cho ta gi lp cc Termination m khng lm thay i thit k trong thc t . La chn Termination cho cc Pin bng cch : Trong ca s Signal Integrity Analyses Setup gc di bn phi, chn Pin, sau chn Term. Advisor C 7 loi Termination cho ta la chn kim th. Nu thy thch hp ta c th thm n vo bn v Schematic bng cch nhn nt Place On Schematic.

Trong ca s phn tch, pha bn tri, ta c th chn la Report to ra cc bo co ph tr cho vic theo di phn tch. Ta c th chn nt Preferences m hp thoi Signal Integrity Preferences thit t cc u tin p dng vo vic phn tch. Hp thoi ny gm c 6 Tab : - General Tab : La chn cc cch qun l li ( Hint/Waning) trong thit k lin quan n vic phn tch. Cc li s c lit k trong hp thoi Message. - Configuration tab : Thit t cc ngng lin quan n vic phn tch, v d nh di ti a ng truyn, khong cch ti thiu ca hai thit b

- Reports tab: Cc loi Report s c to ra khi thc hin phn tch. - Integration tab : Ch ra mt s cc hng s kt hp trong gii php s dng phn tch. Phng php Trapezoidal th tng i nhanh v chnh xc, nhng d b dao ng di mt s iu kin no . Phng php Gear th yu cu nhiu thi gian php hn, nhng tnh n nh cao hn.

- Accuracy tab : Dng nh ngha cc ngg dung sai v thit t cc gii hn cho cc thut ton trn my tnh. - DC Analysis : Dng nh ngha cc ngg dung sai v thit t cc gii hn cho phn tch DC Analyses. Ta c th nhn vo Schematic Mode Setup m ca s cng tn. y, ta c th thit t cc gi tr cho vic phn tch sng hiu trong ch Schematic.

C ch pht hin li v bo li trong mi trng Schematic Editor: Khi mt Project c bin dch , ton b thit k v cc lut l, rng buc c p dng kim tra tnh ng n ca thit k.Ta c th thit t cc chn la trong Project Option bng cch chn : ProjectProject Option. Ca s Project Option gm cc Tab sau : - Error Reporting : Kim tra cc s thit k Schematic.C 7 mc vi phm c Protel quy nh. C th d dng thay i Report Mode bng cch chn 1 trong 4 dng Dropdown Menu bn cnh mi mc. - Connection Matrix : Hin th bng hnh nh kt qu t Error Reporting, biu din 7 loi li quy nh, gip ta c th quan st mt

cch trc quan nguyn nhn gy ra li: li kt ni gia cc chn, kt ni vi cng V d nh trong biu sau, nhn t pha trn, chn Open Collector Pin dng xung n chn c nh du li, chiu sang bn phi n Output Pin : Nh vy giao gia Open Collector Pin v Output Pin bo cho ta bit li ny s c to ra khi bin dch.

Ta c th t trc tip cc mc li cho cc kiu li ny bng cch Click chut tri ln mun thay i cho n khi n chuyn sang mu th hin mc li mong mun.

1. To Th vin Integrated Library : Nh gii thiu pha trn v vic s dng cc th vin trong thit k v tnh cn thit phi to ra mt th vin Integrated Library trong Project.By gi ta s tho lun v cch to v s dng th vin Integrated Library: to mt Th vin Integrated Library, trc ht ta phi to mt Library Project Packet bng cch chn FileNewIntegrated LibraryTrong ca s Project s hin ra Library Project Packet mi ny. Ta s thm vo cc Th vin dng trong thit k .

a. To th vin Schematic Library: Th vin Schematic Library l ni lu tr lin kt ti cc i tng thit b trn ti liu Schematic. to th vin Schematic Library cho 1 ti liu Schematic bt k , ta kch hot ti liu Schematic , ri chn :

C th to th vin Schematic Library tu bng cch chn : NewSchematic Library, sau dng Schematic Library Editor (c th m bng cch bt th Library Editor pha di mn hnh), Tools Copy Component copy cc thit b t cc th vin khc sang. Mi ti liu Schematic Library (.Schlib) mi to ra c xp vo mc Schematic Libraries. b.To th vin PCB Library : Th vin PCB Library cng c to ra tng t nh Schematic Library, Ch khc l ta phi kch hot ti liu PBC (.PCB) Chn Design Make PCB Library c. Thm cc Library vo Library Project Packet : Nhp chut phi vo Library Project Packet, chn Add to Project, hoc Project Add to Project, sau tm cc th vin Schematic Library, PCB Library m ta mun thm vo.C th thm vo cc th vin tu khc nu mun. C mt cch khc thm 1 th vin vo Library Project Packet, nu n c trong ca s Project, ta ch cn gi chut tri ln th vin v ko n vo Library Project Packet. Ti liu Library Project Packet c tn l xxx.LibPkb,sau khi ta thm vo y cc th vin cn, ta s bin dch n thnh th vin xxx.IntLib. ng dn ca th vin ny quy nh trong Project Option Thc hin bin dch bng cch chn : Project Compile Integrated Library, hoc nhp chut phi ln Library Project Packet v chn Compile Integrated Library. Th vin .INTLIB to ra s c t ng thm vo danh sch cc th vin ang dng . Tt c cc th vin cung cp sn cho ta s dng u di dng Integrated Library. d. Sa i Integrated Library : Th vin Integrated Library khng th sa i mt cch trc tip, m phi thc hin thng qua Library Project Packet, sau bin dch li chng trnh ngun Mi trng thao tc vi cc th vin Library Editor:

Khi ta kch hot tp tin .SchLib hoc .PCBLib Protel t ng chuyn sang mi trng lm vic Library Editor. u tin ta s xt mi trng Library Editor cho cc th vin .SCHLib : Trong mi trng ny, ta c th nh ngha, thit k thit b mi, hoc sa i li cc thit b c (sa i hnh dng logic ca thit b) cho ph hp vi bn v Schematic. Tool: New Component : Dng thit k mt thit b mi. Khi chn lnh ny, hp thoi New Compnent xut hin, sau khi ta thm vo tn ca thit b mun to, thit b mi s c cp nhp vo Schematic Library.-

Remove Component : Loi b thit b ra khi Schematic Library. Remove Duplicates : Loi b khi th vin nhng thit b lp Rename Component : Sa i tn thit b

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li.-

Copy Component : Khi chn lnh ny, Hp thoi Copy xut hin cho php ta chn ch n l mt th vin Schematic Library bt k.-

Move Component : Chuyn thit b n mt th vin Schematic Library bt k. New Part : Thm vo i tng dang thit k mt thnh phn k tip Remove Part : Loi b khi i tng ang la chn mt thnh phn (Thng Part cui ca i tng s b loi b)

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- Goto : Chuyn n thit b tu chn trong th vin Schematic ang thc hin. Find Component : Chc nng tng t nh tm kim thit b trnh by trc y. - Updates Schematic : Cp nhp nhng thay i vo ti liu Schematic.-

Preferences : Hin hp thoi Preference trnh by trc. Document Option : Hin ca s Library Editor WorkSpace :

Hp thoi Document Option th hin cc thit t ca khng gian lm vic Library Editor. Edit Part : Tng t nh khi ta kch p vo thit b trong ca s Library Editor, lnh ny m ca s thuc tnh ca thit b, cho php ta thay i, sa hay thit k cc i tng mi. Report : - Component : Hin bo co v cc chn ca thit b ang c kch hot trong ca s Library Editor. Kt qu to ra c cha trong file .cmp. - Component Rule Check : Kim tra cc lut thit k i vi thit b va c ta to ra hay thit b c va c sa i. Kt qu cha trong File .ERR. Library : Hin bo co v tt c cc thit b trong th vin Schematic ang s dng hin thi. Kt qu cha trong File .Rep-

Mi trng Library Editor i vi th vin .PCBLib: Khc vi th vin .SCHLib, cha hnh dng Logic ca thit b cng vi cc lin kt n cc th vin Footprint, th vin .PCBLib cha hnh dng thc s ca thit b, l hnh dng vt l trong thc t trn bn mch in. S kt hp ca hai th vin ny cho ta mt hnh nh hon chnh v thit b, c trn bn v Logic ln trn sn phm cui cng. Mi trng thit k Library Editor cho th vin PCBLib cng tng t nh vi th vin SCHLib, nhng khc v cc thnh phn c dng thit k. Ta gii thiu qua v mt s k hi i tng dng trong mch in thc t: Via : i tng dng thit lp kt ni gia hai Signal Layer trong bn mch PCB.

Via c th l Multi-Layer (Xut pht t Top Layer n Bottom Layer xuyn qua tt c cc lp gia), hoc c th b gii hn gia hai Signal Layer bt k gi l Blink hay Buried Via. Blink via kt ni t b mt n mt Internal Layer bt k, cn Buried Via kt ni hai Internal Layer vi nhau. Via s dng mu sc ca Layer ch ra nhng Layer no c kt ni. Pad : i tng dng to im kt ni gia chn thit b vi Routing trn mch in. Pad thng thng c dng trong PCB Editor nh ngha footprint ca thit b. Pad c th l Multi-Layer (C mt trn tt c cc Signal hoc Plane Layer, c hnh dng c bit v i hi c l khoan kt ni nhiu Layer), c th ch trn 1 Layer, v cng c kh nng kt ni ti 1 Net. Track : L mt ng thng c vi rng nh ngha trc. Track c t trn cc Layer thit lp mt mi quan h kt ni v in gia cc chn thit b. Ngoi ra, Track cn c dng cho cc mc ch khc nh: To cc ng Board Outline, Component Outline, Cch ly ng bin Routing mch in : Routing l mt tin trnh t cc track v cc Via trn mch in kt ni cc thit b Ta gii thiu cc Menu ca mi trng ny : Place: Cha cc thnh phn cu to nn i tng. Arc, Full Circle : C th dng to ra hnh dng ca cc thit b c phn cong, hay to cc ng cong trong qu trnh Routing, hoc ng cong ca bn mch in . Chng ch dng nh ngha hnh dng i tng khi t trn Overlay Layer hoc Mechanic Layer, v t trn Keepout Layer nh ngha cc ng bao ca bng, Mounting Hol Ngoi ra chng cn c t trn Signal Layer m nhim vai tr nh cc Track cong, c kt ni ti cc Net.

- Fill : t mt vng c hnh ch nht ln ti liu hin ti Khi Fill c t trn Signal Layer , n dng to ra mt vng ngn cch hoc mt vng truyn dn ln. Fill c lp y bi cc Track hoc cc on cong v c kt ni vi Net Khi Fill c t trn Power Plane hoc Solder Mark, Paste Mark Layer, n c dng to ra cc vng trng. Fill c t trn KeepOut Layer to ra mt ro chn i vi c AutoRouting v AutoPlacement Trong PCB Library Editor, Fill c dng nh ngha Footprint ca thit b.-

Line : Tng t nh mt Track, nhng khng c s tng tc vi Net. Line c dng cho mt s mc ch nh to ng bin ca bn mch in, ng bao ca thit b, ng bin Keep-out.

String : t mt chui k t ln bn thit k . C mt s chui c k hiu c bit (Thm mt du . pha trc t ng chuyn i thnh cc gi tr trong th vin nu kch hot Convert Special String trn Display Tab trong hp thoi System Preferences ) . Arc _count : S cung Arc trn PBC .Comment - Ch thch cho mt thit b ( dng khi thit k Footprint ca thit b) .Component_Count - S lng cc thit b trn PCB .Designator -Chui xc nh r thit b. .Fill_Count - S lng cc Fill trn PCB .Hole_Count - S lng cc l khoan trn PCB-

.Layer_Name - Tn Layer cha chui .Legend - K hiu ch gii cho s l khoan vt l. .Net_Count - Tng s cc Net khc nhau trn PCB .Net_Names_On_Layer - Tn cc Net trn Layer c th. .Pad_Count - S lng Pad trn PCB. .Pcb_File_Name - Tn v ng dn ca ti liu PCB .Pcb_File_Name_No_Path - Tn ti liu PCB (khng c ng dn) .Plot_File_Name - Tn ca File GerBer Plot. .Print_Date - Ngy in/lp s . .Print_Scale - Tha s t l .Print_Time - Thi gian lp bn in/s

.Printout_Name - Tn bn in .String_Count - Tng s chui trn PCB .Track_Count - Tng s track trn PCB .Via_Count - Tng s Via trn PCB - Via : t cc Via ln ti liu. - Pad : t cc Pad ln ti liu. - KeepOut: Cng ging nh t cc thnh phn tng t trong bng, nhung vi thuc tnh KeepOut : Hng ro ngn cn c Autorouting v AutoPlacement khng i vo.

Tool: Cc menu New Component, Remove Component, Rename Component, Next Component, Prev Component, First Component, Last Component ging nh cc lnh trnh by trong phn SCHLib. Layer Stack Manager: Lnh ny m hp thoi Layer Stack Manager, ni nh ngha cc PCB Layer Stack. C 3 loi Layer c th thm vo Layer Stack : Signal Layers, Internal Plane Layers and Insulation (substrate) Layers.

Sau khi m hp thoi, Layer Stack hin ti xut hin theo mc nh l mt bng hai mt. C th thm vo cc Layer bng cc lnh Add Signal Layer hoc Add Internal Plane trong Pop-up Menu. Cc Layer mi x xut hin pha di Layer ang c chn (tr Bottom Layer). Double-Click ln Layer hoc chn Property m ca s thuc tnh ca Layer. C th c 32 Signal Layer v 16 Plane Layer trong Layer Stack. Trong Layer Stack, ngoi cc Layer dn din( cc signal Layer), cn c cc Layer cc ly in, l cc Core hoc Prepreg. nh ngha tp cc Layer v cc Non- Electronical Layer : Gc di ca khng gian lm vic PCB l mt lot cc Layer Tab, cho php ta la chn lm vic vi cc Layer ring ca mch in. Chn DesignBoard Layer hin ca s thuc tnh cc Layer, cho php xem, thm, loi b mu sc cc Layer. Electronical Layer : Bao gm 32 signal Layer v 16 Plane Layer. C th thm, bt cc Layer thng qua DesignLayer_Stack_Manager Mechanical Layer : C 16 Mechanical Layer cho cc mc ch chung c th c dng trong bn mch in , t ln cc kch thc, bao gm c chi tit cch ch to, hoc c cc chi tit c kh m thit k yu cu . Special Layer:

3 loi Layer c th thm vo : Signal layers : Name Tn ca Layer do ngi dng t. Copper thickness - dy Layer, gi tr ny c yu cu trong signal integrity analysis. Plane Layers Name - Tn ca Layer do ngi dng t Copper thickness - dy Layer, gi tr ny c yu cu trong signal integrity analysis. Net name Tn ca Net kt ni trc tip n Layer. Substrate (dielectric) layers: (Layer ca cc cht in mi) Material - Loi vt liu. Thickness - the dielectric (substrate) dy c yu cu cho signal integrity analysis Dielectric constant - Hng s in mi, dng cho signal integrity analysis Kt ni Power Plane trong PCB Design : Trc ht cn xc nh Power Plane m ta nh lm vic, nu cha c th thm vo bng lnh Add Internal Plane. Double Click vo Layer ny m ca s thuc tnh. Trong ca s thuc tnh, trn Dropdown Menu NetName, chn Net m ta mun kt ni ti Layer. Mechanical Layer : Lnh ny m hp thoi Board Layer, ni chng ta quy nh Layer no c trnh by trong ca s thit k chnh. La chn trong ct Show thay i kh nng c quan st ca Layer . Cc Layer c xp vo cc nhm theo loi ca chng. Double-Click vo mu ca Layer m hp thoi Choose Color, t y ta c th thit lp mu sc cho Layer tu .

Library Option : Hin hp thoi Board Option cho php ta thit t cc tham s ca bn mch in

Cc tham s trong hp thoi ny l n v s dng (milimet hay inch), li Grid Preference : M hp thoi Preferences, ni ta c th thit t cc la chn, u tin cho ti liu. y l nhng thit t c p dng trn ton b cc ti liu PCB. Thay i bt c thit t no s trc tip nh hng n ti liu PCB m bn ang lm vic. Dng Tab Option thit t cc chn la thit k khc nhau, nh l cho php Online DRC hoc cho php tch lu ccs chn la khi thit k i tng. N cung cp cc phng tin nh ngha vic t ng quay i tng v tc , ch tng tc Routing mc nh, v cc c tnh khc : S bc Undo/Redo c th thc hin, s bc xoay, hoc c th gi cc routing kt ni i tng hay khng khi ko i tng. Tab Dislpay c dng thit t cc tham s nh hng n s hin th cua i tng, nh la hin th cc Testpoint, cc thanh trng thi, Net name, Pad number, chn la ch hin th i tng trn Layer c kch hot (Single Layer Mode) hay khng, chn la cch quan st cc i tng trn cc lp khc nhau

Tab Show/Hide dng thit t tnh n/hin ca cc i tng trn ti liu PCB. i tng c th chn cc hin th y (Final), ch hin th tng phn, hin th ng bao ngoi ca i tng (Draft) , hon ton n(Hidden)

Tab Default thit t cc chn la thit k cc thuc tnh mc nh cho i tng trn c th t trn ti liu PCB.C th lu li cc thit t mc nh, ti cc thit t t nhng File lu, hoc Reset li cc gi tr mc nh nh l chng c thit t t u. Menu Report : Librarya Status : Hin bo co v cc thnh phn ca i tng ang c thit k. Nu ta nhn vo

Nt Report, s hin ra bng la chn cc thnh phn ca i tng m ta mun lp bo co. Component : Hin thng tin v thit b, k hiu trong th vin Footprint, v tr trn cc Layer trong mch in. Component Rule Check : Kim tra cc quy tc thit k i tng so vi cc quy nh thit t. Library: Hin chi tit v th vin, tn cc thit b c trong th vin hin ti. Measuare Distance, Measure Primitive : o lng khong cch gia cc phn ca thit b. Khi chn lnh ny, con tr chuyn thnh hnh ch thp. Nhn vo hai thit b m ta mun o lng, khong cch ca chng s hin ra trn mt hp thng bo. By gi ta s trnh by vic thit k bn mch in trong Protel: Sau khi thc hin xong bn v thit k Schematic, bin dch v sa li thit k , ta s chuyn cc thit b t dng Logic sang dng thc t trn mch in. Mch in trong Protel c quy nh c ui PCBDoc, c lit k di mc PCBs. Cc bc to mt bn mch in dng PCB Board Wizard : Bt ca s Files pha di mn hnh , chn PCB Board Wizard trong Panel New from Template, ca s PCB Board Wizard xut hin.Ta bt u thc hin cc cng vic sau: - Nu chn n v l Mils: nh du vo Imperial , nu chon n v l milimet: nh du vo Metric. - Chn Next : Hin ca s lit k cc loi bn mch in theo khun mu. Protel cung cp cho ta mt lot cc khun dng mch in chun cm vo cc khe c sn. Nu mun t la chn hnh dng ca bn mch in, chn Custom. - Trong ca s tip theo, bn tri ta c th chn hnh dng ca mch in, bn phi d chn kch thc cc lp trong mch .

+ Conner Cutoff : chn cc gc ct pha ngoi bn mch , to hnh dng bn gc tu ( nh cu trc cc Card cm vo khe cho sn ) + Inner Cutoff : To cc vng rng bn trong bn mch in . Nu ta n thun mun to mt mch in hnh ch nht, hnh trn hay elip th khng chn hai mc ny . Nu ta nh du la chn Conner Cutoff hoc Inner Cutoff, th hai ca s tip theo cho php ta la chn kch c cc gc ct cc gc ca bn mch v khong trng trn bn mch. - Ca s tip theo cho php ta chn s Signal Layer v s Power Plane. - Ca s tip cho php chn kiu Via trong mch. C th chn Thruhole Via Only (Nu trong mch in ch s dng Multi-Layer,Via xuyn t lp u ti lp cui) hoc Chn Blind and Buried Via Only. - Ca s k tip cho php chn cch gn thit b trn mch in v s track gia hai thit b k nhau. - Cui cng l ca s cho php chn d rng ca track, via, cc khong cch Nhn Finish, mt ti liu c ui .PCBDoc c to ra v thm vo Project. Ti liu ny tng trng cho mch in s c to ra trong thc t. Cc Menu trong mi trng thit k PCB Editor: Do ta trnh by mt s lnh trong cc phn trn, nn ta s khng trnh by li cc lnh nu c s lp li. Trong phn ny ta s trnh by cc lnh mi ng dng ring cho thit k PCB. Menu Edit : - Board : Chn tt c bn mch in. - Net : Chon Net cn thc hin. Khi chn lnh ny, xut hin con tr hnh ch thp di theo chut. Nhp vo Net mun chn. Nu cha r rng th hp thoi Net Name s xut hin, cho php ta chn 1 Net trong danh mc lit k. .

Connection Copper : Chn tt c cc Track c ni ti Track m ta Click vo. Physical Connection : Sau khi chn lnh ny, con tr chuyn thnh hnh du Cng, di chuyn n ti cc Pad mun chn( s xut hin vng trn bt im ti cc Pad), Nhp vo cc Pad ny. Nhp chut phi kt thc lnh, tt c cc Track nm gia cc Pad chn s c chn. All on Layer: Chn tt c cc i tng trn Layer hin ti ang thc hin cng vic. Free Object :

Chn tt c cc i tng t do trn bn mch. Tt c cc i tng c kt ni s khng c chn. All Locked : Tt c cc i tng ca thit k s c kch hot thuc tnh Locked Toogle Selecton : Thay i trng thi c chn hoc khng c chn ca tng i tng c th, khng phi c mt nhm ng thi. Off Grid Pad : Chn tt c cc Grid khng nm trn Snap Grid. - Move : Re-Route : Route li Track c sn. Sau khi chn lnh ny, con tr chuyn sang hnh ch thp. Di con tr n Track mun thay i cho n khi xut hin vng trn bt im, nhn vo Track, sau ko n i theo nhng hnh dng tu thch. Break Track: To cho Track mt nh nhn. Cu lnh ny tng ng ReRoute, nhng chi ko c mt ln. Drag Track End: Ko im cui ca Track sang v tr khc. Polygon Vertices : cho php ta thay i v tr ca cc Track bao ngoi mt Polygon. Holes Size Editor : Thit t kch c cho cc Hole dng cho Via, Pad. C th chn cc gi tr c sn hoc to ra cc gi tr mi. Origin : Set: t im chn l gc ca Grid. Reset: t gc to li v tr tuyt i mc nh ban u gc di bn tri.

Jump : a con tr n v tr chn, l mt Net, Pad, Via m ta ch trong danh sch lit k.

Menu View : Ch c hai lnh mi: Board In 3D : Quan st bn mch i dng khng gian 3 chiu thc t. Connection : Chn cc mc tu cho hin hoc n cc Net, Component trn Layer tin quan st.

Menu Place : sst cc i tng ln bn thit k. Cc i tng ny ta trnh by trong cc phn trc, ch c mt s i tng mi nh : Interactive Routing : t cc Track Porygon Plane : Tng t nh mt vng khng gian c, uc to thnh bi mt nhm cc track, c th kt ni ti cc Net trong phm vi.

Slice Polygon Plane : Chia ct mt Polygon Plane thnh nhiu Polygon Plane lin nhau .Sau khi chn lnh ny, con tr chuyn thnh du Cng cho php ta vch ra cc ng chia ct Polygon c sn. Sau khi thot khi lnh, Polygon Plane ban u s c chia thnh nhiu Polygon Plane.

Menu Design : Menu ny cha cc lnh lin quan n cc thit k trn bn mch in to ra. - Update Schematic : Cp nhp tt c cc thng tin m ta thit k trn bn mch ln ti liu Schematic lin quan. Sau khi chn lnh ny, hp thoi Differences Between Flattened Object xut hin, lit k nhng khc bit gia thit k PCB v thit k Schematic.

-Import Change From: Cp nhp tt c cc thay i trn bn thit k Schematic ngun ln ti liu PCB ang thit k. Lnh ny th hin ging ht nh lnh DesignUpdate PCB khi ta thit k ti liu Schematic m ta trnh by -Rules : y l mt lnh rt quan trng trong thit k PCB. Khi chn lnh ny, hp thoi Rules And Contraints Editor xut hin, cho php ta thit t cc lut thit k, hoc bin tp li nhng i tng tn ti sn trong thit k hin ti.

Cc lut thit k c thit t trn mt din rng, mi lut c mt phm vi ng dng ring.

Cc lut thit k c qun l bi On-line DRC (bo cho bn bit nhng vi phm) v Batch Mode DRC (to ra nhng bo co xc minh cho thit k). Pha bn tri hp thoi l cy lit k 10 Design Rule dng trong thit k mch. Khi ta Click ln mt Design Rule, cc mc con bn trong ca thit k c m ra, cho php ta nh ngha li cc Design Rule hoc to ra cc Design Rule mi. Khi ta Click chut phi ln mt Design Rule bt k cy bn tri, mt Pop-up menu xut hin cho php ta la chn cng vic mun thc hin, nh l thm vo cc Design Rule mi , loi b cc Design Rule, lp bo co

Khi bn thc hin cng vic trong PCB Editor : t cc Track, di chuyn cc thit b, to cc ng dn PCB Editor lun theo di mi hot ng, kim tra xem chng c tun theo cc Design Rule hay khng. Li s uc thng bo ngay khi vi phm. Thit t cc Design Rule trc khi thit k gip ta c th tp trung vo cng vic v lun lun gim st c tnh ng n trong thit k. Mt trong cc tnh nng mnh m ca Protel DXP l c th thit t nhiu Design Rule cho cng mt th loi. mi Design Rule cho mt s i tng ring. Gi s ta c mt mch in n gin, v ta mun tt c cc Track c rng 12 mil, tr GND Track c rng 25mil, ta s thit t mt rng buc ring cho GND track : Chn RoutingWidth pha bn tri ca s, Click chut phi , chn New Rule, xut hin mt rng buc mi, t tn rng buc l GND Trong khung Where the First Object Match chon Net, khung truy vn bn phi s hin ra InNet() .Trong Dropdown Menu la chn ALL chn 12V, truy vn s tr thnh InNet(GND)

Trong khung di, chnh li kch c Min v Max ca 12V track u bng

25mil Nh vy ta to ra cho mch in 1 rng buc mi: tt c cc track trn mch in u c rng l 10 mil, tr 12V track c rng l 25 mil. Ta c th thc hin cc truy vn da vo hp thoi h tr Query Help khi nhn vo Query Builder: y l mt mi trng h tr trc quan cho vic thit k cc truy vn. Board Shape:

Lnh ny dng thay i hnh dng ca mch in m ta ang thit k. - Redefine Board Shape :Thay i hon ton khun dng mch in. Khi chn lnh ny, mch in bin mt con tr chuyn thnh hnh du Cng cho php ta v ra hnh dng mi ca mch in.( Nhn ESC hoc chut phi t ng khp kn hnh v). - Move Board Vertices : Chn lnh ny, sau nhp vo mt ng bin bt k ca bn mch, ko ng bin thnh cc gc. Trong qu trnh lm ny ch c 2 u mt ca ng bin khng i. - Move Board Shape : Ko bn mch n mt v tr tu , cc thit b trn bn mch khng b di chuyn theo. - Auto-Position Sheet : T ng t bn mch quanh i tng nm trn Mechanical Layer v lin kt ti bn mch . Class : Cu lnh ny s m hp thoi Object Class Explorer. Trong hp thoi ny bn c th to ra tn Class (hoc Group) ca i tng thit k.

Class cho php ta xc nh r mc tiu, c th l cc nhm i tng khng lin quan, khi thit k hoc bin tp li cc Design Rule.Class cn c dng khi xc nh cc lp s t vo Room Class ca Nets, Components, Design Channels, From-Tos, Layers v Pads c th c to ra v c nhiu thnh vin. Netlist:

Edit Nets : M hp thoi Netlist Manager ni chng ta c th bin tp li cc Net trong ti liu hin thi.

Trong hp thoi ny ta c th nh ngha thm cc Class mi hoc sa i thnh phn cc Class c. ng thi bn phi, ta c th nhp

vo cc Pin m ca s thuc tnh cc Pad ni vi Pin , t thay i cc thuc tnh ny theo mc ch thit k. Clean Nets... : Lnh ny loi b cc Track tha, lp li trong thit k. AutoRouter thng thc hin cu lnh ny trc khi hon tt cng vic loi b cc li khi thit k. Export Netlist From PCB...: Lnh ny xut ra File .NET cc NetList ca ti liu hin thi. Create Netlist From Connected Copper : Lnh ny to ra File m t cc NetList da trn c s Routing thit k hin thi. Update Free Primitives From Component Nets : Dng ng b li tn ca Net t vic Routing cc thnh phn ban u vi tn ca Net trn cc Pad m chng lin kt ti. Vic ny khng nh hng g n mng Net ca ti liu PCB. Clear All Nets : Lnh ny dng xo sch cc Net trong ti liu PCB. Thc hin cu lnh ny khi ta mun thay i cc Net trong thit k ngun Schematic, v sau ng b li cc Net sa i sang ti liu PCB. Room : C th hiu mt cch n gin, Room l mt phng cha cc thit b trn mch in. Khi ta di chuyn Room th cc thnh phn cha trong n cng di chuyn theo. Ta cn c th sao chp khun dng Room thun tin cho thit k.

Place Rectangular Room/Polygon Room : t mt Room hnh ch nht/a gic ln ti liu PCB. Sau khi t Room, ta c th xc nh cc thit b cha trong Room bng cch m ca s thuc tnh ca n.

Trong ca s thuc tnh ca Room, ta c th quy nh c cc thnh phn s cha trong n bng cch to ra mt truy vn i tng. V d, trong Room_1 mi to thnh, ta mun t cc thit b cha trong Class Sheet1 to ra trc , ta s s dng truy vn : InComponentClass(Sheet1). Tng t nh khi thit k Design Rule, ta c th chn nt Query Builder m ca s tin ch gip ta thit k truy vn d dng hn. Copy Format Room: Dng copy nguyn dng cu trc thit t Routing t Room ngun sang Room ch. Sau khi chn lnh ny, con tr chuyn sang hnh du cng. Ta click vo Room ngun,sau Click vo Room ch hp thoi Confirm Channel Format Copy xut hin, gm cc chn la v im t thit b, Net Routing, Copy kch c v hnh dng Room hay khng Wrap Room around Component: Thay i hnh dng v kch c Room, lm cho Room bc kht xung quanh cc thnh phn ca n.Sau khi chon lnh ny, con tr chuyn sang du cng ta kch vo Room cn thc hin. Create Non-Orthoganal Room from selected components : To ra mt Room vi hnh dng ph hp bao quanh cc i tng chn. Room to ra c cc cnh bin khng vung gc vi nhau. Create Orthogonal Room from selected components : Cng ging nh lnh trn nhng Room to ra c cc cnh bin vung gc. Create Rectangle Room from selected components : Cng ging nh lnh trn nhng Room to ra l hnh ch nht. Slice Room : Lnh ny chia mt Room thnh nhiu Room khc nhau. Khi v cc ng Slice, c rh dng nhng phm b tr c th v nhiu ng vi cc gc khc nhau : SPACEBAR, SHIFT+SPACEBAR. Tool :

Menu ny cha cc cng c phc v cho vic kim tra, hon tt. khim th thit k.

Design Rule Check : Lnh ny m hp thoi Design Rule Checker,ni ta c th kim tra v Logic thit k v tnh thng nht vt l trong ti liu PCB hin thi. Vic kim tra c thc hin da vo mt s hoc tt c cc Design Rule v c th thc hin trc tuyn (Online), tc l ngay trong khi chng ta ang thit k. Cc thng bo li s c lit k ra trong ca s Message hoc trong cc Report.

Trong ca s ny, pha bn tri l cy lit k ra cc Rule chung, nhp vo chng xem ni dung chi tit cc Rule bn trong. Ta co th tu bt/tt cc kim tra kiu Online hay kiu Batch Mode. Online Design Rule Check c th chy nh mt tin trnh ngm, t ng nh du, ngn cn cc hot ng vi phm lut thit k. chn ch ny, ta chn Online DRC trong Tab Option ca ca s System Preperence. Sau khi thit t xong, nhn vo nt Run Design Rule Check chy chng trnh kim tra. Kt qu s c thng bo trong File .DRC mi to ra. Design Rule Check l mt trong nhng c trng quan trng v mnh m, c thc hin t ng,kim tra tnh hp l ca thit k. N thng c s dng trn cc Board khi Routing m bo cc khong cch nh nht thnh phn quy nh phi c tun th. Reset Error Mark: Xo tt c cc im nh du li trn s d thit k. N khng c tc dng sa li cc li . AutoPlacement : - Auto Placer : M hp thoi Auto-Place,cho php ta thit t v chy mt trong hai cng c t ng t thit b (AutoPlacement)

- Cluster Placer : T dng nhm thit b thnh cc nhm trn c s kt ni gia chng, sau t cc nhm ny mt cch hnh hc. Thut ton ny thng ch dng cho cc thit k c s i tng nh, thng l t hn 100 i tng. Cho php chn Quick Component Placement dt nhanh i tng, khng cn ti u. - Statistical Placer : S dng mt thut ton thng k t cc i tng sao cho cc kt ni l ngn nht.C th cp nhp trc tip ln ti liu PCB hoc to ra ca s biu din tu . - Stop Auto Place : cu lnh ny dng dng qu trnh Cluster Placer bt k thi im no khi n ang c tin hnh. Truc khi AutoPlacement, ta cn t trc cc thit b. Nu khng mun di chuyn thit b, t thuc tnh Lock cho thit b . Nu mun t nhng vng khng cha thit b, t thuc tnh Keepout cho vng . - Shove : Cu lnh ny dng chim ch, y cc thit b ang b chng, hoc yu cu sp xp thng hng theo mt trt t ring. Sau khi chn lnh ny, con tr chuyn sang hnh du cng, kch vo thit b mun chn, cc i tng xung quanh n s b y bt ra theo c ly c quy nh trong Shove Depth (11000)

- Set Shove Depth : Dng t gi tr tu (11000) khi dng lnh Shove. - Place From File... : Lnh ny dng nht cc thit b cha trong File ch nh v t n vo thit k. Interactive Placement : Bao gm cc lnh sp xp cc thit b ch nh theo mt trt t tu .

Un-Route : Dng b cc Route c thit lp trc . Vic Un-Routing ny i ngc li vi qu trnh Routing m ta thc hin. C th UnRoute tng phn ca bn mch, nh l cc Net, Connection, Component, Room m ta la chn. Density Map : Hin th biu m t mt cc kt ni trn bn thit k. Nhng vng c mu xanh l mt t, chuyn dn sang mu l mt cao. V d nh ta c biu m t mt thit k LCD Controller :

Reannotate: Dng xc nhn li tt c cc thit b trong thit k PCB. N s t li tn cho cc thit b theo th t chn trong hp thoi hin ra ki gi lnh.

Reverse Designators : Dng do ngc li khun dng ca cc b m t thit b hin th trog ti liu hin ti. Thng c dng trong thit k a knh. N s nh dng li trt t u tin : R2_CIN1, C47_CIN3 s tr thnh CIN1_R2, CIN3_C47. Layer Stackup Legend : Cu lnh ny cho php ta t dng ch thchv cc Signal Layer v Internal Plane nh ngha trong Layer Stack Manager ln ti liu PCB hin thi. Convert : - Explode Component to Free Primitives: Lnh ny dng chuyn thit b v trng thi nguyn thu ca n. Lnh ny khng nh hng g n th vin cha Footprint ca thit b, ch chia thit b trn ti liu thnh cc phn( khng c kt ni

vi nhau).Khng c lnh ti kt hp cc thnh phn li, nu mun th phi dng Undo. - Explode Coordinate to Free Primitives : Chuyn cc to v trng thi nguyn thu ca n. Ta c th tu ko tng thnh phn ca chng i tu . Cng tng t nh vy vi hai cu lnh sau : - Explode Dimension to Free Primitives - Explode Polygon to Free Primitives - Convert Selected Free Pads to Vias: Cu lnh ny chuyn i Pad t do thnh Via. Lnh ny dng khi Import mt Gerber File sang ti liu PCB. - Convert Selected Vias to Free Pads :Lnh ny chuyn Via thnh Pad t do, dng khi Import PADS-PCB v PADS 2000 file, ni m Via c dng kt ni ti Power hoc GND Layer. - Create Union from Components :To mt Union t cc thit b chn, Union l mt nhm thit b c quan h vi nhau nh mt khi thng nht, v vn duy tr nh vy khi ta di chuyn, t li khi. - Remove Component from Union: Dng loi mt thit b hay mt nhm thit b ra khi Union thit t trc. - Remove All Component Unions : Lnh ny dng loi tt c cc Union thit t trc ra khi ti liu PCB hin thi. - Add Selected Primitive to Component: Cu lnh ny dng thm cc thnh phn nguyn thu vo thit b nu nh vic kim tra hnh dng thit b l chnh xc trong PCB Editor. Ch rng thit b ch cng phi c cc thnh phn nguyn thu khng kho mi c th thc hin cng vic. Teardrop Pads: chuyn cc Via/Pad t dng trn sang dng TearDrop. y l mt k thut nhm chng v cc l khoan trong cng on ch to mch in. Khi chn lnh ny, hp thoi Teardrop xut hin, ta c th c cc chn la sau: - All Pad/Via : chn thc hin trrn tt c cc Pad/Via - Selected Object Only : La chn thc hin trn cc Pad/Via m ta thy c nguy c v khi khoan.

- Force Teardrops: p dng TearDrop ln cc Pad/Via gy ra li trong DRC. Equalize Net Lengths : Lnh ny lm cho di ca cc Net ph hp vi lut Matched Net Length.

thi hnh lnh ny, truc ht ta phi thit t cc lut Matched Net Length trn cc Net m ta mun cn bng v di. Khi thit k lut nay, ta c th tu quy nh hnh dng cc Track s thm vo cc Net c c di tiu chun. C th chn cc Track thm vo l ng gp khc vung, gp khc 45 hoc cc cung trn. Outline Selected Objects: Lnh ny dng t cc ng bao ngoi ca mt Track hay bao quanh nhng mu nguyn thu trong thit k, c tc dng cch v in vi cc nt khi t ng bao quanh GND. Find and Set Test Points: Lnh ny tm kim cc Pad v Via tun th quy tc Testpoint trong Design Rule. Cc thuc tnh ca Testpoint s c thit t vo cho cc Pad/Via . Clear All Test Points: Lnh ny dng xo b tt c cc Testpoint trong ti liu hin ti. Preferences : M hp thoi Preferences vi cc chc nng trnh by trc y. Auto Route :

T ng Routing cc thit b, cc thnh phn tu chn trn bn v thit k PCB. Routing l mt tin trnh t cc Track v cc Via trn mch in kt ni cc thit b . Ta c th tu chn Routing c bn mch hay ch Routing mt phn ca n bng cc chn la sau: All, Net, Connection, Component, Area, Room Setup..: Lnh ny m hp thoi Situs Setup Strategies cho php bn nh r chin thut AutoRouter s s dng. T hp thoi ny c th chuyn ngay sang hp thoi Design Rule thit k cc lut cho Routing. Thc ra ta khng cn thit t g trong hp thoi ny, chng trnh t ng chn ra phng php AutoRouter thch hp nht cho thit k. Stop Autorouter: Dng tin trnh Autorouting khi n ang thc hin. Reset : Thc hin li mt phng thc Routing mi nu ta cha hi lng vi cch Routing hin ti. Pause : Tm ngng tin trng AutoRouting. Restart : Khi ng tip tin trnh AutoRouting b ngng trc do lnh Pause. Report : Hu ht cc lnh trong Menu Report c m t trong nhng phn trc, ta khng lit k li m ch a ra chc nng ca cc lnh mi. Report Project Hierachy : Lit k th t phn cp cc ti liu Schematic ca Project, trng trng hp Project gm nhiu thit k Schematic. Nestlist Status : Lit k trng thi cc Net c trong thit k. Kt qu xut ra File .REP.

Trong ti liu, ta i ln cp n thit k a knh, by gi ta s trnh by k v thit k ny : Thit k Multi-Channel : Thit k Multi-Channel y l s dng cng mt knh nhiu ln. Ta ch cn thit k knh 1 ln, nh l mt Sub-Sheet Schematic, v s dng n trong bn v thit k Multi-Channel. Ta phi ch r s dng n bao nhiu ln trong thit k chnh. thit k Multi-Channel cn thc hin cc cng vic sau : 1. Thit k mt mch ( bn v Schematic) m ta mun dng nh s cu trc mt knh, sau thm n vo Project, chng hn ti liu Schematic thit k knh ta t tn l In.SchDoc. Trn bn v Schematic chnh, t biu tng PlaceSheet Symbol, tng trng cho knh. Tn ca knh l du hiu nhn dng duy nht xc nh cc thit b trong mi knh.

In.SchDoc

2. Double Click ln biu tng Sheet Symbol m ca s thuc tnh ca n. 3. Filename nh tn ti liu ma ta thit k knh trn , y l In.SchDoc 4. Desingnator ta nh lnh lp lai knh 3 ln bng cu lnh Repeat(Tn_knh, S khi u, S kt thc). Chng hn y ta nh Repeat(CIN,1,3) : to ra 3 knh vi tn CIN_1, CIN_2,CIN_3. 5. Bin dch Project bng cch chn ProjectCompile PCB Project. Ta s thy ti liu In.SchDoc by gi c 3 th, mi th l mt knh, ch khc nhau v tn, cn kin trc ging ht nhau.

gii quyt vn c nhiu u ra ca nhiu knh, ta thng gn n vo mt ng Bus( Trong trung hp cc u ra tng ng ca cc knh khng ni vi nhau). Nh vy, tt c cc ng ra tng ng ca cc knh s c gn vo Bus t trc. Ta cng cn phi t Sheet Entry trong cu lnh Repeat(ra1) Cn cng ra2 ca c 3 knh c ni chung vi nhau, do ch cn v n thun ni vo mt ng dn. n y ta hon tt cng vic thit k mt Project Multi-Channel. 6. Chuyn nhng thit k va to ra ln mch in bng cch chn DesignUpdate PCB Project.PCB, 3 knh va thit k s c chuyn ln mch in. Trn mch in lc ny xut hin 3 knh m ta thit k . 7. La chn 1 Room bt k, Routing cho n bng cch chn AutoRouteRoom. Sau d Copy m hnh ny ra tt c cc Room khc bng cch chn DesignRoomCopy Room Format quan st, qun l thit k Multi-Channel, ta c th chn ProjectView Channel bt ca s Project Component :

Trong ca s ny, ta c th quan st cc thit b trong mch chnh v cc thit b ca knh. Giai on cui cng ca vic thit k l to cc File dng cho vic sn xut. Tp cc File cn cho cng vic ny l GerBer File, NC Drill File, Pick and Place File, danh sch cc thit b v Testpoint File. Tp cc File ny c cha trong th mc m ta quy nh trong ProjectOutput File hoc trong File Fabrication Outputs. Gerber files:Mi GerBer file tng ng vi mt Layer trn mch in thc t : component overlay, top signal layer, bottom signal layer, the solder masking layer.... Nn tham kho kin nh sn xut trc khi to ra cc File ny ph hp kh nng sn xut ca h.

To GerBer File : File Fabrication Outputs Gerber files Sau cu lnh ny, hp thoi Gerber Setup xut hin, cho php ta thit t cc tham s, la chn cho GerBer File. Nhn OK, GerBer File c to, Protel Chuyn sang mi trng CAMtastic.