huong dan nios 2-

7/30/2019 huong dan nios 2-

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Xy dng h thng Nios II trn kit FPGA Leopard I

Titans Technology | www.titans.com.vn / www.hlab.com.vn HFAR01

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Copyright 2012, Titans Technology

CPU Nios II theo mc ch thit k. Ngoi ra, ngi thit k c th m rng kh nngca CPU bng cch thm cc tnh nng nh qun l b nh MMU hoc cc lnh ty bin

(custom instruction)

Hnh 1: Nios II 32-bit CPU

Theo nghin cu ca Gartner Research , Altera's Nios II l vi x l soft-core ph binnht trong ngnh cng nghip FPGA. Nios II bao gm y cc tnh nng ca cc li vix l hin i nh :

Qun l b nh MMU n v bo v b nh (Memory protection unit MPU ) H thng vector ngt vi cc b iu khin ngt c lp ln ti 32 trn mt b iu khin H thng instruction v data caches ring bit (c th cu hnh t 512 bytes ti 64 KB) Kh nng nh a ch ln ti 2 GB. C th them tightly-coupled memory cho instructions v data tng hiu sut Kin trc 6 tng pipeline t hiu sut MIPS cao (*Dhrystones 2.1 benchmark) trn MHz B nhn v dch phn cng thc thi trong 1 chu k. C th ty chn b chia hardware C kh nng tin on cc lnh r nhnh ng

C th thm ti 256 lnh ty bin v khng gii hn cc b tng tc hardware Module JTAG debug c th ty bin Cc tnh nng JTAG debug nng cao, nh hardware breakpoints, data triggers, v real-

time trace c th ty chn.


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CPU Nios II c ba cu hnh chnh : Nios II /e core , Nios II /s core , Nios II /f core phntheo hiu sut v chi ph , v c th la chn ph hp cho tng ng dng ring.

Application

Nios IIProcessor

Core Vendor Description

Power and costsensitive

Nios IIeconomy

core

Altera With as low as 600 logic elements, the Nios IIeconomy processor core is ideal formicrocontroller applications. The Nios IIeconomy processor core, software tools, anddevice drivers are offered free of charge.

Real time Nios II

standard andfast core

Altera Absolutely deterministic, jitter free real-time

performance with unique hardware real-timefeatures

Vector Interrupt Controller Tightly Coupled Memory Custom instructions (ability to use

FPGA hardware to accelerate afunction)

Supported by industry-leading Real-Time Operating Systems (RTOS)

Nios II processor is the ideal real-timeprocessor to use with DSP Builder-based hardware accelerators to providedeterministic, high performance real-time results

Applications processing Nios II fastcore

Altera With a simple configuration option, the Nios IIfast processor core can use a memorymanagement unit (MMU) to run embeddedLinux. Both open source and commerciallysupported versions of Linux for Nios IIprocessors are available.


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2. Kit FPGA Leopard I ca Titans Technology:

Kit FPGA Leopard I do Titans Technology (www.titans.com.vn ) sn xut theo thit kca phng th nghim H-laboratory (www.hlab.com.vn) . Kit Leopard thit k da trnFPGA Altera Cyclone III vi kin trc multi-core bao gm chip FPGA giao tip vi chipMCU ARM Cortex M3 ca ST Microelectronics. Board c thit k nhm ti ccthit k v iu khin cn cc b tng tc hardware, hoc cc i tng mi tm hiu vFPGA c th thit k giao tip vi cc ngoi vi c bn nh led, nt nhn, lcd charactor,sd card, uart Ngoi ra, board cng ph hp vi nhng ai pht trin cc li IP cn giaotip vi MCU test nh thit k core I2C, UART, SPI, hay cc giao tip tc caokhc.

Hnh 2:Kit FPGA Leopard Ica Titans technology

FPGA Leopard I Development Kit

Cyclone III EP3C16Q240 ARM Cortex M3 STM32F103RCT 8x User Buttons, 8x general purpose leds USB 2.0 Interface LCD 16x2 charactor. 4x Led 7-Segments 2x RS232 with DB9 Connector MMC/SD Card socket 32KB SRAM 4Mbits EEPROM AS and JTAG configuration support.


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3 Oscilators : 50Mhz, 27Mhz, external SMA 40-Pins Expansion Connector.

Cyclone III EP3C16Q240o 15.400 LEs.o 56 M9K Memory Blocks.o 516.096 On-chip Memory bits.o 56 18x18 Multipliers.o 4xPLL.o Maximum 160 IOs.

STM32F103RCTo ARM 32-bit Cortex-M3 CPUo 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1)o 512 Kbytes of Flash memoryo 64 Kbytes of SRAMo 3 12-bit, 1 s A/D converters (up to 21 channels)o 2 12-bit D/A converterso DMA: 12-channel DMA controllero Debug Serial wire debug (SWD) & JTAG interfaceso Up to 11 timerso Up to 2 I2C interfaces (SMBus/PMBus)o Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)o

Up to 3 SPIs (18 Mbit/s), 2 with I2

S interface multiplexedo USB 2.0 full speed interfaceo CRC calculation unit, 96-bit unique ID

bit thm chi tit , chc nng v hng dn s dng kitFPGA Leopard I, vui lngtham kho ti y:http://titans.com.vn/index.php?page=shop.product_details&product_id=70&option=com_virtuemart .


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III. Design Example :

1. H thng Nios II n gin:Trong ti liu ny, chng ta s thc hin mt h thng Nios II nh cho ng dng iu

khin, Nios II s thc hin m v xut ra led, Nios II cng c th giao tip vi nt nhnv giao tip my tnh thng qua JTAG UART.

V d v h thng Nios II bao gm nhng thnh phn sau : Vi x l Nios II /s core (standard) Memory on chip Timer JTAG UART 8-bit parallel I/O (PIO) iu khin LEDs System identification componentHnh 3 m t h thng v mi quan h gia my tnh, board ,FPGA v h thng Nios

II.

Hnh 3: H thng Nios II n gin


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Yu cu v phn cng v phn mm:Trong bi ny, chng ta cn cc thnh phn sau.

o Kin thc v Altera Quartus v to project trn phn mm Quartus II (xem tiliu HFAR02 bit cch to project)

o Altera Quartus II software version 9.0 hoc cao hn.o Nios II EDS version 9.0 hoc cao hno Kit FPGA Leopard I(xem ti y )o Cp USB Blaster(xem ti y )o Kt ni Kit Leopard vi PC nh hnh 4

Hnh 4: H thng Nios II trn kit Leopard I

2. To Altera Quartus Project s dng block diagram:Trc tin, ta phi to project trn Quartus trc, tham kho ti liu HFAR02 bit

cch to mt project trn Quartus Altera .

Sau , ta to mt file mi block diagram cho ton b h thng. t tn file lnios2_9_0.bdf

Hnh 5: To file .bdf cho h thng


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Sau ta thm cc chn input/output cho h thng bng symbol tool :

Hnh 6: To chn in/out cho h thng

To cc chn :CLK (input),VCC (power) , BUTTON[7..0] (input), LED[7..0] (output)

Hnh 7: Giao din thit k ca file Nios2_9_0.bdf

Tip theo, ta s phi to h thng Nios II s dng SoPC Builder:

3. To h thng Nios II s dng Altera SoPC Builder:

Click vo biu tng SOPC Builder to h thng Nios II.


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Hnh 8: SOPC Builder

Hnh 9: Giao din SOPC Builder

Trc tin ta to b nh memory onchip trc.Trong h thng no th CPU cng cn phi c b nh cho d liu v lnh. Trong thit k v

d ny, ta s 20 KB on-chip memory cho c data v instructions. thm memory vo hthng, thc hin cc bc sau:

o Trn tab Component Library (bn tay tri ca tab System Contents), trong


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Memories and Memory Controllers, mOn-Chip, v click vo On-ChipMemory (RAM or ROM).

o ClickAdd. Bng cu hnh thng s xut hin nh hnh 10.o Trong danh sch Block type, chn Auto.o Trong hp thoi Total memory size, nh vo 20480 c 20 KB.o ng thay i cc thng s mc nh no ht .

Hnh 10: Giao din cu hnh tham s on-chip memory

o Click Finish, quay tr li SoPC Builder Tool.


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o Click chut phi vo on-chip memory mi to, i tn thnh onchip_mem . Tip theo ta to CPU Nios II

Trong phn ny, ta s them CPU Nios II/s core v cu hnh cho n s dng b nhcache lnh 2 KB on-chip.

Thc hin cc bc sau thm Nios II/s core vo h thng:o Trong tab Component Library, mProcessors, v click voNios II Processor.o ClickAdd. Xut hin hp thoi cu hnh thng s cho Nios II nh hnh 11.o Di phnSelect a Nios II core, chnNios II/s.o Trong danh schHardware multiplication type, chnEmbedded Multipliers.o Tt mcHardware divide.o Trong phnReset Vectorchn onchip_memo Trong phnException Vectorchn onchip_memo

Trong tab Caches and Memory Intefaces chnInstruction Cache 2 Kbyteso Cc mc khc mc nho ClickFinish. Quay tr li tabSOPC System Contents, v mt con CPU Nios II

xut hin trong bng system contents.

Hnh 11: Giao din cu hnh tham s CPU Nios II /s Core


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o Trong phn connection, m bo kt ni gia Nios II instruction_master ,data_master , jtag_debug_module kt ni ti port s1 ca onchip_mem .

o Click chut phi vo CPU mi to, i tn thnh cpu .

Thm JTAG UARTModule JTAG UART cho php ta giao tip d liu gia vi x l Nios II processor

vi my tnh thng qua cp USB-Blaster. Thc hin cc bc sau thm moduleJTAG UART:

o Trong tab Component Library, M phnInterface Protocols, chnSerial, vclick chnJTAG UART.

o ClickAdd. Bng cu hnh thng s cho JTAG UART xut hin nh hnh 12.o ng thay i bt c thng s mc nh no.

Hnh 12: Giao din cu hnh tham s JTAG UART

o ClickFinish. Quay tr liSOPC System Contents tab , thnh phn JTAG UART xut hin trong bngsystem contents

o Click chut phi vo module JTAG UART, i tn thnh jtag_uart.


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o m bo c kt ni gia Nios IIdata_masterport viAvalon_jtag_slave caJTAG UART

Thm b Interval Timer.Hu ht cc h thng iu khin u s dng thnh phn timer tnh ton thi gian

chnh xc. c nhp clock h thng theo chu k, Nios II HAL cn mt timer. Thchin cc bc sau them timer vo h thng :

o Trong tab Component Library, mPeripherals, chn MicrocontrollerPeripherals, v click chn Interval Timer.

o ClickAdd. Bng cu hnh thng s cho Interval Timer xut hin nh hnh 13o Trong danh sch Presets, chn Full-featured.o ng thay i bt c thng s mc nh no.

Hnh 13: Giao din cu hnh tham s Interval Timer


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o ClickFinish. Quay tr liSOPC System Contents tab , thnh phn IntervalTimer xut hin trong bngsystem contents

o Click chut phi vo module Interval Timer, i tn thnh sys_clk_timer.o m bo c kt ni gia Nios IIdata_masterport viport s1 ca sys_clk_timer

Thm System ID PeripheralModule system ID peripheral cho php m bo h thng c bin dch ti nhng

thi im khc nhau s c s ID khc nhau m bo phn mm s c downloadxung ng h thng mong mun. Thc hin cc bc sau them system IDPeripheral vo h thng :

o Trong tab Component Library, mPeripherals, chn Debug andPerformance, v click chn System ID Peripheral.

oClickAdd. Bng cu hnh thng s cho System ID Peripheral s xut hin nhhnh 14.

o ng thay i bt c thng s mc nh no.

Hnh 14: Giao din cu hnh tham s System ID Peripheral

o ClickFinish. Quay tr liSOPC System Contents tab , thnh phn System IDPeripheral xut hin trong bngsystem contents

o Click chut phi vo module System ID Peripheral, i tn thnh sysid.o m bo c kt ni gia Nios IIdata_masterport viport control_slave ca

sysid

Thm PIOThnh phn PIO l cch d nht Nios II c th nhn tn hiu t bn ngoi, hoc

iu khin mt tn hiu output. Cc ng dng iu khin phc tp c th cn hngtrm tn hiu PIO, trong v d ny, ta ch cn 8 tn hiu PIO iu khin 8 n ledtrn board. Thc hin cc bc sau them thnh phn PIO.

o Trong tab Component Library, mPeripherals, chnMicrocontrollerPeripherals, v click chnPIO (Parallel I/O).


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o ClickAdd. Bng cu hnh thng s cho PIO (Parallel I/O) xut hin nh hnh15

o ng thay i bt c thng s mc nh no.

Hnh 15: Giao din cu hnh tham s PIO

o ClickFinish. Quay tr liSOPC System Contents tab , thnh phn PIO xut hin trong bngsystem contents

o Click chut phi vo module PIO, i tn thnh led_pio.o

m bo c kt ni gia Nios IIdata_masterport viport s1 ca led_pio Gn khng gian a ch v a ch ngt

Ti thi im ny, chng ta c tt c cc thnh phn cn thit to thnh mth thng hon chnh. By gi, ta phi ch nh cch m cc thnh phn giao tip vinhau. Ta s phi gn a ch base address cho mi thnh phn slave trong khnggian ca nios master , v gn mc u tin ngt (IRQ) cho JTAG UART v intervaltimer. Ch s ngt cng nh th mc u tin cng ln. Thc hin cc bc sau gn khng gian a ch v u tin ca ngt.

o Trong tab system , chnAuto-Assign base addresses


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o Trong tab system contents , IRQ bn tay phi, nhp IRQ cho interval timer l 1,cn jtag_uart l 16. V timer cn u tin cao hn duy tr hot ng ca tonh thng.

Hnh 16 m t h thng Nios II hon chnh trong v d ny

Hnh 16: H thng Nios II hon chnh

To h thng (System Generation)Chng ta sn sang to h thng SOPC. Thc hin cc bc sau :

o Click vo tab SystemGeneration.o Chn None cho Create simulation model.o ClickGenerate. Click Save v ch h thng hon tt nh hnh 17. Nu h thng

yu cu t tn th nh nios2_sys


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Hnh 17: Giao din hon tt

o ClickExit. Quay tr li giao din thit k ca quartus4. Tch hp h thng SoPC Builder vo project Quartus II:

Trong phn ny, chng ta s phi thc hin cc bc sau hon thnh thit khardware.

o Tch hp SoPC system vo project quartus IIo Chn chip FPGA v gn chno Compile projecto V test trn kit Leopard I

Tch hp SoPC system vo project tch hp h thng SOPC vo h thng quartus .bdf, thc hin cc bc sau:

o Chn hp thoiSymboltrn thanh cng c.o Di mcLibraries, mProject.o Chn nios2_sys. Hp thoiSymbols hin th symbol nios2_sys nh hnh 18.


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Hnh 18: Symbol nios2_sys

o ClickOK. Quay tr l.bdfschematic. Symbol nios2_sys s nm trong khng gianthit k ca quartus.

o Ni cc chn to t trc vi cc chn ca Nios_sys. a chut ti gn chn ni dy t chn .

o Lu li file.bdf hon chnh, clickSave trn menu File.Figure 19 cho ta thy h thng .bdfschematic hon chnh vi cc chn iu khin led.

Hnh 19: H thng hon chnh

Trong ca s qun l project, ta thy cc file nh hnh 20 :


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Hnh 20: Project Navigator

Chn chip FPGA v gn chnTrong phn ny, chng ta s phi chn thit b FPGA ph hp vi board Leopardv gn chn cho ph hp vi board Leopard. gn thit b FPGA, thc hin cc bc sau :

o Trn menu Assignments, clickDevice. Hp thoiDevice xut hin.o Trong danh sch Family list, chn dng Cyclone III.o Torng mc Target device, chnSpecific device selected in 'Available devices'

list.o Trong mcAvailable devices, chn EP3C16Q240C8.o Chn OK.

Figure 21 m t hp thoi Device .


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Hnh 21: Hp thoi Device Setting

gn chn FPGA, Thc hin cc bc sau:o Trong menu Processing, VoStart, v click chnStart Analysis & Elaboration chun b cho vic gn chn. Qu trnh ny c th mt vi pht v kt thc khic hp thoi xc nhn xut hin.

o ClickOK.o Trn menu Assignments, clickPin Planner. Bng Quartus II Pin Planner xut

hin.o Trong ctNode Name, gn chn theo hnh 22.


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Hnh 22: Hp thoi Pin Planner

o ClickOK.o Trn menu Assignments, clickDevice. Bng hi thoiDevice xut hin.o ClickDevice and Pin Options, Bng hi thoiDevice and Pin Options xut hin.o Click vo trangUnused Pins .o Trong danh sch Reserve all unused pins , chnAs input tri-stated with weak

pull-up . Vi la chn ny, tt c cc chn khng dng trn thit b FPGA s ctrng thi tng tr cao. Ch , lun lun dng option ny trnh lm h ccchn IO v linh kin trn board do cc chn khng dng c mc in p xung t

o ClickOK ng cc hp thoi. Bin dch h thng v kim tra timing

Chng ta phi bin dch h thng to ra file .sofm c th download xungboard. Sau khi bin dch xong, chng ta phi kim tra timing ca thit k c lm vicdi iu khin ca phn cng hay khng. m bo thit k t yu cu v timing,thc hin cc bc sau :

o Trn menu File, clickNew.o Trong danh sch file, ChnSynopsys Design Constraints File (*.sdc).o t tn l hw_leopard.sdc v clickOK.M file trong chng trnh Editoro Thm dng lnh create_clock : create_clock -name sopc_clk -period 20

[get_ports CLK].


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o Click Saveo Trong menu Assignments , chnSettings .o

Trong mc Timing Analyzer Setting,chn TimeQuest Timing Analyzero Browse file hw_leopard.sdc v nhn add thm vo danh sch.o Bt mcEnable multicorner timing analysis during compilation nh hnh 23

Hnh 23: TimeQuest Timing Analyzer

o Click OK v bt u bin dch.o Sau khi bin dch xong s hin ra bng thng bo nh hnh 24


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Hnh 24: Compilation Report

o M mc TimeQuest Timing Analyzer trong compilation Reporto ClickMulticorner Timing Analysis Summaryo Kim tra gi tr Worst-case Slack phi dng i vi Setup, Hold , Recovery v

Removal. Ch ,ch kim tra cho clocksopc_clkm thi. Nu c bt c gi tr

no m th h thng s khng th hot ng trn phn cng c. Trong trnghp ny, gim tn s dao ng xung t c timing theo yu cu.

Chng ta hon tt thit k v sn sang np chng trnh cung board Leopard th nghim.

Download v test trn kit Leopard ITrong phn ny, chng ta s download file .sofxung board Leopard. Thc hin cc

bc sau:o Kt ni board Leopard vi my tnh host bng cp USB-Blaster, Sau cm

ngun vo board.o Trn menu Tools ca phn mm Quartus II, clickProgrammer. Cng c Quartus

II Programmerxut hin vi file cu hnh mc nh (nios2_9_0.sof) nhHnh25.


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Hnh 25: Quartus II Programming

o Nu cha c cp USB-Blaster xut hin, kim tra cp v click voHardwareSetup kim tra cp download. Nu vn khng c, kim tra driver ci haycha

o ClickCloseo Trong hng nios2_9_0 , check voProgram/Configure.o ClickStart .Khi thanhProgess t 100% ngha l h thng Nios II c cu

hnh v hot ng trn FPGA Leopard. Tuy nhin, n vn cha c chng trnhg thc thi c.

5.Pht trin software s dng Nios II IDE Eclipse :

Trong phn ny,chng ta s lm quen vi chng trnh Nios II SBT for Eclipse vbin dch mt chng trnh C n gin. Phn ny ch nu ra cc bc c bn nht

pht trin software da trn phn cng h thng to phn trc.Trong phn ny, chng ta s thc hin cc bc sau :

o To mtNios II C/C++ application and BSP projects mio Bin dch project.

thc hin phn ny, chng ta phi c file .ptf c to ra phn trc.

To mt project Nios II Application and BSP mi t Template c snTrong phn ny, chng ta s to mt project Nios II C/C++ application and BSP

mi . Thc hin theo cc bc sau :

o Khi ng chng trnh Nios II 9.0 IDE.o Nu hp thoi Workspace Launcher xut hin, click OK chn v tr workspace

mc nh.o Trn menu File, chnNew, Click voNios II C/C++ Application. Ca s wizard

cho Nios II C/C++ Application xut hin nh hnh 26.


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Hnh 26: Nios II New C/C++ Application project

o Di mcSelect Target Hardware , tiSOPC Builder System PTF Files ,browse ti th mc hin ti, chn file nios2_sys.ptfv clickOpen .

o Trong Name, nh vo chcount_binary.o Trong mcSelect Project Template , chn Count Binary.o ClickNext.o Check vo mc Create a New system library named: count_binary_syslibo ClickFinish

By gi Nios II IDE to v hin th project mi trong ca s Project Explorer , thngnm bn tay tri nh hnh 27


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Hnh 26: Giao din Nios II IDE

Bin dch projectTrong phn ny, chng ta s bin dch project to ra mt file thc thi. V trong

v d ny ta ch c mt h thng nios nh, do ta s phi iu chnh mt s setting gim thiu kch thc th vin, bi v h thng Nios II hardware ch c 20 KB bnh m thi. Thc hin theo cc bc sau :

o Trong ca s Project Explorer, click phi vo count_binary_syslib v clickProperties. Ca sProperties for count_binary_syslibxut hin.

o Click voSystem Library. iu chnh cc mc sau : Check vo mcReduced device drivers. Tt mcSupport C++. Check vo mcSmall C library. Tt mcModelSim only, no hardware support.

o ClickOK.o Trong ca sProject Explorer, clickBuild Projecto Sauk hi build hon tt, mt thng tin s xut hin trn ca s Console.

Chy ng dng Nios II trn Kit Leopard ITrong phn ny, chng ta s download chng trnh xung kit hardware v thc thi n. download file thc thi, thc hin cc bc sau :

o Click phi vo projectcount_binary , chnRun As , click voNios IIHardware. Nios II IDE s download code thc thi vo board Leopard vchng trnh bt u chy.


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o Nu hp thoi Run Configuration xut hin, th chng ta phi kim tra li tnProject Name , File ELF ,v File .sof c np xung Kit Leopard cha,

sau Click Run.o Khi board Leopard chy, Mn hnh Console ca Nios II trn my PC s hin

th cc k t m nh hnh 27, v led trn board leopard s m theo s nhphn sau mi giy.

o Click vo iocn Terminate (hnh vung mu ) dng CPU Nios II li numun CPU ng li.

Hnh 27: Output t hardware ln mn hnh Console ca Nios II IDE

Chng ta c th sa li file chng trnh count_binary.c trong giao din pht trinNios II IDE v lp li cc bc trn thay i chng trnh theo yu cu thit kca mi ngi.Nh vy l chng ta hon tt cc bc pht trin mt h thng Nios II trn Kit

Leopard I, v chng ta c th pht trin cc ng dng phc tp hn, giao tip vicc ngoi vi bn ngoi phc tp hn trong cc ti liu hng dn sau.


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IV.Hnh nh Demo trn Kit Leopard I:

V d thit k c thc thi trn Kit Leopard ,v Nios II ang iu khin cc ledm theo m nh phn, ng thi xut gi tr m ln PC thng qua cp USB-Blaster

Hnh 28: Led trn Kit Leopard ang m theo s nh phn


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Table of ContentsApplication Report.................................................................................................... 0

Xy dng mt h thng da trn Nios II trn Kit FPGA Leopard I .......................................... 0

I. Gii thiu:.................................................................................................................................................... 0

II. Nios II 32-bit CPU v Kit FPGA Leopard I :............................................................................................ 0

1. Nios II 32-bit soft CPU: ............................................................................................................................ 0

2. Kit FPGA Leopard I ca Titans Technology: ........................................................................................... 3

III.

Design Example :.................................................................................................................................... 5

1. H thng Nios II n gin: ...................................................................................................................... 5

2. To Altera Quartus Project s dng block diagram: ............................................................................ 6

3. To h thng Nios II s dng Altera SoPC Builder: ............................................................................... 7

4. Tch hp h thng SoPC Builder vo project Quartus II: .................................................................... 16

5. Pht trin software s dng Nios II IDE Eclipse : ................................................................................ 23

IV. Hnh nh Demo trn Kit Leopard I: ...................................................................................................... 27

Reference ....................................................................................................................................................... 29

Document Revision History.............................................................................................................................. 29


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Reference

tt_nios2_hardware_tutorial Wikipedia.com Websites from Internet http://www.altera.com

Document Revision History HFAR01 Rev 1.0 ( 12/2012 )

Phin bn u tin

Copyright 2009 Titans Technology. Ti liu ny thucbn quyn ca Titans Technology (www.titans.com.vn),chng ti hy vng cc bn khi s dng vi bt k mc ch

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Hy truy xut trang web ca chng ti thng xuyn c nhng cp nht mi nhtv cc thit b mi nht ti website www.titans.com.vn.

Nu c bt c kin ng gp cng nh cn h tr, t vn thm thng tin v snphm, vui lng gi mail n a ch email:[email protected]

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