HomeBay2.0 ASIC preliminary 20070604 R0.1.ppt [호환 모드] · PDF fileto 10,000 feet with...

ASIC Version 1.0ASIC Version 1.0

Feature

General Description :

The eDSL1000 solution delivers cost-effective, high-performance broadband access to multiunit buildings (Residential multi-dwelling units [MDU], multi-tenant unit [MTU],Hospitality).

The HomeBayTM 2.0’s ATCM (Advanced Time Compressed Multiplexing) Technology dramatically extends Ethernet over existing phone line at speed 8M bps and distances up t 10 000 f t ith R t d t ti

PreliminaryPreliminary

Heart ofth P i t

Ethernet I/F with MII & RMIIEthernet PHYI/F with MIIEth t MAC I/F (S it hi IC) ith RMII

to 10,000 feet with Rate adaptation

The HomeBayTM 2.0 use MII and RMII for Interfacing with Ethernet MAC and Phy.

OverviewIncludes on-chip PreAmp, PGA, ADC/DAC

the PrivateNetwork System

Feature

Ethernet MAC I/F (Switching IC) with RMII

Store & Forward MethodStore & Forward Buffer Management SchemeInternal 32K Byte SRAM Tx/Rx BufferAuto-sensing Tx/Rx Buffer Management

Proprietary Time Slot AssignmentCRC Check in each Time Slot

Includes on chip PreAmp, PGA, ADC/DACSupports External Tx Driver & AGC2B1Q Line Coding ISI & Ghost reduction with Decision Feedback EqualizerData Recovery using Internal Digital PLLAutomatic/Manual Rate Adaptive Ethernet I/F with MII & RMIIStore & Forward MethodP i t Ti Sl t A i t Frame Sync. Recovery in each Time Slot

Time Slot Assignment depends on Data Rate

Dynamic Bandwidth AllocationDynamic Bandwidth Allocation in RealtimeIncrease Data Transfer Rate using Dynamic Bandwidth AllocationBandwidth Restriction Mode (4 Classes)

Proprietary Time Slot AssignmentDynamic Bandwidth AllocationEmbedded SRAM BufferSuperior Manageability with MDIO functionSupports Netbios/NetBEUI Security functionOperating Voltage : Digital:3.3 V ,Analog: 5VOperating Frequency : 65.536 MHzPackage Type : 128-pin LQFP

Embedded SRAM Buffer32K Byte SRAM

Easy of use and easy of developmentOnly Ethernet PHY/MAC I/FOffer Reference Board

Superior Manageability

Supports On-chip PreAmp , PGA, ADC/ DAC32 Steps PGA(Programmable Gain Amplifier).8bit-32Msps ADC/ 8bit-54Msps DAC.External Tx Line Drivers are needed.

2B1Q Line Coding Method2B1Q Line Coding with Scramble/DescrambleISI & Ghost reduction using DFE(Decision Feedback Equalizer) Architecture HomeBayTM 2.0 Internal States Report using

MDIO

SecuritySupports NetBios/NetBEUI Security function

Operating Voltage : Digital : 3.3 volt, Analog : 5 voltOperating Frequency : 65.536 MHzPackage Type: 128-pin LQFP (ROHS)

Feedback Equalizer) Architecture.

Data Recovery using Internal Digital PLLOne-Chip Timing Recovery, no external devices are not needed.Data Recovery Circuit to reduce the clock slip

Automatic/Manual Rate Adaptive8M/0.8Km, 4M/1.3Km, 2M/1.8Km,1M/2.3Km

nSYS Technologies Co., LTD/Communication & Network Lab. 2007-06-12-1-

Package Type: 128 pin LQFP (ROHS)(Cable 0.5mm)


Service Concept

Internet

DSU/CSU

.

.

.

.

eDSL1000 SUPC

Telephone LineTelephone

8M b / 0 8K

Router...... eDSL1000 SU

PC

Telephone LineTelephone

.

.

Switching Hub

Can be

Integrate

8M bps / 0.8Km(Voice + Data)

Center Unit : MDF Subscribe Unit : APT/Building/Office

pPSTN

eDSL1000 CU

ed

Fig1. Service Concept using HomeBay2

OverviewInternet Gateway for MDU and MTUThe HomeBay 2.0 delivers Broadband Service on the Same Lines as POTS, Digital Telephone and ISDN Traffic

FeatureData Re-Transmission using CRCDynamic Bandwidth Allocation in Tx/Rx Time SlotInternal States Report in SNMP (Simple Network Management Protocol) for Remote Network and ISDN Traffic

Extremely Low Setup and Maintenance Cost Compare with ADSL, SDSL, VDSL and Cable ModemHomeBay2 CU System service multi users in MDF (Main Distribution Facility)Can be configured the Integrated Ethernet Switching Hub or notHomeBay2 SU System can be configured in th S b ib ’ Sid ith th LAN C d

g )ManagementProprietary ATCM (Advanced Time Compressed Multiplexing) Technology is the Best Protocol in 2-wired Phone Line EnvironmentThe Minimum interference to/from Voice SignalProprietary Layer2 Protocol for Error-free Data ServiceMid and Long Distance Data Transfer Using nSYS Tech’s Patent Approved Line Coding Method


the Subscriber’s Side with the LAN CardHigh Data Rate Service : 8M bpsLong Distance Service Area : 2.3Km(0.5mm)

Tech s Patent Approved Line Coding Method


System Block Diagram

EthernetPHY

CPUwith

Ethernet MAC RAMSwitch

AddressBus

DataBus

SystemROM

AFEHomeBay Multi-port

SwitchEngine

Voice + Data

68EN360, PPC850,or NetARM

ManagementPort (RS232C )

SystemRAM

AFE(X 8)

HomeBay Multi portController

(X 8)

PSTNX 8

Voice + DataX 8

Fig2. Central Unit System Block Diagram using HomeBay2

AFEHomeBay Single-port

Controller AFEController(X 1)

Data + VoiceEthernet PHY

Fig3. Subscriber Unit System Block Diagram using HomeBay2

DescriptionsCU/SU Block Diagram using HomeBay2 in Fig2, Fig3Ethernet MAC (Switching IC) I/F with RMIIEthernet PHY I/F with MIISU Configure :-. Ethernet PHY + HomeBay2 + AFE (Analog

SNMP can be configured with u-Processor and Switching IC when HomeBay2 has Internal States Register using MDIOHomeBay2’s AFE Application Note will show the Typical Application in 2-wired Telephone Line Environment


Front End)CU Configure :-. u-Processor + Ethernet MAC (Switching IC) +

HomeBay2 + AFE


HomeBay2 Block Diagram

Ethernet10BaseT

PC orSwitching Hub

EthernetPHY

EthernetInterfaceController

MDIOController

SRAM

SNMP

Link/PhyController

PLLEncoder

/Decoder

PGA DAC

ADC

PreAMP

AFEPhone

Voice + Data

Fig4. HomeBay2 Internal Block Diagram

Descriptions

Fig 4 is the HomeBay2’s Internal Block DiagramFig.4 is the HomeBay2 s Internal Block DiagramEthernet Interface Controller Block’s Functional Object is Ethernet MAC/PHY Interface with MII or RMII and Ethernet Data is transferred in Memory Control BlockLink/Phy Controller Block’s Functional Object is the Overall FSM Control (Initial Pattern, Tx Pulse Gen and Rx Gain Control) with Memory Control Block


Encoder/Decoder Block’s Functional Object is the Clock Recovery, AFE I/F, Digital PLL and so on


Pin DescriptionsA

_VSS

GA

_VD

DG

A_I

OB

A_A

VD

DB

A_A

VSS

BA

_RES

TA

_CO

MP

A_I

OR

A_A

VD

DR

A_A

VSS

RA

_VR

EFO

UT

A_A

VSS

A_V

REF

INA

_AV

DD

A_V

DD

A_V

SSX

_BIA

S25

VO

NX

_RV

SSG

X_R

VD

DG

INEP

CM

INEN

X_R

AV

DD

X_R

AV

SSV

OP

12345

MRSTZEPHY_SEL

EPHY_LINKVCC1GND1

RX_AVDD2INPINNOUTPOUTN

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

D D D D D D D D D D D D D D D D T X PV RX

RX

LI V L I RX

RX

PV

1021011009998

6789101112131415

nSYHom

TEST_MON0TEST_MON1TEST_MON2TEST_MON3TEST_MON4TEST_MON5TEST_MON6TEST_MON7

VCC2GND2

RX_AVSS2AD_VSSGAD_VDDGADC_BIAS06ADC_BIAS26AVINAVNAD_AVSSGAD_AVDDGAD AVSS

9796959493929190898815

161718192021222324

YS Tec

meB

ay 2.0

GND2TEST_MON8TEST_MON9

TEST_MON10TEST_MON11TEST_MON12TEST_MON13TEST_MON14TEST_MON15

VCC3

AD_AVSSAD_AVDDAD_VSSAD_VDDPLL_VDDPLL_VSSPLL_AVSSPLL_AVDD PLL_VSSGPLL VDDG

8887868584838281807924

252627282930313233

ch0

VCC3GND3

TST_MD0TST_MD1TST_MD2MONSEL0MONSEL1MONSEL2

VCC4GND4

PLL_VDDGGND9XCLKOXCLKIVCC9CLK_SELSIGDEL_OUTSHDNODIP_PLLSET1DIP_PLLSET0

79787776757473727170

3435363738

EEDOEEDI

EECKEECS

EPHY_RSTZ

GND8VCC8DIP_RATE1DIP_RATE0DIP_SY_ASY

C5

D5

OL RS

LK EN D3

D2

D1

D0

C6

D6

LK V D3

D2

D1

D0

C7

LK D7 IO NT

DC

EN

SL

39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

6968676665


VC

CG

ND

MII

_CO

MII

_CR

MII

_TX

CL

MII

_TX

EM

II_T

XD

MII

_TX

DM

II_T

XD

MII

_TX

DV

CC

GN

DM

II_R

XC

LM

II_R

XD

MII

_RX

DM

II_R

XD

MII

_RX

DM

II_R

XD

VC

CR

MII

_CL

GN

DM

DI

MIN MD

SCA

N_E

DIP

_MA

_S


Pin Descriptions (continued)

Signal Name Type Pin No Description

VCC[1..9] - 4,14,24,32,39,49,57 Supply voltage for Digital. DC 3.3V

1. Basic signals

VCC[1..9] 4,14,24,32,39,49,57,68,75

Supply voltage for Digital. DC 3.3V

GND[1..9] - 5,15,25,33,40,50,59,69,78

Low supply voltage for Digital

MRSTZ I 1 active low Main Reset

TST_MD[0..2] I 26,27,28 Chip Test Mode : Tie low for normal operation

SCAN_EN I 63 Chip Scan Test Enable : Tie low for normal operation

MON_SEL[0..2] I 29,30,31 Chip Monitoring Mode Select : Tie low for normal operation

TEST_MON[0:15] O 6,7,8,9,10,11,12,13,16,17,18,19,20,21,22 23

Chip Test Monitoring Output In normal operation TEST_MON[0..4] is used MDIO Phy ID the other pin should be open2,23 MDIO Phy ID, the other pin should be open

2. PLL interface signals

Signal Name Type Pin No Descriptiong yp p

XCLKI I 76 X-TAL,OSC InputX-TAL Clock : 7.3728MHzOSC : 80MHz

XCLKO O 77 X-TAL Output

CLK_SEL I 74 Clock Selection“1”: External OSC “0”:Internal X TAL1 : External OSC , 0 :Internal X-TAL

PLL_VSSG P 80 Digital Ground Guard ring

PLL_VDDG P 79 Digital Power Guard ring

PLL_VDD P 84 Digital Power Supply

PLL_VSS P 83 Digital Ground

PLL AVDD P 81 Analog Power Supply


PLL_AVDD P 81 Analog Power Supply

PLL_AVSS P 82 Analog Ground




DIP_MA_SL I 64 Master / Slave mode control signal.High for master mode. Low for slave mode.

3. Control/Status signals

DIP_SY_ASY I 65 Symmetric/Asymmetric mode control signal.High for Symmetric mode and Low for Asymmetric mode.

DIP_RATE[0..1] I 66,67 Data Rate Select “00” : 1“10” : 1/2“01” : 1/4“11” : 1/8

DIP_PLLSET [0..1] I 70,71 Symmetric Data Rate Select for RX“00” : x6.4“10” : x8.0“01” : x9.6“11” : x11 211 : x11.2[Valid in PLL Mode Only]

LED_LINK I/O 16 LED signal output. Active low when link success.Blink while link process is in progress.Share with TEST_MON5 Status Indicator

LED_RX I/O 17 Share with TEST_MON7 Status Indicator

LED TX I/O 18 Sh i h TEST MON6 S I diLED_TX I/O 18 Share with TEST_MON6 Status Indicator

4. EEPROM interface signals


EEDO I 34 EEPROM Data Input, 3.3V/5V tolerance PAD

EEDI O 35 EEPROM Data Output, 3.3V/5V tolerance PAD

EECK O 36 EEPROM Clock, 3.3V/5V tolerance PAD

EECS O 37 EEPROM Chip Select, 3.3V/5V tolerance PAD


EECS O 37 EEPROM Chip Select, 3.3V/5V tolerance PAD




EPHY_RSTZ O 38 Active low reset output signal for Ethernet PHY reset.

EPHY SEL I 2 Ethernet Phy Select “0”:MII “1”:RMII

5. Ethernet interface signals

EPHY_SEL I 2 Ethernet Phy Select 0 :MII, 1 :RMII

MII_COL I/O 41 Collision input signal from Ethernet PHY. (MII)

MII_CRS I/O 42 Carrier sense signal from Ethernet PHY. (MII)

MII_TXCLK I 43 Transmit clock input from Ethernet PHY. (MII)

MII_TXEN O 44 Transmit enable input from Ethernet PHY.

MII TXD[0 3] O 48,47,46,45 Transmit data output to Ethernet PHYMII_TXD[0..3] O 48,47,46,45 Transmit data output to Ethernet PHY. Only lower 2 bits is used in case RMII

MII_RXCLK I 51 Receiver clock input from Ethernet PHY. (MII)

MII_RXDV I 52 Receiver data valid output to Ethernet PHY.

MII_RXD[0..3] I 56,55,54,53 Receiver data input from Ethernet PHY. Only lower 2 bits is used in case RMII

RMII_CLK I 58 RMII Operation Clock : (50MHz) (RMII)

EPHY_LINK I 3 Ethernet Phy Link Status Signal for NMS (Active low)

※We Recommend to use LSI logic’s Ethernet PHY Chip in case MII Interface, and to use ALTIMA’sEthernet PHY Chip in case RMII Interface

6. SNMP interface signals


MDC I 62 Management Interface Clock : (Max 2.5MHz)

MDIO I/O 60 Management Interface Input/OutputIt is used as bi-dir serial link between PHY and STA. External Pull-up is required.

MINT O 61 Management Interface InterruptTri-state interrupt pin signal which is controlled by the Register ‘MDIO_USE_INT’

PHY_ID [0..4] I 6,7,8,9,10 MI Physical Device Address Input Id tif th MI PHY t i t ith STA


Identify the MI PHY to communicate with STAShared with TEST_MON[0:4][ Valid in TST_MD is low, MON_SEL is low]




TX_BIAS25 O 112 2.5V Reference Voltage for Tx AMP

7. DAC interface signals

DA_VSS P 113 Digital Ground

DA_VDD P 114 Digital Power Supply

DA_AVDD P 115 Analog Power Supply

DA_VREFIN I 116 Voltage Reference Input

DA_AVSS P 117 Analog Ground

DA_VREFOUT O 118 Voltage Reference Ouput

DA_AVSSR P 119 Analog Ground

DA_AVDDR P 120 Analog Power Supply

DA_IOR O 121 Positive Current Output

DA_COMP I/O 122 Compensation Pin

DA_RSET I/O 123 Full-scale adjust resistor

DA_AVSSB P 124 Analog Ground

DA_AVDDB P 125 Analog Power Supply

DA_IOB O 126 Negative Current Output

DA_VDDG P 127 Digital Power Guard ringg g

DA_VSSG P 128 Digital Ground Guard ring





AD_VDD P 85 Digital Power Supply

8. ADC interface signals

AD_VSS P 86 Digital Ground

AD_AVDD P 87 Analog Power Supply

AD_AVSS P 88 Analog Ground

AD_AVDDG P 89 Guard ring Power

AD_AVSSG P 90 Guard ring Ground

AVN I 91 Comparator Reference Voltage

AVIN I 92 Analog Input Signal

ADC_BIAS26 I 93 Top Level Reference Voltage (2.6V)

ADC_BIAS06 I 94 Bottom Level Reference Voltage (0.6V)

AD_VDDG P 95 Guard Ring Power

AD_VSSG P 96 Guard Ring Ground

SIGDEL_OUT O 73 Sigma Delta Output

SHDNO O 72 PGA ShutdownHigh Active





RX_AVSS2 P 97 PGA Core AMP Power Supply

9. PGA interface signals

RESERVED for FUTURE USE

OUTN O 98 AMP Negative OutputRESERVED for FUTURE USE

OUTP O 99 AMP Positive OutputRESERVED for FUTURE USE

INN I 100 AMP Negative Inputg pRESERVED for FUTURE USE

INP I 101 AMP Positive InputRESERVED for FUTURE USE

RX_AVDD2 P 102 RX Power Supply (5V)RESERVED for FUTURE USE

PVOP O 103 Positive Line OutputPVOP O 103 Positive Line OutputRESERVED for FUTURE USE

RX_RVDDG P 104 VDD Guard Ring PowerRESERVED for FUTURE USE

RX_RAVDD P 105 RX Power Supply(5V)RESERVED for FUTURE USE

LINEN I 106 N ti Li I tLINEN I 106 Negative Line InputRESERVED for FUTURE USE

VCM I 107 Preamp Common Mode VoltageRESERVED for FUTURE USE

LINEP I 108 Positive Line InputRESERVED for FUTURE USE

RX_RAVSS P 109 RX Power GroundRESERVED for FUTURE USE

RX_RVSSG P 110 GND Guard Ring PowerRESERVED for FUTURE USE

PVON O 111 PREAMP Negative Line OutputRESERVED for FUTURE USE



Functional Descriptions

1. Ethernet Controller

HomeBay2 has both rolls of MAC and PHY. As a MAC, HomeBay2 could be connected to Ethernet PHY andconnected to SWITCHING Controller as a PHY. To be connected to these, HomeBay2 support MII(MediaIndependent Interface) and RMII(Reduced Media Independent Interface). And HomeBay2 has 32KB SRAM todepe de e ce) d ( educed ed depe de e ce). d o e y s S oaccount for any difference between the Ethernet and HomeBay2 transmission speed.

1.1 The Role of Ethernet MAC by MIIHomeBay2 could support the Ethernet PHY by MII or RMII. In case of MII, CRS(Carrier Sense),

COL(Collision) pin should be input from Ethernet PHY.

1.1.1 TransmissionWhen a Frame is prepared, HomeBay2 send it immediately. At that time, first of all HomeBay2 should checkp p , y y , ythe Ethernet line if there is another activity. The signal which indicate this activity is CRS. When this signalis LOW, TxEN and TxD[3:0] is sent to Ethernet PHY synchronizing with TxCLK.

TxEN

TxCLK

400ns

CRS

TXD[3:0] PRE PRE PRE PRE PRE PRE SFD 1st 2nd 3rd 4th 5th 6th 7th 8th

180ns

Fig 1.1 MII Trasmission

1.1.2 ReceptionpWhile CRS is asserted HomeBay2 receive the ethernet data. And RxD is SFD(Start Frame Delimitter),HomeBay2 begin to packet the Ethernet nibble Data to store the SRAM with the byte data. But when there isa collision that packet is discarded. If SRAM is full during receiving operation, HomeBay2 generate theTxEN to keep Ethernet PHY from sending packets. To latch the RxD at the stable period, HomeBay2 latchthe RxD at the RxCLK rising edge.

400ns

RxDV

RXD[3:0]

RxCLK

PRE PRE SFD 1st 2nd

Data latch

PRE


(a) Start part


Functional Descriptions (Continued)

RxDV

RxCLK

n thn-1 thn-2 thn-3 thRXD[3:0]

(b) End part

Fig 1.2 MII Reception

1.2 The Role of MAC by RMIIRMII is similar to the MII, except:

- The data path is two bits wide instead of four.- The Main Clock must be 50MHz instead of 25MHz.- All timing for both transmit and receive is referenced to a single Main Clock(50MHz) instead of

TxCLK(2.5MHz) for transmission and RxCLK(2.5MHz) for Reception.- The MII RxDV and CRS inputs are combined into one signal that is outputted on the CRS pin.(Refer

to the RMII Spec ) So COL CRS pins are not used in RMII Modeto the RMII Spec.) So COL, CRS pins are not used in RMII Mode.- RxD[1:0] = 00 from start of CRS until valid data is ready to be output.

To support 10Mbps Mode, each data Di-Bit must be input on TxD[1:0] and output on RxD[1:0] for tenconsecutive Main Clock.(50MHz) All input and output data is triggered on rising edge of Main Clock.

Main Clock

20ns

TxD[1:0]

TxEN

Main Clock

PRE SFD 1st

Note1

Note 1 : Each Di-Bit is present on RxD[1:0] for 10 consecutive Main Clock.

Fig 1.3 RMII Transmission




1.3 The Roll of PHYHomeBay2 could support the Switching Controller by MII or RMII. In MII mode, CRS and COL signalsare generated from HomeBay2. So CRS, COL pins should be output. In RMII mode, it’s same to thecase that HomeBay2 operates as a MAC.

2. SNMP(MDIO)

2.1 OverviewHomeBay2 Chip has a Management I/F which is defined in IEEE802.3. It has single clock pin(MDC)which is driven by the STA(station) and has a bi directional data pin which sends & receives the datawhich is driven by the STA(station) and has a bi-directional data pin which sends & receives the databetween the PHY & the STA.Management Information is stored in the Management Register of HomBay. Management Register set iscompliant to the defintion of IEEE802.3.

2.2 PIN DescriptionMDC(Management Data Clock) is sourced by the Station Management entity to the PHY as the timingreference for transfer of information on the MDIO signal. MDC is an aperiodic signal that has no

maximum high or low times. The minimum high and low times for MDC shall be 160 ns each, and theminimum period for MDC shall be 400 ns regardless of the nominal period of MII operation clockminimum period for MDC shall be 400 ns, regardless of the nominal period of MII operation clock.

MDIO (management data input/output) is a bi-directional signal between the PHY and the STA. It is usedto transfer control information and status between the PHY and the STA. Control information is driven bythe STA synchronously with respect to MDC and is sampled synchronously by the PHY. Statusinformation is driven by the PHY synchronously with respect to MDC and is sampled synchronously bythe STA. MDIO shall be driven through three-state circuits that enable either the STA or the PHY to drivethe signal. A PHY that is attached to the MII via the mechanical interface shall provide a resistive pull-upto maintain the signal in a high state.to maintain the signal in a high state.

2.3 Frame StructureIDLE (IDLE condition)

The IDLE condition on MDIO is a high-impedance state. All three state drivers shall be disabled and thePHY’s pull-up resistor will pull the MDIO line to a logic one.

PRE (preamble)At the beginning of each transaction, the station management entity shall send a sequence of 32

contiguous logic one bits on MDIO with 32 corresponding cycles on MDC to provide the PHY with apattern that it can use to establish synchronization. A PHY shall observe a sequence of 32 contiguous onep y q gbits on MDIO with 32 corresponding cycles on MDC before it responds to any transaction. If the STA

determines that every PHY that is connected to the MDIO signal is able to accept management frames thatare not preceded by the preamble pattern, then the STA may suppress the generation of the preamblepattern, and may initiate management frames with the ST (Start of Frame) pattern.

ST (start of frame)The start of frame is indicated by a <01> pattern. This pattern assures transitions from the default logicone line state to zero and back to one.




OP (operation code)The operation code for a read transaction is <10>, while the operation code for a write transaction is<01>.

PHYAD (PHY Address)The PHY Address is five bits, allowing 32 unique PHY addresses. The first PHY address bit transmittedand received is the MSB of the address A PHY that is connected to the station management entity via theand received is the MSB of the address. A PHY that is connected to the station management entity via themechanical interface shall always respond to transactions addressed to PHY Address zero <00000>.(Note. This specification is not allowed in the HomeBay2 MI operation. HomeBay2 MI responds onlywhen mechanical PHY pin address and PHYAD is the same.) A station management entity that isattached to multiple PHYs must have a priori knowledge of the appropriate PHY Address for each PHY.

REGAD (Register Address)The Register Address is five bits, allowing 32 individual registers to be addressed within each PHY. Thefirst Register Address bit transmitted and received is the MSB of the address. The register accessed atRegister Address zero <00000> shall be the control register defined in the clause 22 2 4 1 and theRegister Address zero <00000> shall be the control register defined in the clause 22.2.4.1, and theregister accessed at Register Address one <00001> shall be the status register defined in the clause22.2.4.2.

TA (turnaround)The turnaround time is a 2 bit time spacing between the Register Address field and the Data field of amanagement frame to avoid contention during a read transaction. For a read transaction, both the STAand the PHY shall remain in a high-impedance state for the first bit time of the turnaround. The PHY shalldrive a zero bit during the second bit time of the turnaround of a read transaction. During a writetransaction the STA shall drive a one bit for the first bit time of the turnaround and a zero bit for thetransaction, the STA shall drive a one bit for the first bit time of the turnaround and a zero bit for thesecond bit time of the turnaround. Fig 3.1 shows the behavior of the MDIO signal during the turnaroundfield of a read trans-action.

Fig 2.1. Waveform of TA Frame

DATA (data)The data field is 16 bits. The first data bit transmitted and received shall be bit 15(MSB) of the registerbeing addressed.

2 4 MDIO timing relationship to MDC2.4. MDIO timing relationship to MDCMDIO (Management Data Input/Output) is a bi-directional signal that can be sourced by the StationManagement Entity (STA) or the PHY. When the STA sources the MDIO signal, the STA shall provide aminimum of 10 ns of setup time and a minimum of 10 ns of hold time referenced to the rising edge ofMDC, as shown in Fig 2.2, measured at the MII connector.When the MDIO signal is sourced by the PHY, it is sampled by the STA synchronously with respect to therising edge of MDC. The clock to output delay from the PHY, as measured at the MII connector, shall be aminimum of 0 ns, and a maximum of 300 ns, as shown in Fig 2.3.




Fig 2.2. MDIO setup time with MDC

Fig 2.3. MDIO hold time with MDC

2.5 Timing Diagram of MI Operationg g pMI has read, write, and interrupt operation. MI read operation is that STA reads the management data inPHY. STA writes the management data to PHY in MI write operation.MI has an interrupt operation to indicate the states of PHY to STA. It can be activated after STA readoperation when it has an internal event.HomeBay2 Chip has a special Interrupt Pin Signal(M_INT pin) which is activated at the moment of PHYevent. It is controlled by the Register ‘USE_MDIO_INT’ defined in Management Register. Note thatM_INT pin has no time-relationship with MDC. When PHY has an internal event, PHY asserts its M_INTsignal until STA reads its interrupt status register. g p g

2.6 Management Register Description 2.6.1 MI Register 0 [Control]

Bit Name Description OurType

Default

0.15 Reset Reset, 1=reset, 0=normal ro 0

14 Loopback Loopback Mode 1=enable 0=normal ro 014 Loopback Loopback Mode, 1=enable, 0=normal ro 0

13 Speed Speed Select, 1=100Mbps, 0=10Mbps ro 0

12 AtuoNegoEn Auto Negotiation, 1=enable, 0=normal ro 0

11 PowerDown Power Down, 1=enable, 0=normal ro 0

10 Isolate Isolation, 1=enable, 0=normal ro 0

9 RestartAutoNego Restart Auto Negotiation, 1=enable, 0=normal ro 0


8 DuplexMode Duplex Mode, 1=full duplex, 0=half duplex ro 0

7 CollisionTest Collision Test, 1=enable, 0=disable ro 0

6#0 Reserved Reserved ro 7`d0



2.6.2 MI Register 1 [Status]

Bit Name Description Default

1.15 100BaseT4 100Base-T4 Capable, 0=nc(not capable) 0

14 100bXF 100B TX f ll d l 0 0

OurType

ro

14 100bXF 100Base-TX full duplex, 0=nc 0

13 100bXH 100Base-TX half duplex, 0=nc 0

12 10MF 10Base-T Full duplex, 0=nc 0

11 10MH 10Base-T half duplex, 0=nc, 1=capable 1

10 100bT2F 100Base-T2 Full duplex, 0=nc, 1=capable 0

9 100bT2H 100Base-T2 Half duplex, 0=nc, 1=capable 0

ro

ro

ro

ro

ro

ro

8#7 Reserved Reserved 2`b0

6 MFpreambleSuppression MI Preamble Suppression, 0-nc 0

5 AutoNegoCompletion AutoNegotiaition Acknowlegement, 1=ack, 0=normal 1

4 RemoteFault Remote Fault Detect, 1=detected, 0=no fault 0

3 AutoNegoAbility Auto Negotiation Capable, 0=nc 0

2 LinkStatus Link Status 1=link detected 0=not detected

ro

ro

ro

ro

ro

ro2 LinkStatus Link Status, 1=link detected, 0=not detected -

1 JabberDetect Jabber Detect, 1=detect, 0=normal 0

0 ExtendedCap. Extended Register Capable, 0=nc, 1=exist

ro

ro

ro 1

2.6.3 MI Register 2 [PHY ID1]

Bit Name Description OurType Default

2.6.4 MI Register 3 [PHY ID2]

2.15#0 PhyId OUI[3 down to 18], Company ID R/W 0x26AA


3.15#10 PhyId OUI[19:24], Company ID Ro 0b1011_00

9#4 Manufacture's model Manufacturer’s Part Number ro 0b001100

3#0 Manufacture's revision Manufacturer’s Revision Number ro 0b0000




2.6.5 MI Register 4 [Auto Negotiation Advertisement ]


4.15 NextPage Next Page Enable, 1=exist, 0=no next page ro 0

14 Reserved Acknowledge 1=received 0=not received ro 014 Reserved Acknowledge, 1=received, 0=not received ro 0

13 RemoteFault Remote Fault Enable, 1=remote fault detected ro 0

12#10 Reserved Reserved ro 0

9 100BaseT4 100Base-T4, 0=nc(not capcable) ro 0

8 100BaseTxF 100Base-TX Full Duplex, 0=nc ro 0

7 100BaseT 100Base-TX Half Duplex 0=nc ro 07 100BaseT 100Base TX Half Duplex, 0 nc ro 0

6 10BaseTxF 10Base-T Full Duplex, 0=nc ro 0

5 10BaseT 10Base-T Half Duplex, 0=nc, 1=capable ro 1

4#0 Reserved Reserved ro 0b00001

2.6.6 MI Register 5 [Auto Negotiation Remote End Capability]


5.15 NextPage Next Page Enable, 1=exist, 0=not exist ro 0

14 Ack Acknowledge, 1=received, 0=not received ro 0

13 RemoteFault Remote Fault, 1=detected, 0=no fault ro 0

12#10 Reserved Reserved ro 010

9 100BaseT4 100Base-T4, 0=nc ro 0

8 100BaseTxF 100Base-TX Full Duplex, 0=nc ro 0

7 100BaseT 100Base-T Full Duplex, 0=nc ro 0

6 10BaseTxF 10Base-T Full Duplex, 0=nc ro 0

5 10BaseT 10Base-T Half Duplex, 0=nc, 1=capable ro 0

4#0 Reserved Reserved ro 0b00000




2.6.7 MI Register 16 [HomeBay2 Control]

Bit Name Description OurType Default16.15

MSK_RX_BUF_FULL Rx Buffer Full Interrupt Mask, 1=mask r/w 1

14 MSK_TX_BUF_FULL Tx Buffer Full Interrupt Mask, 1=mask r/w 1

13 MSK_LINK_FAIL Link Fail Interrupt Mask, 1=mask r/w 1

12 MSK_PIDLE Phy Idle interrupt mask, 1=mask r/w 1

11 USE_MDIO_INT M_INT pin control, 1=use M_INT, 0=disable r/w 0

10 SEL_ACK_ERR_CNT Error Counter(reg19) Select, 1=ack_err, 0=state r/w 1

9 SEL_TX_FRAME_CNT Frame Counter(reg18) Select, 1=tx, 0=rx r/w 0

8 reserved8 reserved

7 CLR_ERR_CNT Error Counter Clear, 1=clear, 0=no action r/w 0

6 CLR_RX_FRAME_CNT RX Frame Counter Clear, 1=clear, 0=no action r/w 0

5 CLR_TX_FRAME_CNT TX Frame Counter Clear, 1=clear, 0=no action r/w 0

4 SET_RX_LINK_HANGUP MII RX Connection Control, 1=hangup, 0=normal r/w 0

3 SET_TX_LINK_HANGUP MII TX Connection Control, 1=hangup, 0=normal r/w 0GUP , g p,

2 reserved

1 SET_INT_POS M_INT polarity contol, 1=positive, 0=negative r/w 0

0 SOFT_RST_n HomeBay2 Soft Reset, 0=reset, 1=normal r/w 1


Bit Name Description OurType Default17.1

5 ISR_RX_BUF_FULL RX buffer full interrupt, 1=buffer full rc 0

14 ISR_TX_BUF_FULL TX buffer full interrupt, 1=buffer full rc 0

13 ISR_LINK_FAIL Link fail interrupt, 1=fail rc 0

12 ISR_PHY_IDLE Phy Idle interrupt, 1=fail rc 011#10 RX_BA_STATE RX link status 0=0.5M;1=1M;2=1.5M;3=2Mbps ro -

li k b d id h9#8 TX_BA_STATE TX link bandwidth status 0=0.5M;1=1M;2=1.5M;3=2M ro -

7 IS_RMII RMII/MII I/F Indication, 1=rmii used, 0=mii used ro Ext. pin

6 IS_MASTER Mode Indicator, 1=master mode, 0=slave mode ro Ext. pin

5 IS_LINK_OK Link Status, 1=ok, 0=nok ro 0

4 IS_ET_ALIVE Ethernet I/F Operation Status, 1=alive, ro 0

3 IS_RET_ALIVE Remote Ethernet I/F operation status, 1=alive ro 0


2 reserved

1 IS_BA Auto bandwidth allocation indicator, 1=enalble ro 0

0 reserved

‘rc’ type is cleared after STA read its value.



2.6.9 MI Register 18 [HomeBay2 Counter]


18.15#0 RX_FRAME_CNT Ethernet RX Frame Counter ro 16`d0

15#0 TX_FRAME_CNT Ethernet TX Frame Counter ro 16`d0



19.15#0 STATE_OUT Phy Analog Frontend State Output ro 16`d0

15#0 ACK ERR CNT Ph Li k A k E t 16`d015#0 ACK_ERR_CNT Phy Link Ack Error counter ro 16`d0



20.15#0 FRAME_ERR_CNT Phy Link Frame Error Counter ro 16`d0



21.15#7 Reserved Reserved R/W 0

6 SET BA “1”: Symmetric “0”: Asymmetric mode R/W 06 SET_BA 1 : Symmetric, 0 : Asymmetric mode R/W 0

5 SET_DHCP_SERVER “1”: DHCP server is Packet drop R/W 0

4 SET_DHCP_CLIENT “1”: DHCP client is Packet drop R/W 0

3 SET_NETBIOS_IPTCP “1”: IP datagram TCP packet is Netbios drop R/W 0

2 SET_NETBIOS_IPUDP “1”: IP datagram UDP packet is Netbios drop R/W 0

1 SET NETBIOS IPX “1”: IPX packet is Netbios drop R/W 01 SET_NETBIOS_IPX 1 : IPX packet is Netbios drop R/W 0

0 SET_NETBIOS_LLC “1”: LLC packet is Netbios drop R/W 0




2.6.13 EEPROM Register Definitions

BitName Description Default

16THS_POWER Power Detection Threshold 16’h0708

8REF_PEAKAVG AGC Reference Gain Value 8’hc0

Address

0

1.H

8GAIN_STEP AGC Gain Step Size 8’h08

8PRE_THS Pre Sync Zero Detector Threshold Normally Less than SYNC_THS 8’h12

8SYNC_THS Sync Detector Threshold 8’h18

8TICK_OFST Sync Detector Tick Time Offset 8’h06

1.L

2.H

2.L

3.H

8PHASE_OFFSET_BIAS Symbol Recovery Phase Offset 8’h02

16ROM_EQ_END EQ Freeze CRC_OK Count Number 16’h0032

16ROM_EQ_TIME_OUT EQ Training Time Out 16’h2000

16ROM_WAIT_TIME_OUT Wait State Time Out 16’h0400

16ROM_TX_OFF_END 16’h0800

3.L

4

5

6

7 Tx off Time Interval in PHY_RE INIT state

8ROM_PHY_INIT_COND

PHY_RE_INIT Condition Selection00 : CRC Error = 204801 : CRC Error = 102402 : CRC Error = 51203 : CRC Error = 256others : 128

8’h02

8ROM PLL OFST

PLL__OFST[1] ? 1 : Loop Filter ON0 : Loop Filter OFF 8’h0A

8.H

8 L 8ROM_PLL_OFST 0 : Loop Filter OFF PLL_OFST[3] ?1: OFFSET Enable ON0: OFFSET Enable OFF

8’h0A 8.L




7. Band width Allocation

7.1 Symmetric in pure modeIn Symmetric configuration mode, both HomeBay2 chip work only symmetric mode. There is no dynamicBand width allocation. From the meaning of the word ‘symmetric’, just share channel equally by both sideHomeBay2 chip.

7 2 S i d i h B d id h i i7.2 Symmetric mode with Bandwidth restrictionBut, Not dynamically, HomeBay2 has a feature to restrict to selected Band width. Service Provider can restrictsubscriber’s Band width to some special bps. In these limited Band width mode, Service Provider candifferentiate subscriber-As(who need cheaper connection service and think less band width is OK) fromsubscriber-Bs (who need more band width but money is not matter). In addition to this, Service Provide candifferentiate subscriber-Cs(who need more bandwidth in down load) from subscriber-Ds(who need morebandwidth in up load). The limited Band width mode can be used only in the symmetric configuration.(CAUTION : Symmetric with Bandwidth restriction mode must be set equally both side’s Rx to Tx and Tx toR i El th li k b t M t d Sl l k lik OK b t th i d t th h ld b t d iRx pairs. Else the link between Master and Slave may look like OK, but their data path should be corrupted inReal data communication.)

7.3 Asymmetric modeIn Asymmetric configuration mode, HomeBay2 can manage it’s the channel band width dynamically. For thisfeature, two HomeBay2 chip share the counter part HomeBay2 chip’s status and local HomeBay2 chip’s statusvia. Their Header frame. Master HomeBay2 chip gather these information, and arbitrate between two

HomeBay2HomeBay2chips which are pending to send data to each other.If Master knows both side HomeBay2 chip have a data to send, Master controls itself and slave to work insymmetric mode. Also, if Master knows both side HomeBay2 chips have no data to send, Master controls

itselfand slave to work in symmetric mode until these status changed.If Master knows slave want to send a data, but master itself has no pending data to send, master controls itselfto asymmetric mode without grant and slave to asymmetric mode with grant. After that, master just send it’sheader frame and receive slave’s data during the hole left frame time. Slave just receives master’s headerg jframe and send it’s pending data during the hole left frame time.In opposition to the case mentioned above, if master knows slave has no data to send but master has a data tosend, master controls itself to asymmetric mode with grant and slave to asymmetric mode without grant. Theirworking just look like the opposition case of above case.



Timing Diagrams

1. SNMP(MDIO)

1.1. MI Read Timing- At R0 phase vertical bar = PHY fetches the R0 at rising edge of MDC. Hi-Z in PHYout. STA disables its output after hold

time.A Z h i l b PHY h i Bi Di d i d f h ld i d d i h l i Z- At Z phase vertical bar = PHY changes its Bi-Dir pad into output mode after hold time and drives the value in Zero.

- At D15 phase vertical bar = PHY drives the addressed register value at the rising clock of 1st D15 value.

1.2. MI Write Timing

1.3. MI Interrupt Timing



Circuit



Circuit (Continued)



Ph i l S ifi tiPhysical Specifications

D1

1

128 103

D

102

nSYS Tec

Hom

eBay 2.

E E1

ch.0

38 65

6439 be

see

AA

A

21

L

c

θ

seePin Detail L Pin Detail1

y



Ph i l S ifi ti ( ti d)Physical Specifications (continued)




1.1 Absolute Maximum Ratings

SYMBOL PARAMETER UNITSVCC Power Supply V

RATING-0.3 to 3.6pp y

VIN Input Voltage VVOUT Output Voltage VVCC5 Power Supply for Dual Oxide Cells VVIN5 Input Voltage for Dual Oxide Cells V

VOUT5 Output Voltage VTSTG Storage Temperature °C

-0.6 to 6.0-0.3 to VCC5 + 0.3-0.3 to VCC5 + 0.3

-55 to 150

-0.3 to VCC + 0.3-0.3 to VCC + 0.3

1.2 Recommended Operating Conditions

SYMBOL PARAMETER MIN TYP MAX UNITSVCC Power Supply 3.0 3.3 3.6 VVIN Input Voltage 0 - VCC V

Commercial Power Supply for Dual Oxide Cells 4.75 5.0 5.25Industrial Power Supply for Dual Oxide Cells 4.5 5.0 5.5

VIN5 Input Voltage 0 - VCC5 VCommercial Junction Operating Temperature 0 25 115Industrial Junction Operating Temperature -40 25 125

V

°C

VCC5

Tj

1.3 General DC Characteristics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSIIL Input leakage current no pull-up or pull-down -1 1 uAIOZ Tri-state leakage current -1 1 uACIN3 3.3V input capacitance 2.8 pEp p p

COUT3 3.3V output capacitance 2.7 4.9 pE

3.3V Bi-directional 2.7 4.9 pEbuffer capacitance

CIN5 5V Input capacitance 2.8 pE

CBID3




Faraday Technology Corp.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSCOUR5 5V Output capacitance 2.7 5.6 pFCBID5 5VBi di ti l b ff 2 7 5 6 pF

The Capacitance listed above does not include PAD capacitance and package capacitance. One can estimate pin capacitance by adding pad capacitance which is about 0.5pF and the package capacitance.

Note :

1.4 DC Electrical Characteristics for 3.3V Operation(under Recommended Operating Conditions and VCC =3.0~3.6v, Tj=0 °C to + 115 °C)

CBID5 5V Bi-directional buffer 2.7 5.6 pFcapacitance

(under Recommended Operating Conditions and VCC 3.0 3.6v, Tj 0 C to 115 C)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSVIL Input Low Voltage CMOS 03*VCC VVIH Input High Voltage CMOS 0.7*VCC VVt- Schmitt trigger negative CMOS 1.20 V

going threshold voltage

Vt+ Schmitt trigger positive CMOS 2 10 VVt+ Schmitt trigger positive CMOS 2.10 Vgoing threshold voltage

VOL Output low voltage IOL=2,4,8,12,16,24 mA 0.4 VVOH Output high voltage IOH=2,4,8,12,16,24 mA 2.4 VRI Input Pull-up / down VIL=0V or VIH = VCC 75 KΩ

resistance

1.5 DC Electrical Characteristics for 5V Operation(under Recommended Operating Conditions and VCC =4.75v~5.25v, Tj=0 °C to + 115 °C)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSVIL Input Low Voltage CMOS 03*VCC VVIH Input High Voltage CMOS 0.7*VCC VVIL Input Low Voltage TTL 0.8 Vp gVIH Input High Voltage TTL 2.0Vt- Schmitt trigger negtive CMOS 1.78


Vt+ Schmitt trigger positive CMOS 3.20 Vgoing threshold voltage

Vt- Schmitt trigger negtive TTL 1.10 Vgoing threshold voltage



Vt+ Schmitt trigger positive TTL 1.90 Vgoing threshold voltage

HomeBay2.0 ASIC preliminary 20070604 R0.1.ppt [호환 모드] · PDF fileto 10,000 feet with...

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