HCPL-788J

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15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

FAULTABSVAL

VOUT

VREF

VIN+

VIN-RSENSE1SHORT CIRCUIT FAULT

ISOLATION BOUNDARY

A/DCONVERTER

MICROCONTROLLER

HCPL-788J

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

FAULT

ABSVAL

VOUT

VREF

VIN+

VIN-RSENSE2

ISOLATION BOUNDARY

HCPL-788J

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

FAULT

ABSVAL

VOUT

VREF

VIN+

VIN-RSENSE3

ISOLATION BOUNDARY

HCPL-788J

M

+5 V

OVERLOADFAULT+

+

3 PHASE ABSOLUTEVALUE OUTPUT

VREF

VTH

3 PHASE

MOTOR

Low Cost Three Phase Current Sensing with Short Circuit and Overload Detection

HCPL-788J

Isolation Amplifer with Short Circuit and Overload Detection

Data Sheet

Description

Avagos Isolation Amplifer with Short Circuit and Over-load Detection makes motor phase current sensing com-pact, aordable and easy-to-implement while satisyingworldwide saety and regulatory requirements.

Applications

x Motor phase and rail current sensing

x Power inverter current and voltage sensingx Industrial process control

x Data acquisition systems

x General purpose current and voltage sensing

x Traditional current transducer replacements

CAUTION:It is advised that normal static precautions be taken in handling and assembly of

this component to prevent damage and/or degradation which may be induced by ESD.

Features

x Output Voltage Directly Compatible with A/DConverters (0 V to V

REF)

x Fast (3 s) Short Circuit Detection with Transient FaultRejection

x Absolute Value Signal Output or Overload Detection

x 1 V/C Oset Change vs. Temperature

x SO-16 Package

x -40C to +85C Operating Temperature Range

x 25 kV/s Isolation Transient Immunity

x Regulatory Approvals: UL, CSA, IEC/EN/DIN EN 60747-5-2 (1230 Vpeak Working Voltage)

Lead (Pb) FreeRoHS 6 fully

compliantRoHS 6 ully compliantoptionsavailable;-xxxE denotesa lead-reeproduct

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Description

The HCPL-788J isolation ampli-fer is designed or cur-rent sensing in electronic motor drives. In a typicalimplementa-tion, motor currents ow through an ex-ternal resistor and the resulting analog voltage drop issensed by the HCPL-788J. A larger analog output volt-age is created on the other side o the HCPL-788Js opti-

cal isolation barrier. The output voltage is proportionalto the motor current and can be connected directly to asingle-supply A/D converter. A digital over-range output(FAULT) and an analog rectifed output (ABSVAL) are also

Figure 1. Current sensing circuit.

provided. The wire OR-able over-range output (FAULT)is useul or quick detection o short circuit conditionson any o the motor phases. The wire-OR-able rectifedoutput (ABSVAL), simplifes measure-ment o motor loadsince it perorms polyphase rectifcation. Since the com-mon-mode voltage swings several hundred volts in tens

o nanoseconds in modern electronic motor drives, theHCPL-788J was designed to ignore very high common-mode transient slew rates (10 kV/s).

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

GND2

VDD2

FAULT

ABSVAL

VOUT

VREF

VDD2

GND2

VIN+

VIN-

CH

CL

VDD1

VLED+

VDD1

GND1

RSHUNT0.02

ISOLATED +5 V

4.7 k

39

.01 F

0.1 F

0.1 F

ISOLATION BOUNDARY

INPUTCURRENT

+5 V

A/D

VREF

GND

C

TO OTHERPHASE

OUTPUTS

+

0.1 F

HCPL-788J

Symbol Description

FAULT Short circuit ault output. FAULT changes rom a

high to low output voltage within 6 s ater VIN

exceeds the FAULT Detection Threshold. FAULT is an

open drain output which allows outputs rom all

the HCPL-788Js in a circuit to be connected

together (wired-OR) orming a single ault s ignal

or interacing directly to the micro-controller.

ABSVAL Absolute value o VOUT

output. ABSVAL is 0 V

when VIN

=0 and increases toward VREF

as VIN

approaches +256 mV or -256 mV. ABSVAL is

wired-OR able and is used or detectingoverloads.

VOUT

Voltage output. Swings rom 0 to VREF

.

The nominal gain is VREF

/504 mV.

VREF

Reerence voltage input (4.0 V to VDD2

). This

voltage establishes the ull scale output ranges

and gains o VOUT

and ABSVAL.

VDD2

Supply voltage input (4.5 V to 5.5 V).

GND2

Ground input.

Symbol Description

VIN+

Positive input voltage (200 mV recommended).

VIN-

Negative input voltage (normally connected to

GND1).

CH

Internal Bias Node. Connections to or between CH

CL

and CL

other than the required 0.1 F capacitorshown, are not recommended.

VDD1


VLED+

LED anode. This pin must be let unconnected or

guaranteed data sheet perormance. (For optical

coupling testing only.)

VDD1


GND1

Ground input.

GND2

Ground input.

VDD2


Pin Descriptions

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Ordering Inormation

HCPL-788J is UL Recognized with 5000 Vrms or 1 minute per UL1577.

Part

Number

Option

Package

Surace

Mount

Tape

& Reel

IEC/EN/DIN EN

60747-5-2 Quantity

RoHS

Compliant

non RoHS

Compliant

HCPL-788J-000E no option

SO-16X X 45 per tube

-500E #500 X X X 850 per reel

To order, choose a part number rom the part number column and combine with the desired option rom the optioncolumn to orm an order entry.

Example 1:HCPL-788J-500E to order product o 16-Lead Surace Mount package in Tape and Reel packaging with IEC/EN/DIN EN60747-5-2 Saety Approval and RoHS compliant.

Example 2:HCPL-788J to order product o 16-Lead Surace Mount package in Tube packaging and non RoHS compliant.

Option datasheets are available. Contact your Avago sales representative or authorized distributor or inormation.

Remarks: The notation #XXX is used or existing products, while (new) products launched since July 15, 2001 andRoHS compliant will use XXXE.

Note: Initial and continued variation in the color o the HCPL-788Js white mold compound is normal and does not aect device perormance orreliability.Note: Floating lead protrusion is 0.25 mm (10 mils) max.

Package Outline Drawings16-Lead Surace Mount

Dimensions in inches (millimeters)

9

0.295 0.010(7.493 0.254)

10111213141516

87654321

0.018(0.457)

0.138 0.005(3.505 0.127)

9

0.406 0.10(10.312 0.254)

0.408 0.010(10.160 0.254)

0.025 MIN.

0.008 0.003(0.203 0.076)

STANDOFF

0.345 0.010(8.986 0.254)

08

0.018(0.457)

0.050(1.270)

ALL LEADSTO BECOPLANAR 0.002

A 788J

YYWW

TYPE NUMBER

DATE CODE

0.458 (11.63)

0.085 (2.16)

0.025 (0.64)

LAND PATTERN RECOMMENDATION

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Recommended Pb-Free IR Profle

Recommended reow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.

Package Characteristics

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Notes

Input-Output MomentaryWithstand Voltage

VISO

5000 Vrms RH < 50%, t = 1 min.,T

A= 25C

1,2,3

Resistance (Input-Output) RI-O

>109 VI-O

= 500 VDC

3

Capacitance ( Input-Output) CI-O

1.3 pF = 1 MHz 3

Input IC Junction-to-CaseThermal Resistance

Tjci 120 C/W TA = 85C

Output IC Junction-to-CaseThermal Resistance

Tjco 100 C/W TA

= 85C

Regulatory InormationThe HCPL-788J has been approved by the ollowing organizations:

IEC/EN/DIN EN 60747-5-2

Approved under:IEC 60747-5-2:1997 + A1:2002EN 60747-5-2:2001 + A1:2002DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01.

UL

Recognized under UL 1577, component recognitionprogram, File E55361.

CSA

Approved under CSA Component Acceptance Notice#5, File CA 88324.

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Figure 2. Dependence o saety-limiting values on

temperature.

IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*

Description Symbol Characteristic Unit

Installation classifcation per DIN VDE 0110/1.89, Table 1or rated mains voltage 300 V

rms

or rated mains voltage 600 Vrms

or rated mains voltage 1000 Vrms

I-IVI-IVI-III

Climatic Classifcation 55/85/21

Pollution Degree (DIN VDE 0110/1.89) 2

Maximum Working Insulation Voltage VIORM

1230 VPEAK

Input to Output Test Voltage, Method b**V

IORMx 1.875 = V

PR, 100% Production Test with

tm = 1 sec, Partial discharge < 5 pC

VPR

2306 VPEAK

Input to Output Test Voltage, Method a**V

IORMx 1.6 = V

PR, Type and Sample Test, t

m= 10 sec,

Partial discharge < 5 pC

VPR

1968 VPEAK

Highest Allowable Overvoltage (Transient Overvoltage tini

= 60 sec) VIOTM

8000 VPEAK

Saety-limiting values maximum values allowed in theevent o a ailure, also see Figure 2.

Case TemperatureInput PowerOutput Power

TSPS1, INPUT

PS1, OUTPUT

175400600

CmWmW

Insulation Resistance at TSI, V

IO= 500 V R

S>109

PsPOWERmW

00

TS CASE TEMPERATURE C

20025

800

50 75 100

200

150 175

Psi OUTPUT

Psi INPUT

125

400

600

* Isolation characteristics are guaranteed only within the saety maximum ratings which mustbe ensured by protective circuits within the application. Surace Mount Class ifcation is classA in accordance with CECC00802.

** Reer to the optocoupler section o the isolation and Control Components DesignersCatalog, under Product Saety Regulations section IEC/EN/DIN EN 6747-5-2, or a detaileddescription o Method a and Method b partial discharge test profles.

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Insulation and Saety Related Specifcations

Parameter Symbol Min. Max. Conditions

Minimum External Air Gap(Clearance)

L(101) 8.3 mm Measured rom input terminals to output terminals,shortest distance through air.

Minimum External Tracking(Creepage)

L(102) 8.3 mm Measured rom input terminals to output terminals,shortest distance path along body.

Minimum Internal Plastic Gap 0.5 mm Through insulation distance conductor to conductor,usually the straight line distance thickness between theemitter and detector.

Tracking Resistance CTI >175 Volts DIN IEC 112/VDE 0303 Part 1Comparative Tracking Index)

Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Note

Storage Temperature TS

-55 125 C

Operating Temperature TA -40 100 CSupply Voltages V

DD1, V

DD20.0 5.5 V 4

Steady-State Input Voltage VIN+

, VIN-

-2.0 VDD1

+ 0.5 V

2 Second Transient Input Voltage VIN+

, VIN-

-6.0 VDD1

+ 0.5 V

Output Voltage VOUT

-0.5 VDD2

+ 0.5 V

Absolute Value Output Voltage ABSVAL -0.5 VDD2

+ 0.5 V

Reerence Input Voltage VREF

0 VDD2

+ 0.5 V V 5

Reerence Input Current IREF

20 mA

Output Current IVOUT

20 mA

Absolute Value Current IABSVAL

20 mA

FAULT Output Current IFAULT

20 mA

Input IC Power Dissipation PI

200 mW

Output IC Power Dissipation PO

200 mW

Recommended Operating Conditions

Parameter Symbol Min. Max. Units Note

Ambient Operating Temperature TA

-40 85 C

Supply Voltages VDD1

, VDD2

4.5 5.5 V

Input Voltage (accurate and linear) VIN+

, VIN-

-200 200 mV

Input Voltage (unctional) VIN+

, VIN-

-2 2 V

Reerence Input Voltage VREF

4.0 VDD2

V

FAULT Output Current IFAULT

4 mA

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DC Electrical Specifcations

Unless otherwise noted, all typicals and fgures are at the nominal operating conditions o VIN+

= 0, VIN-

= 0 V, VREF

=4.0 V, V

DD1= V

DD2= 5 V and T

A= 25C; all Minimum/Maximum specifcations are within the Recommended Operating

Conditions.

Parameter Symbol Min. Typ. Max. Units

Test

Conditions Fig. Note

Input OsetVoltage VOS -3 0 3 mV VIN+ = 0 V,T

A= 40C to +85C 3, 4,5 6

Magnitude o InputOset Change vs.Temperature

|VOS

/TA| 1 10 V/C V

IN+= 0 V,

TA

= 40C to +85C7

VOUT

Gain G VREF

/504mV - 3%

VREF

/504mV

VREF

/504mV + 3%

V/V |VIN+

| < 200 mV,T

A= 25C

6,7,8,9

VOUT

Gain G VREF

/504mV - 5%

VREF

/504mV

VREF

/504mV + 5%

V/V |VIN+

| < 200 mV,T

A= 40C to +85C

6,7,8,9

Magnitude o VOUT

Gain Change vs.Temperature

|G/TA| 50 300 ppm/C |V

IN+| < 200 mV,

TA

= 40C to +85C6,7,8,9

8

VOUT

200 mVNonlinearity

NL200

0.06 0.4 % |VIN+

| < 200 mV,T

A= 40C to +85C

6,7,8,9

Maximum InputVoltage BeoreV

OUTClipping

|VIN+

|MAX

256 mV

FAULT DetectionThreshold

|VTHF

| 230 256 280 mV 10 9

FAULT LowOutput Voltage

VOLF

350 800 mV IOL

= 4 mA

FAULT HighOutput Current

IOHF

0.2 15 A VFAULT

= VDD2

ABSVAL OutputError

eABS

0.6 2 % o ull scale

output

11 10

Input SupplyCurrent

IDD1

10.7 20 mA

Output SupplyCurrent

IDD2

10.4 20 mA

Reerence VoltageInput Current

IVREF

0.26 1 mA

Input Current IIN+

-350 nA VIN+

= 0 V

Input Resistance RIN

800 k VIN+

= 0 V

VOUT

OutputResistance

ROUT

0.2

ABSVAL OutputResistance

RABS

0.3

Input DC Common-Mode RejectionRatio

CMRRIN

85 dB 11

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AC Electrical Specifcations

Unless otherwise noted, all typicals and fgures are at the nominal operating conditions o VIN+

= 0, VIN-

= 0 V, VREF

=4.0 V, V

DD1= V

DD2= 5 V and T

A= 25C; all Minimum/Maximum specifcations are within the Recommended Operating

Conditions.

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note

VOUT

Bandwidth (-3dB) BW 20 30 kHz VIN+

= 200 mVpk-pk

sine wave.

12,

20V

OUTNoise N

OUT2.2 4 mVrms V

IN+= 0 V 20 12

VIN

to VOUT

Signal Delay(50 - 50%)

tDSIG

9 20 s VIN+

= 50 mV to200 mV step.

14,20

13

VOUT

Rise/Fall Time(1090)

tRFSIG

10 25 s VIN+


14,20

ABSVAL Signal Delay tDABS

9 20 s VIN+


14,20

ABSVAL Rise/Fall Time(1090%)

tRFABS

10 25 s VIN+


14,20

FAULT Detection Delay tFHL

3 6 s VIN+


15,20

14

FAULT Release Delay tFLH 10 20 s VIN+ = 500 mV to0 mV step.

16,20

15

Transient Fault Rejection tREJECT

1 2 s VIN+

= 0 mV to500 mV pulse.

17,20

16

Common Mode TransientImmunity

CMTI 10 25 kV/s For VOUT

, FAULT, andABSVAL outputs.

17

Common-Mode RejectionRatio at 60 Hz

CMRR >140 dB 18

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Notes:

1. In accordance with UL1577, each optocoupler is proo tested by applying an insulation test voltage 600 Vrms or 1 second. This test isperormed beore the 100% production test or partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristic Table,i applicable.

2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-outputcontinuous voltage rating. For the continuous voltage rating reer to your equipment level saety specifcation or IEC/EN/DIN EN 60747-5-2insulation characteristics table.

3. Device considered a two terminal device: pins 1-8 shorted together and pins 9-16 shorted together.4. V

DD1must be applied to both pins 5 and 7. V

DD2must be applied to both pins 10 and 15.

5. I VREF exceeds VDD2 (due to power-up sequence, or example), the current into pin 11 (IREF) should be limited to 20 mA or less.6. Input Oset voltage is defned as the DC Input voltage required to obtain an output voltage (at pin 12) o VREF

/2.7. This is the Absolute Value o Input Oset Change vs. Temperature.8. This is the Absolute Value o V

OUTGain Change vs. Temperature.

9. |VIN+

| must exceed this amount in order or the FAULT output to be activated.

10. ABSVAL is derived rom VOUT

(which has the gain and oset tolerances stated earlier). ABSVAL is 0 V when VIN

= 0 V and increases toward VREF

asV

INapproaches +256 mV or -256 mV. H

ABSis the dierence between the actual ABSVAL output and what ABSVAL should be, given the value o

VOUT

. HABS

is expressed in terms opercent o ull scale and is defned as:

|ABSVAL - 2 x | VOUT

- VREF

/ 2| |x 100.

VREF

11. CMRRIN

is defned as the ratio o the gain or dierential inputs applied between pins 1 and 2 to the gain or common mode inputs applied toboth pins 1 and 2 with respect to pin 8.

12. The signal-to-noise ratio o the HCPL-788J can be improved with the addition o an external low pass flter to the output. See Frequently AskedQuestion #4.2 in the Applications Inormation Section at the end o this data sheet.

13. As measured rom 50% o VIN

to 50% o VOUT

.

14. This is the amount o time rom when the FAULT Detection Threshold (230 mV VTHF 280 mV) is exceeded to when the FAULT output goeslow.

15. This is the amount o time or the FAULT Output to return to a high state once the FAULT Detection Threshold (230 mV VTHF

280 mV) is nolonger exceeded.

16. Input pulses shorter than the ault rejection pulse width (tREJECT

), will not activate the FAULT (pin 14) output. See Frequently Asked Question #2.3in the Applications Inormation Section at the end o this data sheet or additional detail on how to avoid alse tripping o the FAULT output dueto cable capacitance charging transients.

17. CMTI is also known as Common Mode Rejection or Isolation Mode Rejection. It is tested by applying an exponentially rising alling voltagestep on pin 8 (GND1) with respect to pin 9 (GND2). The rise time o the test waveorm is set to approximately 50 ns. The amplitude o the stepis adjusted until V

OUT(pin 12) exhibits more than 100 mV deviation rom the average output voltage or more than 1s. The HCPL-788J will

continue to unction i more than 10 kV/s common mode slopes are applied, as long as the break-down voltage limitations are observed. [TheHCPL-788J still unctions with common mode slopes above 10 kV/s, but output noise may increase to as much as 600 mV peak to peak.]

18. CMRR is defned as the ratio o dierential signal gain (signal applied dierentially between pins 1 and 2) to the common mode gain (input pinstied to pin 8 and the signal applied between the input and the output o the isolation amplifer) at 60 Hz, expressed in dB.

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Figure 3. Input oset voltage change vs.

temperature.

Figure 4. Input oset voltage change vs. VDD1

. Figure 5. I nput oset vo ltage c hange vs. VDD2

.

Figure 6. VOUT vs. VIN. Figure 7. Gain change vs. temperature. Figure 8. Gain change vs. VDD1.

VOSOFFSETCHANGEV

4.5-800

INPUT SUPPLY VOLTAGE VDD1 V

800

4.75 5.0 5.25 5.5

0

600

400

200

-200

-400

-600 VOSOFFSETCHANGEV

4.5-800

OUTPUT SUPPLY VOLTAGE VDD2 V

800

4.75 5.0 5.25 5.5

0

600

400

200

-200

-400

-600

VOUTOUTPUTVOLTAGEV

-3000

INPUT VOLTAGE VIN mV

4.0

-200 0 100 300

2.0

3.5

3.0

2.5

1.5

1.0

0.5

-100 200

GAINCHANGE-%

-40-2.0

TEMPERATURE C

-20

2.0

0 20

-1.0

60 80

TYPICALWORST CASE

40

0

1.0

1.5

0.5

-0.5

-1.5

GAINCHANGE-%

4.5-2.0

INPUT SUPPLY VOLTAGE VDD1 V

2.0

4.75 5.0 5.25 5.5

0

1.5

1.0

0.5

-0.5

-1.0

-1.5

Figure 9. Gain change vs. VDD2

. Figure 10. FAULT output voltage vs. VIN

. Figure 11. ABSVAL output voltage vs. VIN

.

G

AINCHANGE-%

4.5-2.0

OUTPUT SUPPLY VOLTAGE VDD2 V

2.0

4.75 5.0 5.25 5.5

0

1.5

1.0

0.5

-0.5

-1.0

-1.5

FAULTOUTPU

TVOLTAGEFAULTBARV

-3000


5.0

-200 0 100 300

2.0

3.5

3.0

2.5

1.51.0

0.5

-100 200

4.0

4.5

ABSVALAB

SOLUTEVALUEOUTPUTV

-3000


4.0

-200 0 100 300

2.0

3.5

3.0

2.5

1.5

1.0

0.5

-100 200

INPUTOFFSETCHANGE-VOS-uV

-40-800.0

TEMPERATURE DEG C

-20

800.0

0 20

-400.0

60 80

TYPICALMAX

40

0

400.0

600.0

200.0

-200.0

-600.0

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Figure 15. FAULT detection, 0 to 300 mV input,at V

REF= 5 V.

Figure 12. Bandwidth vs. temperature. Figure 13. FAULT detection delay vs. tempera-

ture.

Figure 14. Step response, 0 to 200 mV input, atV

REF= 5 V.

Figure 16. FAULT release, 300 to 0 mV input, atV

REF= 5 V.

Figure 17. FAULT rejecting a 1 s, 0 to 2 V to 0

input. Rejection is independent o amplitude.

Figure 18. Detection o 6 s ault 0 to 2 V to0 input, at V

REF= 5 V.

Figure 19. Sine response 400 mV pk to pk 4 kHzinput, at V

REF= 5 V.

B

ANDWIDTHkHz

-4025

TEMPERATURE C

-20

35

0 20 60 8040

30

34

33

32

31

29

28

27

26 FAULTDETECTIONDELAYs

-402.5

TEMPERATURE C

-20

3.5

0 20 60 8040

3.0

2.75

3.25

0 V

2.5 V

5 V

0 V

2.5 V

5 V

0 V

2.5 V

5 V

-300 mV

0 mV

300 mV

5.00 s/DIV

VIN 300 mV/D

VOUT (PIN 12)2.5 V/D

FAULT (PIN 14) 2.5 V/D

ABSVAL (PIN 13)2.5 V/D

0 V

2.5 V

5 V

0 V

2.5 V

5 V

0 V

2.5 V

5 V

-300 mV

0 mV

300 mV

5.00 s/DIV

VIN 300 mV/D

VOUT (PIN 12) 2.5 V/D


FAULT (PIN 14)2.5 V/D

0 V

2.5 V

5.0 V

0 V

2.5 V

5.0 V

0 V

2.5 V

5.0 V

-2 V

0 mV

2 V

5.00 s/DIV

VIN 2.0 V/D



FAULT(PIN 14)2.5 V/D

0 V

2.5 V

5 V

0 V

2.5 V

5 V

0 V

2.5 V

5 V

-300 mV

0 mV

300 mV

100 s/DIV

VIN 300 mV/D


ABSVAL (PIN 13) 2.5 V/D


0 V

2.5 V

5 V

0 V

2.5 V

5 V

0 V

2.5 V

5 V

-300 mV

0 mV

300 mV

5.00 s/DIV

VIN 300 mV/D


ABSVAL (PIN 13) 2.5 V/D


5.00 s/DIV

0 V

2.5 V

5 V

0 V

2.5 V

5 V

0 V

2.5 V

5 V

-300 mV

0 mV

300 mV


VIN 300 mV/D



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Figure 20. AC test circuit.

Figure 21. Internal block diagram.

14

13

12

11

10,15

9, 16

1

3

4

6

5, 7

2, 8

FAULT

ABSVAL

VOUT

VDD2

VIN+

VDD1

4.7 k50

0.01 F

0.1 F

0.1 F

HCPL-788J

VREF

10

0.1 F

0.1 F

5 V

1VREF

VOUT

FAULT

ABSVAL

VDD2

VDD2

GND2

GND2

VIN+

VIN-

CH

CL

VLED+

VDD1

VDD1

GND1

2

3

4

6

5

7

8

11

12

13

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10

9

16

MODULATOR

256 mVREFERENCE

FAULTDETECT

ENCODER

RECTIFIER

DECODER D/A LPF

HCPL-788J

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Figure 24. ABSVAL with 1 phase.Figure 23. ABSVAL with 2 phases, wired-ORed

together.

Figure 22. ABSVAL with 3 phases, wired-ORed

together.

ABSVALV

00

TIME SECONDS

4.0

0.01 0.02 0.03 0.04

2.0

3.0

1.0

Applications Inormation

Production Description

Figure 21 shows the internal block diagram o the HCPL-788J. The analog input (V

IN) is converted to a digital signal

using a sigma-delta (-) analog to digital (A/D) convert-er. This A/D samples the input 6 million times per second

and generates a high speed 1-bit output representingthe input very accurately. This 1 bit data stream is trans-mitted via a light emitting diode (LED) over the opticalbarrier ater encoding. The detector converts the opticalsignal back to a bit stream. This bit stream is decodedand drives a 1 bit digital to analog (D/A) converter. Finallya low pass flter and output buer drive the output signal(V

OUT) which linearly represents the analog input. The out-

put signal ull-scale range is determined by the externalreerence voltage (V

REF). By sharing this reerence voltage

(which can be the supply voltage), the ull-scale range othe HCPL-788J can precisely match the ull-scale range oan external A/D converter.

In addition, the HCPL-788J compares the analog input(V

IN) to both the negative and positive ull-scale values.

I the input exceeds the ull-scale range, the short-circuitault output (FAULT) is activated quickly. This eature op-erates independently o the - A/D converter in orderto provide the high-speed response (typically 3 s) need-

ed to protect power transistors. The FAULT output is wireOR-able so that a short circuit on any one motor phasecan be detected using only one signal.

One other output is provided the rectifed output(ABSVAL). This output is also wire OR-able. The motorphase having the highest instantaneous rectifed out-put pulls the common output high. When three sinu-soidal motor phases are combined, the rectifed output(ABSVAL) is essentially a DC signal representing the rmsmotor current. This single DC signal and a thresholdcomparator can indicate motor overload conditions be-ore damage to the motor or drive occur. Figure 22 showsthe ABSVAL output when 3 HCPL-788Js are used to mon-itor a sinusoidal 60 Hz current. Figures 23 and 24 showthe ABSVAL output when only 2 or 1 o the 3 phases aremonitored, respectively.

The HCPL-788Js other main unction is to provide gal-vanic isolation between the analog input and the ana-log output. An internal voltage reerence determines theull-scale analog input range o the modulator (approxi-mately 256 mV); an input range o 200 mV is recom-mended to achieve optimal perormance.

ABSVAL

V

00

TIME SECONDS

4.0

0.01 0.02 0.03 0.04

2.0

3.0

1.0

ABSVALV

00

TIME SECONDS

4.0

0.01 0.02 0.03 0.04

2.0

3.0

1.0

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Analog Interacing

Power Supplies and Bypassing

The recommended supply connections are shown inFigure 26. A oating power supply (which in many ap-plications could be the same supply that is used to drivethe high-side power transistor) is regulated to 5 V us-ing a simple zener diode (D1); the value o resistor R4should be chosen to supply sucient current rom theexisting oating supply. The voltage rom the currentsensing resistor (Rsense) is applied to the input o theHCPL-788J through an RC anti-aliasing flter (R2 and C2).

Figure 25. Recommended applications circuit.

Figure 26. Recommended supply and sense resistor connections.

Although the application circuit is relatively simple, a ewrecommendations should be ollowed to ensure optimal

perormance.

The power supply or the HCPL-788J is most oten ob-tained rom the same supply used to power the powertransistor gate drive circuit. I a dedicated supply is re-quired, in many cases it is possible to add an additionalwinding on an existing transormer. Otherwise, somesort o simple isolated supply can be used, such as a linepowered transormer or a high-requency DC-DC con-verter.

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

GND2

VDD2

FAULT

ABSVAL

VOUT

VREF

VDD2

GND2

VIN+

VIN-

CH

CL

VDD1

VLED1+

VDD1

GND1

RSHUNT0.02

ISOLATED +5 V

R3 4.7 k

R239

.01 F

C30.1 F

C10.1 F

HCPL-788J

INPUTCURRENT

+5 V

A/D

VREF

GND

C

TO OTHERPHASE OUTPUTS

+

R1C2

C60.1 F

C4C8 C7 C5

C5 = C7 = C8 = 470 pFC4 = 0.1 F

16

15

14

13

12

11

10

9

5

1

2

8

7

3

4

6

GND2

VDD2

FAULT

ABSVAL

VOUT

VREF

VDD2

GND2

VDD1

VIN+

VIN-

GND1

VDD1

CH

CL

VLED+

R239

+

R4

C10.1 F

C20.01 F

FLOATINGPOWERSUPPLY

HV+ +

+R1

RSENSE

HV-

MOTOR

D15.1 V

GATE DRIVECIRCUIT

HCPL-788J

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An inexpensive 78L05 three-terminal regulator can alsobe used to reduce the oating supply voltage to 5 V. Tohelp attenuate high-requency power supply noise orripple, a resistor or inductor can be used in series withthe input o the regulator to orm a low-pass flter withthe regulators input bypass capacitor.

As shown in Figure 25, 0.1 F bypass capacitors (C1, C3,

C4, and C6) should be located as close as possible to thepins o the HCPL-788J. The bypass capacitors are requiredbecause o the high-speed digital nature o the signalsinside the HCPL-788J. A 0.01 F bypass capacitor (C2) isalso recommended at the input due to the switched-ca-pacitor nature o the input circuit. The input bypass ca-pacitor also orms part o the anti-aliasing flter, whichis recommended to prevent high-requency noise romaliasing down to lower requencies and interering withthe input signal. The input flter also perorms an impor-tant reliability unction it reduces transient spikesrom ESD events owing through the current sensingresistor.

Figure 27. Example printed circuit board layout.

PC Board Layout

The design o the printed circuit board (PCB) should ol-low good layout practices, such as keeping bypass ca-pacitors close to the supply pins, keeping output signalsaway rom input signals, the use o ground and powerplanes, etc. In addition, the layout o the PCB can also a-ect the isolation transient immunity (CMTI) o the HCPL-

788J, due primarily to stray capacitive coupling betweenthe input and the output circuits. To obtain optimal CMTIperormance, the layout o the PC board should mini-mize any stray coupling by maintaining the maximumpossible distance between the input and output sides othe circuit and ensuring that any ground or power planeon the PC board does not pass directly below or extendmuch wider than the body o the HCPL-788J.

TOP LAYER

BOTTOM LAYER

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Current Sensing Resistors

The current sensing resistor should have low resistance(to minimize power dissipation), low inductance (to min-imize di/dt induced voltage spikes which could adverselyaect operation), and reasonable tolerance (to maintainoverall circuit accuracy). Choosing a particular value orthe resistor is usually a compromise between minimiz-

ing power dissipation and maximizing accuracy. Smallersense resistance decreases power dissipation, while larg-er sense resistance can improve circuit accuracy by utiliz-ing the ull input range o the HCPL-788J.

The frst step in selecting a sense resistor is determin-ing how much current the resistor will be sens ing. Thegraph in Figure 28 shows the rms current in each phaseo a three-phase induction motor as a unction o aver-age motor output power (in horsepower, hp) and motordrive supply voltage. The maximum value o the senseresistor is determined by the current being measuredand the maximum recommended input voltage o the

isolation amplifer. The maximum sense resistance canbe calculated by taking the maximum recommendedinput voltage and dividing by the peak current that thesense resistor should see during normal operation. Forexample, i a motor will have a maximum rms currento 10 A and can experience up to 50% overloads duringnormal operation, then the peak current is 21.1 A (=10x 1.414 x 1.5). Assuming a maximum input voltage o 200mV, the maximum value o sense resistance in this casewould be about 10 m.

The maximum average power dissipation in the senseresistor can also be easily calculated by multiplying the

sense resistance times the square o the maximum rmscurrent, which is about 1 W in the previous example.

I the power dissipation in the sense resistor is toohigh, the resistance can be decreased below themaximum value to decrease power dissipation.

The minimum value o the sense resistor is limited byprecision and accuracy requirements o the design. Asthe resistance value is reduced, the output voltage across

the resistor is also reduced, which means that the osetand noise, which are fxed, become a larger percentageo the signal amplitude. The selected value o the senseresistor will all somewhere between the minimum andmaximum values, depending on the particular require-ments o a specifc design.

When sensing currents large enough to cause signifcantheating o the sense resistor, the temperature coecient(tempco) o the resistor can introduce nonlinearity dueto the signal dependent temperature rise o the resistor.

The eect increases as the resistor-to-ambient thermalresistance increases. This eect can be minimized by

reducing the thermal resistance o the current sens-ing resistor or by using a resistor with a lower tempco.Lowering the thermal resistance can be accomplishedby repositioning the current sensing resistor on the PCboard, by using larger PC board traces to carry awaymore heat, or by using a heat sink.

For a two-terminal current sensing resistor, as the value oresistance decreases, the resistance o the leads becomea signifcant percentage o the total resistance. This hastwo primary eects on resistor accuracy. First, the eec-tive resistance o the sense resistor can become depen-dent on actors such as how long the leads are, how they

are bent, how ar they are inserted into the board, andhow ar solder wicks up the leads during assembly (theseissues will be discussed in more detail shortly). Second,the leads are typically made rom a material, such as cop-per, which has a much higher tempco than the materialrom which the resistive element itsel is made, resultingin a higher tempco overall.

Both o these eects are eliminated when a our-terminalcurrent sensing resistor is used. A our-terminal resistorhas two additional terminals that are Kelvin-connecteddirectly across the resistive element itsel; these two ter-minals are used to monitor the voltage across the resis-

tive element while the other two terminals are used tocarry the load current. Because o the Kelvin connection,any voltage drops across the leads carrying the load cur-rent should have no impact on the measured voltage.

Figure 28. Motor output horsepower vs. motor

phase current and supply voltage.

MOTOR

OUTPUTPOWERHORSEPOWER

00

MOTOR PHASE CURRENT A (rms)

40

5 20 25 35

20

35

30

25

15

10

5

10 15 30

440380220120

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Sense Resistor Connections

The recommended method or connecting theHCPL-788J to the current sensing resistor is shownin Figure 26. V

IN+(pin 1 o the HCPL-788J) is con-

nected to the positive terminal o the sense resis-tor, while V

IN-(pin 2) is shorted to GND

1(pin 8), with

the power-supply return path unctioning as the sense line

to the negative terminal o the current senseresistor. This allows a single pair o wires orPC board traces to connect the HCPL-788J circuit to thesense resistor. By reerencing the input circuit to the neg-ative side o the sense resistor, any load current inducednoise transients on the resistor are seen as a common-mode signal and will not interere with the current-sensesignal. This is important because the large load currentsowing through the motor drive, along with the para-sitic inductances inherent in the wiring o the circuit, cangenerate both noise spikes and osets that are relativelylarge compared to the small voltages that are beingmeasured across the current sensing resistor.

I the same power supply is used both or the gate drive circuitand or the current sensing circuit, it is very importantthat the connection rom GND

1o the HCPL-788J to the

sense resistor be the only return path or supply currentto the gate drive power supply in order to eliminate po-tential ground loop problems. The only direct connec-tion between the HCPL-788J circuit and the gate drivecircuit should be the positive power supply line. Pleasereer to Avago Technologies Applications Note 1078 oradditional inormation on using Isolation Amplifers.

When laying out a PC board or the current sensingresistors, a couple o points should be kept in mind.

The Kelvin connections to the resistor should bebrought together under the body o the resistor andthen run very close to each other to the input o theHCPL-788J; this minimizes the loop area o the con-nection and reduces the possibility o stray magnetic

felds rom interering with the measured signal. Ithe sense resistor is not located on the same PC board asthe HCPL-788J circuit, a tightly twisted pair o wires canaccomplish the same thing.

Also, multiple layers o the PC board can be used toincrease current carrying capacity. Numerous plated-through vias should surround each non-Kelvin terminalo the sense resistor to help distribute the current be-tween the layers o the PC board. The PC board shoulduse 2 or 4 oz. copper or the layers, resulting in a currentcarrying capacity in excess o 20 A. Making the currentcarrying traces on the PC board airly large can also im-prove the sense resistors power dissipation capabilityby acting as a heat sink. Liberal use o vias where theload current enters and exits the PC board is also recom-mended.

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Frequently Asked Questions about the HCPL-788J

1. The Basics

1.1: Why should I use the HCPL-788J or

sensing current when Hall-efect

sensors are available which dont

need an isolated supply voltage?

Historically, motor control current sense designs have required trade-os betweensignal accuracy, response time, and the use o discrete components to detect shortcircuit and overload conditions. The HCPL-788J greatly simplifes current-sense designsby providing an output voltage which can connect directly to an A/D converter as well

as integrated short circuit and overload detection (eliminating the need or externalcircuitry). Available in an auto-insertable, SO-16 package, the HCPL-788J is smallerthan and has better linearity, oset vs. temperature and Common Mode Rejection(CMR) perormance than most Hall-eect sensors.

1.2: What is the purpose o the VREF

input?

The VREF

input establishes the ull scale output range. VREF

can be connected to thesupply voltage (V

DD2) or a voltage between 4 V and V

DD2. The nominal gain o the HCPL-

788J is the output ull scale range divided by 504 mV.

1.3: What is the purpose o the rectied

(ABSVAL) output on pin 13?

When 3 phases are wire-ORed together, the 3 phase AC currents are combined to

orm a DC voltage with very little ripple on it. This can be simply fltered and used

to monitor the motor load. Moderate overload currents which dont trip the FAULT

output can thus be detected easily.

2. Sense Resistor and Input Filter

2.1: Where do I get 10 m resistors? I

have never seen one that low.

Although less common than values above 10 , there are quite a ew manuacturerso resistors suitable or measuring currents up to 50 A when combined with the HCPL-788J. Example product inormation may be ound at Vishays web site (http://www.vishay.com) and Isoteks web site (http://www.isotekcorp.com).

2.2: Should I connect both inputs

across the sense resistor instead o

grounding VIN-

directly to pin 8?

This is not necessary, but it will work. I you do, be sure to use an RC flter on both pin1 (V

IN+) and pin 2 (V

IN-) to limit the input voltage at both pads.

2.3: How can I avoid alse tripping o the

ault output due to cable capacitance

charging transients?

In PWM motor drives there are brie spikes o current owing in the wires leading to

the motor each time a phase voltage is switched between states. The amplitude and

duration o these current spikes is determined by the slew rate o the power transis-

tors and the wiring impedances. To avoid alse tripping o the FAULT output (pin 14)

the HCPL-788J includes a blanking flter. This flter ignores over-range input conditions

shorter than 1 s. For very long motor wires, it may be necessary to increase the time

constant o the input RC antialiasing flter to keep the peak value o the HCPL-788J

inputs below 230 mV. For example, a 39 , 0.047 F RC flter on pin 1 will ensure that

2 s wide 500 mV pulses across the sense resistor do not trip the FAULT output.

2.4: Do I really need an RC lter on the

input? What is it or? Are other values

o R and C okay?

This flter prevents damage rom input spikes which may go beyond the absolutemaximum ratings o the HCPL-788J inputs during ESD and other transient events. Theflter also prevents aliasing o high requency (above 3 MHz) noise at the sampledinput. Other RC values are certainly OK, but should be chosen to prevent the inputvoltage (pin 1) rom exceeding 5 V or any conceivable current waveorm in the senseresistor. Remember to account or inductance o the sense resistor since it is possibleto momentarily have tens o volts across even a 1 m resistor i di/dt is quite large.

2.5: How do I ensure that the HCPL-788Jis not destroyed as a result o short

circuit conditions which cause

voltage drops across the sense

resistor that exceed the ratings o

the HCPL-788Js inputs?

Select the sense resistor so that it will have less than 5 V drop when short circuitsoccur. The only other requirement is to shut down the drive beore the sense resistor isdamaged or its solder joints melt. This ensures that the input o the HCPL-788J cannotbe damaged by sense resistors going open-circuit.

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3. Isolation and Insulation

3.1: How many volts will the HCPL-788J

withstand?

The momentary (1 minute) withstand voltage is 5000 V rms per UL1577 and CSAComponent Acceptance Notice #5.

3.2: What happens i I dont use the

470 pF output capacitors Avago

recommends?

These capacitors are to reduce the narrow output spikes caused by high commonmode slew rates. I your application does not have rapid common mode voltagechanges, these capacitors are not needed.

4. Accuracy

4.1: What is the meaning o the ofset

errors and gain errors in terms o the

output?

For zero input, the output should ideally be 1/2

o VREF

. The nominal slope o the input/output relationship is V

REFdivided by 0.504 V. Oset errors change only the DC input

voltage needed to make the output equal to 1/2

o VREF

. Gain errors change only theslope o the input/output relationship. For example, i V

REFis 4.0 V, the gain should be

7.937 V/V. For zero input, the output should be 2.000 V. Input oset voltage o 3 mVmeans the output voltage will be 2.000 V 0.003*7.937 or 2.000 23.8 mV when theinput is zero. Gain tolerance o 5% means that the slope will be 7.937 0.397. Overthe ull range o 3 mV input oset error and 5% gain error, the output voltage willbe 2.000 25.0 mV when the input is zero.

4.2: Can the signal to noise ratio be

improved?

Yes. Some noise energy exists beyond the 30 kHz bandwidth o the HCPL-788J.An external RC low pass flter can be used to improve the signal to noise ratio. Forexample, a 680 , 4700 pF RC flter will cut the rms output noise roughly by a actoro 2. This flter reduces the -3dB signal bandwidth only by about 10%. In applicationsneeding only a ew kHz bandwidth even better noise perormance can be obtained.The noise spectral density is roughly 400 nV/ Hz below 15 kHz (input reerred). As anexample, a 2 kHz (680 , 0.1 F) RC low pass flter reduces output noise to a typicalvalue o 0.08 mVrms.

4.3: I need 1% tolerance on gain. Does

Avago sell a more precise version?

At present Avago does not have a standard product with tighter gain tolerance. A 100 variable resistor divider can be used to adjust the input voltage at pin 1, i needed.

4.4: The output doesnt go all the way

to VREF

when the input is above ull

scale. Why not?

Op-amps are used to drive VOUT

(pin 12) and ABSVAL (pin 13). These op-amps canswing nearly rom rail to rail when there is no load current. The internal V

DD2is about

100 mV below the external VDD2

. In addition, the pullup and pulldown output tran-sistors are not identical in capability. The net result is that the output can typically

swing to within 20 mV o GND2 and to within 150 mV o VDD2. When VREF is tied toV

DD2, the output cannot reach V

REFexactly. This limitation has no eect on gain only

on maximum output voltage. The output remains linear and accurate or all inputsbetween -200 mV and +200 mV. For the maximum possible swing range, separate V

REF

and VDD2

voltages can be used. Since 5.0 V is normally recommended or VDD2

, use o4.5 V or 4.096 V reerences or V

REFallow the outputs to swing all the way up to V

REF(and

down to typically 20 mV).

4.5: Does the gain change i the internal

LED light output degrades with

time?

No. The LED is used only to transmit a digital pattern. Gain is determined by a bandgapvoltage reerence and the user-provided V

REF. Avago has accounted or LED degrada-

tion in the design o the product to ensure long lie.

4.6: Why is gain dened as VREF

/504 mV,

not VREF

/512 mV as e xpected, based

on Figure 24?

Ideally gain would be VREF

/512 mV, however, due to internal settling characteristics,the average eective value o the internal 256 mV reerence is 252 mV.

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5. Power Supplies and Start-Up

5.1: What are the output voltages beore

the input side power supply is turned

on?

VOUT

(pin 12) is close to zero volts, ABSVAL (pin 13) is close to VREF

and FAULT (pin 14) isin the high (inactive) state when power to the input side is o. In act, a sel test canbe perormed using this inormation. In a motor drive, it is possible to turn o all thepower transistors and thus cause all the sense resistor voltages to be zero. In this case,fnding V

OUTless than 1/

4o V

REF, ABSVAL more than 3/

4o V

REFand FAULT in the high state

indicates that power to the input side is not on.

5.2: How long does the HCPL-788J take

to begin working properly ater

power-up?

About 50 s ater a VDD2

power-up and 100 s ater a VDD1

power-up.

6. Miscellaneous

6.1: How does the HCPL-788J measure

negative signals with only a +5 V

supply?

The inputs have a series resistor or protection against large negative inputs. Normalsignals are no more than 200 mV in amplitude. Such signals do not orward bias anyjunctions suciently to interere with accurate operation o the switched capacitorinput circuit.

6.2: What load capacitance can the HCPL-

788J drive?

Typically, noticeable ringing and overshoot begins or CLOAD

above 0.02 F. Avagorecommends keeping the load capacitance under 5000 pF (at pin 12). ABSVAL (pin13) typically exhibits no instability at any load capacitance, but speed o responsegradually slows above 470 pF load.

6.3: Can I use the HCPL-788J with a

bipolar input A/D converter?

Yes, with a compromise on oset accuracy. One way to do this is by connecting +2.5V to pins 10, 11, and 15 and connecting -2.5 V to pins 9 and 16 with 0.1 F bypasscapacitors rom +2.5 V to -2.5 V and rom -2.5 V to ground. Note that FAULT cannotswing above 2.5 V in this case, so a level shiter may be needed. Alternately, a single 5V supply could be power the HCPL-788J which could drive an op amp confgured tosubtract 1/

2o V

REFrom V

OUT.

For product information and a complete list ofdistributors, please go to our website: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks o fAvago Technologies in the United States and other countries.

Data subject to change. Copyright 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV01-0570EN

AV02-1546EN - February 8, 2010

HCPL-788J

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