HB0764: CoreJTAGDebug v2.0 HandbookHB0764: CoreJTAGDebug v2.0 Handbook Microsemi makes no warranty,...

HB0764

CoreJTAGDebug v2.0 Handbook 03 2017

HB0764: CoreJTAGDebug v2.0 Handbook

Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. About Microsemi Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions; security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 4,800 employees globally. Learn more at www.microsemi.com. ©2017 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.

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50200764 Handbook Revision 1 2

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1 Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

1.1 Revision 1.0 Revision 1.0 is released for CoreJTAGDebug v2.0.



Contents

1 Revision History ........................................................................................................................ 3 1.1 Revision 1.0 ................................................................................................................................................ 3

2 Introduction ............................................................................................................................. 7 2.1 Overview .................................................................................................................................................... 7 2.2 Features ..................................................................................................................................................... 7 2.3 Core Version ............................................................................................................................................... 7 2.4 Supported Families .................................................................................................................................... 7 2.5 Device Utilization and Performance .......................................................................................................... 8

3 Functional Description ............................................................................................................. 9

4 Interface ................................................................................................................................. 12 4.1 Configuration Parameters ........................................................................................................................ 12

4.1.1 Signal Descriptions .................................................................................................................... 12

5 Register Map and Descriptions .............................................................................................. 15

6 Tool Flow ................................................................................................................................ 16 6.1 License ..................................................................................................................................................... 16

6.1.1 RTL ............................................................................................................................................. 16 6.2 SmartDesign ............................................................................................................................................. 16 6.3 Configuring CoreJTAGDebug in SmartDesign ........................................................................................... 17 6.4 Simulation Flows ...................................................................................................................................... 17 6.5 Synthesis in Libero ................................................................................................................................... 17 6.6 Place-and-Route in Libero ........................................................................................................................ 17

7 System Integration ................................................................................................................. 18 7.1 System Level Design ................................................................................................................................. 18

7.1.1 IGLOO2 / RTG4 ........................................................................................................................... 18 7.2 SmartFusion2 ........................................................................................................................................... 18 7.3 Multi-processor Debug Design ................................................................................................................ 19

8 Design Constraints ................................................................................................................. 21



List of Figures

Figure 1 CoreJTAGDebug Block Diagram when IR_CODE = 0x55 .................................................................................. 9 Figure 2 CoreJTAGDebug Block Diagram when 0x59 ≥ IR_CODE ≥ 0x56 ..................................................................... 10 Figure 3 CoreJTAGDebug Multi-Processor Debug Block Diagram ............................................................................... 11 Figure 4 SmartDesign CoreJTAGDebug Instance View (IR_CODE = 0x55) ................................................................... 16 Figure 5 SmartDesign CoreJTAGDebug Instance View (0x59 ≥ IR_CODE ≥ 0x56) ........................................................ 17 Figure 6 Configuring CoreJTAGDebug in SmartDesign ................................................................................................ 17 Figure 7 SmartDesign RTG4/IGLOO2 JTAG Debug Design ........................................................................................... 18 Figure 8 SmartDesign SmartFusion2 JTAG Debug Design ............................................................................................ 19 Figure 9 SmartDesign CoreJTAGDebug Configuration Window .................................................................................. 20



List of Tables

Table 1 Device Utilization and Performance ................................................................................................................. 8 Table 2 CoreJTAGDebug Configuration Options .......................................................................................................... 12 Table 3 CoreJTAGDebug I/O Signals ............................................................................................................................ 12 Table 4 CoreJTAGDebug Multi-processor Debug Instance IR Code Configuration ...................................................... 19



2 Introduction

2.1 Overview CoreJTAGDebug v2.0 facilitates the connection of JTAG (Joint Test Action Group) compatible soft core processors to the JTAG header for debugging. This core facilitates the debugging of up to five soft core processors in a single device.

2.2 Features Following are the key features of CoreJTAGDebug:

• Provides fabric access to the JTAG interface • Configurable IR Code support for JTAG tunneling • Multi-processor debug support

• Promotes separate JTAG output clock for each soft core processor to a low skew clock network • Performs clock gating on JTAG output clock for each soft core processor

2.3 Core Version This Handbook applies to CoreJTAGDebug v2.0.

2.4 Supported Families • PolarFire

• RTG4™ • IGLOO®2 • SmartFusion®2



2.5 Device Utilization and Performance Utilization and performance data is listed in Table 1 for the supported device families. The data listed in this table is indicative only. The overall device utilization and performance of the core is system dependent.

Table 1 Device Utilization and Performance

Family Tiles Utilization

Performance (MHz) Sequential Combinatorial Total Device Total %

PolarFire 16 95 299544 MPF300TS 0.000 50.00

SmartFusion2 16 97 56340 M2S050 0.002 64.16

IGLOO2 16 97 56340 M2GL050 0.002 64.16

RTG4 16 103 151824 RT4G150 0.001 45.58

Note: Data in this table was achieved using the Verilog RTL with typical synthesis and layout settings on -1 parts. Top-level parameters or generics were left at default settings.



3 Functional Description

CoreJTAGDebug utilizes the UJTAG hard macro to provide fabric access to the JTAG interface. The UJTAG hard macro shifts in the JTAG TDI serial data into a shift register and provides the contents of the shift register in parallel form through the uireg[7:0] output. Only one instance of the UJTAG macro is permitted in the fabric.

CoreJTAGDebug contains an instantiation of the uj_jtag module, which implements a JTAG tunnel controller to facilitate JTAG tunneling between a FlashPro programmer and a target softcore processor. A configuration parameter is provided to allow configuration of the IR code used by the tunneling logic. Clock gating is implemented within the uj_jtag module to hold the target clock low when idle.

Figure 1 CoreJTAGDebug Block Diagram when IR_CODE = 0x55

CoreJTAGDebug

UJTAG uj_jtagJTAG (To TAP) JTAG (To Target)

UJT

AG

I/F

To facilitate the debugging of multiple soft core processors inside a single design, multiple instances of this core can be instantiated provided that each CoreJTAGDebug instance has a unique IR code. All instances of CoreJTAGDebug contain an instance of the uj_jtag tunneling logic. Only the instance with an IR code of 0x55 will instantiate the UJTAG macro.



Figure 2 CoreJTAGDebug Block Diagram when 0x59 ≥ IR_CODE ≥ 0x56

CoreJTAGDebug

uj_jtagUJTAG I/F JTAG (To Target)

A CLKINT clock buffer is instantiated on the UDRCK line in the CoreJTAGDebug instance with an IR code of 0x55 to promote the UDRCK clock line to a global low skew resource. A CLKINT buffer is also instantiated on the TGT_TCK line of each CoreJTAGDebug instance. The TGT_TCK output needs to be maintained separately for each CoreJTAGDebug instance as clock gating is performed in the uj_jtag tunneling logic based on the current IR code.

An optional inverter can be placed on the TGT_TRST line within CoreJTAGDebug for connection to a debug target, which expects to be connected to an active-high reset source, assuming that the TRSTB signal incoming from the JTAG TAP is active-low. As inverters are inserted on a per instance basis, the TGT_TRST line is not shared between CoreJTAGDebug instances.

Figure 3 details the block diagram of a system containing multiple CoreJTAGDebug instances in order to debug multiple processors. The CoreJTAGDebug instance with its IR code configured to 0x55 multiplexes the TDO signal (TGT_TDO) from each JTAG target back to the JTAG TAP based on the UDRV_TDO signal for each uj_jtag instance, which is asserted as a result of an IR code match. Notice the existence of one CLKINT buffer per CoreJTAGDebug instance with an additional CLKINT buffer used in the CoreJTAGDebug instance with an IR code of 0x55.



Figure 3 CoreJTAGDebug Multi-Processor Debug Block Diagram

CoreJTAGDebugInstance 0IR_CODE = 0x55





UJTAG

uj_jtag

UTDO

uj_jtag

uj_jtag

uj_jtag

uj_jtag

One-hot2

BCD

TDO

JTAGTAP

JTAGTARGET

0

JTAGTARGET

1

JTAGTARGET

2

JTAGTARGET

3

JTAGTARGET

4UTDODRV_OUT

UTDO_OUT

TGT_TCK

TGT_TDO

UDRCK_INCLKINT

CLKINT

CLKINT

CLKINT

CLKINTCLKINT



4 Interface

4.1 Configuration Parameters Configurable options that apply to CoreJTAGDebug are as shown in Table 2. If a configuration other than the default is required, use the configuration dialog box in SmartDesign to select appropriate values for the configurable options.

Table 2 CoreJTAGDebug Configuration Options

Name Valid Range Default Description

IR_CODE 0x55-0x59 0x55 JTAG IR Code

ACTIVE_HIGH_TGT_RESET 0-1 0 0: TGT_TRST output is directly driven by the active-low URSTB output of the UJTAG macro. 1: TGT_TRST output is an inverted form of the active-low URSTB output of the UJTAG macro.

4.1.1 Signal Descriptions Signal descriptions for CoreJTAGDebug are defined in Table 3.

Table 3 CoreJTAGDebug I/O Signals

Port Name Width Direction Dependency Description

JTAG TAP Ports

TDI 1 In IR_CODE = 0x55 Test Data In. Serial data input from TAP. Must be routed to a top-level port in SmartDesign.

TCK 1 In IR_CODE = 0x55 Test Clock. Clock source to all sequential elements within CoreJTAGDebug. Must be routed to a top-level port in SmartDesign.

TMS 1 In IR_CODE = 0x55 Test Mode Select. Must be routed to a top-level port in SmartDesign.

TDO 1 Out IR_CODE = 0x55 Test Data out. Serial data ouput to TAP. Must be routed to a top-level port in SmartDesign.

TRSTB 1 In IR_CODE = 0x55 Test Reset. Active low reset input from TAP. Must be routed to a top-level port in SmartDesign.

JTAG Target Ports

TGT_TDO 1 In N/A Test data out from the target to TAP. Connect to the target TDO port.

TGT_TCK 1 Out N/A Test Clock output to the target. Gated form of TCK promoted to a global, low skew net internally within CoreJTAGDebug.

TGT_TRST 1 Out N/A Test Reset. Active-high reset output to the target. CoreJTAGDebug allows this line to be an inverted form of TRSTB if the JTAG target expects an active-high reset source.

TGT_TMS 1 Out N/A Test Mode Select output to the target.

TGT_TDI 1 Out N/A Test Data In. Serial data input from the target.



Chain Ports

UDRCAP_IN 1 In 0x59 ≥ IR_CODE ≥ 0x56 UDRCAP input from the CoreJTAGDebug instance with an IR_CODE of 0x55.

UDRSH_IN 1 In 0x59 ≥ IR_CODE ≥ 0x56 UDRSH input from the CoreJTAGDebug instance with an IR_CODE of 0x55.

UDRUPD_IN 1 In 0x59 ≥ IR_CODE ≥ 0x56 UDRUPD input from the CoreJTAGDebug instance with an IR_CODE of 0x55.

UIREG_IN 8 In 0x59 ≥ IR_CODE ≥ 0x56 UIREG input from the CoreJTAGDebug instance with an IR_CODE of 0x55.

URSTB_IN 1 In 0x59 ≥ IR_CODE ≥ 0x56 URSTB input from the CoreJTAGDebug instance with an IR_CODE of 0x55.

UDRCK_IN 1 In 0x59 ≥ IR_CODE ≥ 0x56 UDRCK input from the CoreJTAGDebug instance with an IR_CODE of 0x55.

UTDI_IN 1 In 0x59 ≥ IR_CODE ≥ 0x56 UTDI input from the CoreJTAGDebug instance with an IR_CODE of 0x55.

UTDODRV_x 1 In IR_CODE = 0x55 Enable signal from a CoreJTAGDebug signal with an IR_CODE in the range 0x56-0x59. This signal is used to denote when the JTAG IR code matches with the IR code for the specific CoreJTAGDebug instance, indicating that UTDO is being driven by this CoreJTAGDebug instance.

UTDO_IN_x 1 In IR_CODE = 0x55 UTDO test data input from a CoreJTAGDebug instance with an IR_CODE in the range 0x56-0x59. This signal is only fed back to the JTAG TAP via TDO when the associated UTODRV_x signal is asserted.

UDRCAP_OUT 1 Out IR_CODE = 0x55 Active-high UJTAG macro output indicating that the UJTAG TAP controller FSM is in the Capture_DR state. This signal should be connected to the UDRCAP_IN input of each CoreJTAGDebug instance with an IR_CODE in the range 0x56-0x59.

UDRSH_OUT 1 Out IR_CODE = 0x55 Active-high UJTAG macro output indicating that the UJTAG TAP controller is in the Shift_DR state. This signal should be connected to the UDRSH_IN input of each CoreJTAGDebug instance with an IR_CODE in the range 0x56-0x59.

UDRUPD_OUT 1 Out IR_CODE = 0x55 Active-high UJTAG macro output indicating that the UJTAG TAP controller FSM is in the Update_DR state. This signal should be connected to the UDRUPD_IN input of each CoreJTAGDebug instance with an IR_CODE in the range 0x56-0x59.

UIREG_OUT 8 Out IR_CODE = 0x55 8-bit bus carrying the contents of the TAP controller’s Instruction register. Only instructions in the range 0x55-0x59 shall be supported for CoreJTAGDebug. This signal should be connected to the UIREG_IN input of each CoreJTAGDebug instance with an IR_CODE in the range 0x56-0x59.

URSTB_OUT 1 Out IR_CODE = 0x55 Active-low reset output from UJTAG macro indicating that the TAP controller is in Test-Logic-Reset mode. Asserted at power-up and reset by a power-on reset. This signal should be connected to the URSTB_IN input of each CoreJTAGDebug instance with an IR_CODE in the range 0x56-0x59.



UDRCK_OUT 1 Out IR_CODE = 0x55 Directly connected to JTAG TAP TCK port. This signal

should be connected to the UDRCK_IN input of each CoreJTAGDebug instance with an IR_CODE in the range 0x56-0x59.

UTDI_OUT 1 Out IR_CODE = 0x55 Directly connected to JTAG TAP TDI port. This signal should be connected to the UDRCAP_IN input of each CoreJTAGDebug instance with an IR_CODE in the range 0x56-0x59.

UTDODRV_OUT 1 Out 0x59 ≥ IR_CODE ≥ 0x56 Enable signal for the UTDO_OUT output of this CoreJTAGDebug instance. Asserted when the UIREG_IN IR CODE matches the IR_CODE of this CoreJTAGDebug instance.

UTDO_OUT 1 Out 0x59 ≥ IR_CODE ≥ 0x56 Test data out from the target connected to this CoreJTAGDebug instance. This signal should be connected to the associated input of the CoreJTAGDebug instance with an IR_CODE of 0x55.



5 Register Map and Descriptions

There are no registers for CoreJTAGDebug.



6 Tool Flow

6.1 License A license is not required to use this IP Core with Libero SoC.

6.1.1 RTL Complete RTL code is provided for the core, allowing the core to be instantiated with SmartDesign. Simulation, Synthesis, and Layout can be performed within Libero SoC.

6.2 SmartDesign An example instantiated view of CoreJTAGDebug is as shown in Figure 4.

For more information on using SmartDesign to instantiate and generate cores, refer to the Using DirectCore in Libero® SoC User Guide.

Figure 4 SmartDesign CoreJTAGDebug Instance View (IR_CODE = 0x55)

The Chain input pins have a default tie-off to ground for designs which only contain one CoreJTAGDebug instance. The UTDODRV_x and UTDO_IN_x signals must be connected to the UTDODRV_OUT and UTDO_OUT signals respectively of the associated CoreJTAGDebug instance for designs performing multi-processor debug. Unused UTDODRV_x and UTDO_IN_x signals can be left at the default tie-off if the design contains less than the maximum five CoreJTAGDebug instances.


http://www.microsemi.com/soc/documents/directcore_in_libero_tutorial_ug.pdf

http://www.microsemi.com/soc/documents/directcore_in_libero_tutorial_ug.pdf


Figure 5 SmartDesign CoreJTAGDebug Instance View (0x59 ≥ IR_CODE ≥ 0x56)

6.3 Configuring CoreJTAGDebug in SmartDesign The core can be configured using the configuration GUI within SmartDesign. An example of the GUI for the SmartFusion2 family is shown in Figure 6.

Figure 6 Configuring CoreJTAGDebug in SmartDesign

6.4 Simulation Flows No testbench is provided with CoreJTAGDebug.

The CoreJTAGDebug RTL can be used to simulate the processor executing a program using a standard Lbero generated HDL testbench.

6.5 Synthesis in Libero Click the Synthesis icon in Libero SoC. The Synthesis window displays the Synplicity® project. Set Synplicity to use the Verilog 2001 standard if Verilog is being used. To run Synthesis, select the Run icon.

6.6 Place-and-Route in Libero Click the Layout icon in the Libero SoC to invoke Designer. After synthesis has been completed the Place-and-Route tool can be run.



7 System Integration

7.1 System Level Design

7.1.1 IGLOO2 / RTG4 Figure 7 details the design requirements to perform JTAG debugging of a softcore processor located in fabric from SoftConsole through the JTAG interface for IGLOO2 and RTG4 devices.

Figure 7 SmartDesign RTG4/IGLOO2 JTAG Debug Design

PCB

IGLOO2/RTG4

CoreJTAGDebug

FlashProSystem Controller

JTAG TAP Controller

eNVM/UPROM UJTAG

uj_jtagSoft Processor

JTAGJTAG

10-pin JTAG header

JTAG_SEL

PC

USB JTAG mux

JTAG

7.2 SmartFusion2 Figure 8 details the design requirements to perform JTAG debugging of a softcore processor located in fabric from SoftConsole through the JTAG interface for SmartFusion2 devices.



Figure 8 SmartDesign SmartFusion2 JTAG Debug Design

PCB

SmartFusion2

CoreJTAGDebug

FlashPro System Controller

JTAG TAP Controller

eNVM UJTAG

uj_jtagSoft Processor

Cortex-M3

JTAGJTAG

JTAG TAP Controller

JTAG

JTAG

10-pin JTAG header

20-pin RVIheader

JTAG_SEL

PC

USB

JTAG

FP/RVI_SEL

muxmuxJTAG

JTAG

7.3 Multi-processor Debug Design Table 4 displays a SmartDesign Canvas containing multiple CoreJTAGDebug instances to debug multiple soft core processors. The IR_CODE of the five CoreJTAGDebug instances are as follows:

Table 4 CoreJTAGDebug Multi-processor Debug Instance IR Code Configuration

CoreJTAGDebug Instance Name IR_CODE

COREJTAGDEBUG_0 0x55





The JTAG_TARGET interface of each instance of CoreJTAGDebug provides a native JTAG interface for connection to a target soft core processor’s debug interface.



Figure 9 SmartDesign CoreJTAGDebug Configuration Window



8 Design Constraints

Designs containing CoreJTAGDebug require the application of the following constraints in the design flow to allow timing analysis to be performed on the TCK clock domain.

The procedure for adding the constraints is as follows:

1. If the Enhanced Constraint flow in Libero v11.7 or later is used, double-click Constraints > Manage Constraints in the Design Flow window and click the Timing tab. In the Timing tab of the Constraint Manager window, select New to create a new SDC file, and name it. Design constraints including the clock source constraints can be entered in this blank SDC file. Go to step 3.

2. If the Classic Constraint flow in Libero v11.7 or later is used, right-click Create Constraints > Timing Constraint in the Design Flow window and click Create New Constraint. This creates a new SDC file. The design constraints including the clock source constraints can be entered in this blank SDC file. Go to step 3.

3. Calculate the TCK period and half period. TCK is typically 6 MHz when debugging with FlashPro, with a maximum frequency of 30 MHz supported by FlashPro5. After completion, enter the following constraints in the SDC file:

create_clock -name { TCK } \ -period TCK_PERIOD \ -waveform { 0 TCK_HALF_PERIOD } \ [ get_ports { TCK } ]

For example, the following constraints need to be applied for a design that uses a TCK frequency of 6 MHz:

create_clock -name { TCK } \ -period 166.67 \ -waveform { 0 83.33 } \ [ get_ports { TCK } ]

4. Associate all constraints files with the Synthesis, Place-and-Route and Timing Verification stages in the Constraint Manager > Timing tab by selecting the related check boxes for the SDC files in which the constraints were entered in.


HB0764: CoreJTAGDebug v2.0 HandbookHB0764: CoreJTAGDebug v2.0 Handbook Microsemi makes no warranty,...

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