GaN/Si LED and HEMTs - SEMI.ORGGaN/Si LED and HEMTs ... S.I. SiC GaN Bulk-GaN GaN Silicon GaN 3C SiC...

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GaN/Si LED and HEMTs

Speaker : Rong Xuan

Industrial Technology Research Institute (ITRI)

Electronics and Optoelectronics Research Lab

Opto-electronics Device &System Application Division


Outline

Introduction

GaN/Si LED Technology

GaN/Si HEMTs Technology

Conclusions

2


``

Epiwafer providers

TDI Hitachi Cable NTT Kyma OptoGaN AZZURRO

CREE TDI Hitachi Cable NTT

CREE Hitachi Cable NTT Toyoda Gosei AZZURRO IQE,Kopin Picogiga

Sumitomo SEI Kyma LumiLOG Samsung-corning Hitachi Cable AZZURRO

Nitronex AZZURRO Picogiga IMEC IQE NTT DOWA

Toshiba Ceramic (TOCERA)

BlueGlass

Device maker Lumileds Osram Nichia Toyoda Gosei Velox

CREE Osram

CREE Fujistu RFMD NXP Freescale NEC, TriQuint

Sony Nichia NEC Toyota

Nitronex OKI TriQUINT MicroGaN, ST, IR, Sanken,Fuji GaN system

R&D R&D

Application Blue/white LED, power devices

Blue/white LED

RF devices Blue/violet laser diode, power devices

Power devices ,RF,LED

RF devices Power devices

Blue/white LED

GaN

Sapphire

GaN

n SiC

GaN

S.I. SiC

GaN

Bulk-GaN

GaN

Silicon

GaN

3C SiC GaN

Glass Silicon

Ref.:Website of Yole

Substrates for GaN Epitaxy

GaN template Vendors or Products


4

Why GaN on Si ?

Prospects:

1) Large area and highly qualified wafer available

2) Sophisticated silicon technology available

Micro-machining, Fine lithography

3) Integrated opto-electronic devices possible (Si-photonics)

Difficulties:

1) Large lattice mismatch and different lattice structure

Poor hetero-interface, High density defects

2) Large difference of thermal expansion coefficients

Cracking, Bowing

3) Strong reaction between GaN and Si

Ga and Si meltback etching reaction

How to resolve:

1) Insertion of AlN and/or multilayered buffer layer

2) Selective Area Epitaxy


6”~8” GaN/Si 有效使用面積

1. Investment

♦ Capacity

A = n••r2

A(4“)/A(2“) = 1

=> same capacity

♦ with 3mm edge exclusion

A = n••(r-e)2

A(4“)/A(2“) = 1.14

=> +14% capacity

♦ System investment

$/1.14 = 0.88

=> 88%

56x2” 14x4” 56x2” 8x6” 56x2” 5x8”

1. Investment

♦ Capacity

A = n••r2

A(6“)/A(2“) = 1.29

=> +29% capacity


A = n••(r-e)2

A(6“)/A(2“) = 1.53

=> +53% capacity


$/1.53 = 0.65

=> 65%

1. Investment

♦ Capacity

A = n••r2

A(8“)/A(2“) = 1.43

=> +43% capacity


A = n••(r-e)2

A(8“)/A(2“) = 1.74

=> +74% capacity


$/1.74 = 0.58

=> 58%

2. Running Cost

$/1.14 => 88%

3. Chip Process

Assume 150% processing time of

4“ compared to 2“:

(42/1.5)/(22/1) = 2.7x Throughput

2. Running Cost

$/1.53 => 65%

3. Chip Process



(62/2)/(22/1) = 4.5x Throughput

2. Running Cost

$/1.74 => 58%

3. Chip Process



(82/2.5)/(22/1) = 6.4x Throughput

Ref.:Aixtron


Si (111)

AlN

buffer

un-doped GaN

n-doped GaN

MQWs

p-doped GaN

Full LED

coincidence

n-GaN quality

(002)/(102) of X-ray

350/450 arcsec

n-GaN thickness

> 3 μm

Difference and coincidence for GaN/Si LED & HEMTs

u-GaN thickness > 5 μm

u-GaN quality

(002)/(102) of X-ray

600/1200 arcsec

Issue : quality & n-GaN thickness

Si (111)

AlN

buffer

un-doped GaN

AlGaN (2DEG)

Power device

Issue : u-GaN thickness


Material Thermal

conductivity

(W/cmK)

Thermal ex-

pansion coef-

ficient in-plane

(10-6/K)

Lattice

mismatch

GaN/substrate

(%)

a(Å ) c(Å ) Thermal

mismatch

GaN/substrate

(%)

GaN 3.189 5.189 1.3 5.59 _ _

AlN 3.11 4.98 2.85 4.2 2.4 25

(111)Si 5.431 _

1-1.5 2.59 -16.9 54

Sapphire 4.758 12.991 0.5 7.5 -16 -34

A. Dadgar et al., phys. stat. sol. (c) No. 6, 1583– 1606 (2003)

6H-SiC 3.080 15.12 3.0-3.8 4.2 3.5 25

Challenges of GaN/Si Epitaxy

7


8

In-Situ curvature measurement system

Reasons for wafer curvatures

1.Vertical temperature gradient :

2. Lattice mismatch :

3. Thermal stress

0

200

400

600

800

1000

1200

1400

-100

-50

0

50

100

150

200

0 1 104

2 104

3 104

T

curvature middle

Time (s)

Gro

wth

te

mp

era

ture

(C̊

)

Curv

atu

re (1

/km

)


9

6 inch GaN on Si

Si

AlN

SL03

AIX CRIUS I MOCVD

GaN template on Si Substrate

SL01

SL02

GaN

LED structure

same as on

sapphire

-150

-100

-50

0

50

100

150

0 5000 1 104

1.5 104

2 104

Process time (s)

Curv

atu

re (

1/K

m-1

)

50X

50X

GaN on Si without island structure

GaN on Si with island structure

In-situ curvature meansurement & top view of OM pictures

Crack surface

Crack free

-150

-100

-50

0

50

100

150

0 5000 1 104

1.5 104

2 104

Process time (s)

Curv

atu

re (

1/K

m-1

)

50X

50X

GaN on Si without island structure

GaN on Si with island structure

In-situ curvature meansurement & top view of OM pictures

Crack surface

Crack free


10

Base on Aixtron Crius 1 Supporting

Insitu monitor is needed for GaN/Si epitaxy


GaN/Si LED Technology

11


Issues of GaN LED on Si substrate

1. Wafer bow & Epi-file crack

2. Epitaxy quality of GaN layer

3. Surface morphology of GaN template

4. Luminescence property (IQE)of active region

5. Electrical property of GaN LED on Si substrate

6. Reliability


GaN/Si Stress Engineering Solutions

Crack surface of GaN/Si

Crack and pits free of GaN/Si

Si substrate

A: Selective area growth

1.Pattern Sub.

2. Rod growth(ITRI’s patents)

3. Elog

4. porous Si substrates or

B: Strain release on blank Sub.

Nucleation 1. Al pre-deposition

Compositional

graded layer

1. AlGaN linear or step graded layer

2. AlGaN/GaN SLs

3. InAlGaN quarternary graded layer

Inter-layer

1. LT-AlN

2. SixNx

3. LT-GaN nucleation

13

Aixtron Crius 1


TMAl pre-deposition 20 sec .

1100oC

Temp

time

AlN

N.L. AlGaN / GaN

TMA pre-deposition for GaN/Si Growth

NH3

TMAl

TMGa

1000 sccm

2500 sccm

20 sccm

20 sccm

Reactor : AIX 2000

H2固定15000sccm

1. Prevent SixNy formation

2. Prevent meltback etching reaction between Ga and Si

14


15

AlN nucleation

AlGaN SLs

In-Situ SiN mask

n+GaN

n+GaN

n+GaN

p-GaN/MQW

AlN/AlGaN interlayer

AlN/AlGaN interlayer

Single SiN layer Double SiN layer

In-Situ SiN mask

In-Situ SiN mask

3.3 um AlGaN

1.7 um n-GaN

By using in-situ SiNx layer can suppress the dislocation punch through active region

TEM cross-section image of GaN/Si epitaxy

Aixtron Crius 1


GaN template quality on 6 inch Si Sub.

0.0 0.4 0.8 1.2 1.6 2.00

200

400

600

800

1000

1200

1400

1600

1800

2000

X-r

ay F

WH

M o

f (1

02

) (a

rcse

c)

GaN thickness (m)

AlGaN buffer 3.3um

AlGaN buffer 2.5um


17

1. Quality調整 :

002 = 395 arcsec 102 = 466 arcsec

OM : 20X

RMS = 0.226 nm

=> Quality is almost the same with that on Al2O3.

PS : world record is 350 for (002) and 430 for (102)

2. n-GaN growth :

4.2 μm including

2.5 μm n-GaN n-GaN 2.5 um

(~2.5E18 cm-3)

GaN/Si LED testing


18

Relationship between Epi-thickness & wafer bow

-150

-100

-50

0

50

100

0 5000 1 104

1.5 104

2 104

Growth time (s)

Cu

rvatu

re (

km

-1)

650 um thick substrate

0

0.05

0.1

0.15

0.2

0.25

0.3

0 5000 1 104

1.5 104

2 104

Growth time (s)

Re

fle

cta

nce

(a

. u

. )

650 nm light source

Sample A epi-thickness 2.2 um

Sample B epi-thickness 2.7 um

Sample C epi-thickness 3.6 um

Reflectance of sample C

It can be calculated the curvature

change about 51 km -1 /um(epi-

growth) during the cooling down


19

In-situ reflection & curvature measurement

6inch-SL-20 LED 03

6inch-SL-22 LED 04

6inch-SL-22 LED 05

6inch-SL-22 LED 06

0

500

1000

1500

2000

2500

3000

3500

4000

350 400 450 500 550

Wavelength (nm)

EL

in

ten

sit

y

6inch-SL-20 LED 03

6inch-SL-22 LED 03

6inch-SL-22 LED 04 (SiNx)

6inch-SL-22 LED 06 (SiNx)

In-situ curvature

Less compress stress


RMS and topography 3D profile

AFM inspection result

Area RMS ~0.226nm

Avg. Height ~1.746nm

6”GaN/Si LED testing (1)


21


0

1000

2000

3000

4000

5000

8.55 104

8.65 104

8.75 104

8.85 104

position (arcsec)

X-r

ay

co

un

ts (

a.

u.)

(102)

FWHM ~ 430 arcsec


22

0

500

1000

1500

2000

2500

3000

3500

4000

350 400 450 500 550

Wavelength (nm)

EL in

ten

sity (

a. u

.)

EL test & device process

LED on sapphire

FWHM ~ 19 nm

LED on Si (SL-

18-LED01)

FWHM ~21 nm

OM picture of LED on Si (after ITO & mesa etch )

6 inch-SL-18-LED 01



23

I-V test data on thin GaNLEDs

Sample ID Vf1

(20mA)

Wdd

(20mA)

Wpd

(20mA)

HWFM

(20mA)

Po1 mW

(20mA)

Vf2

(100 mA)

Po2

mW(100mA)

Ir -5V

(uA)

Normal sapphire

with mirror coating

at back side 3.089 455.35 448.56 19.6 6.91 3.738 28.14 0.0035

6inch-Si LED

Before Si removed 2.968 459.02 454.55 19.1 2.0003 3.649 8.8998 0.003

6inch-Si LED

after Si removed 2.932 456.4 451.3 18.6 7.05 3.59 28.93 0.005

Х 3.5 after Si removed

Light out put power increased by 3.5 times at 20 mA current

injection after Si substrate remove.

COW test


24

GaN/Si HEMTs Technology


Fuji Electric Scenario for Application of WBG Device

Source: Fuji 2010 25


26

Main Applications Accessible to WBG

Specs/market data of today silicon devices

Power Supplies/

PFCUPS HEV Solar panel Wind turbine

Industry

Motor

Drive

Energy

Transport.

Grid, Rail

Main DevicesMOSFET

Diodes

MOSFET

IGBT

Diodes

MOSFET

IGBT

Diodes

IGBT

Diodes

IGBT

Diodes

IGBT

Diodes

GTO, Thyristor

IGBT, PiN Diode

Breakdown

Voltage (V)600V 600/1200V

650V→ 900V

>1.2kv

600V (90%)

1200V (10%)

Today 690V

Trend: 3 -4 KV600V to 1200V > 5KV

Peak current (A)

(for a single chip)0.5 - 10A 2 -100A 50-200A 75A 150A 3 - 100A 10 - 200 A

2008 volume (Munits)MOS: 1600

Diode:1600

IGBT:800

Diode: 800

IGBT:2.6

Diode: 2.6

IGBT:12

Diode: 12

IGBT:0.11

Diode: 0.11

IGBT:25

Diode: 25

wide reange of

specs/prices

2008 ASP for a

discrete device

Tr: $0.6 - $1

Diode: $0.3

Tr: $1.2

Diode: $0.6

Tr: $9

Diode: $5

Tr: $8

Diode: $4

Tr: $20

Diode: $8

Tr: $8

Diode: $4

wide reange of

specs/prices

2008 Si device

market ($M)

(discrete)

1800 1400 ~ 40 150 < 3 ~300 ~110

Source: Yole Development


27

Power Devices Vendors or Products

Source: Gartner, Yano Research: IEK/ITRI (2010/10)

Power Devices Vendors and Products (1/2)

Toshiba

STMicroelectronics

Infineon

Fairchild

Vishay

Mitsubishi Electric

International Rectifier (IR)

ON Semiconductor

Fuji Electric

NEC Electronics

Shindengen Electric

Rohm

Renesas Technology

Panasonic

Microsemi

NXP

Sanken

Hitachi

Diodes

Toyota

3C 工業/航太/醫療/軍用車用3C,家電用工業,醫療,航太,軍用車用

Source: Gartner; Yano Research; IEK/ITRI (2010/10)


Comparison of Si / SiC / GaN

Breakdown

Electric Field

(MV/cm)

1

3

5

Thermal

Conductivity

(W/cm °C)

Melting Point

(°C)

Saturation Electron

Velocity ( x107 cm/s)

Energy Gap

(eV)

1K

3K

5K

1

3

5

1

3 5

1

3

5 Si

SiC

GaN

Low Loss: x100

High Voltage: x10 Numbers Compared

between SiC & Si

Radiation: x3

High Frequency: x10

High Temperature: x3

Endurable for Radioactivity: x3

Blue LED Substrate

Automobile Parts

Heating Elements

Structural Materials

…

Power Devices

for Invertors / Converters

in EV/HEV, Renewable

Energy Systems

(PV, Wind Turbid,…)

RF & Microwave

Components

Source: IEK/ITRI (2010/07)

-- Characteristics and Applications

28


Breakdown Voltage of Different Epi-structure (1)

29


2-20um 2-30um

Ron(mΩ-cm2)@Vg=0V 13.90 15.58

Breakdown Voltage

(V)@100uA 855 863

Vth(V) -2 -2

gm (mS/mm) 55 62

Ids (mA/mm) @Vg=1V 160 156

GaN/Si HEMTs Device Performance

30

0 100 200 300 400 500 600 700 800 900 100010

-5

10-4

10-3

10-2

10-1

100

Breakdown Voltage

Ids (

mA

/mm

)

Vds (V)

without C-doped

C-doped

Vgs=-5V

Thickness: 3.9 μm

Mobility: 1100 (cm2/Vs)

Concen.: -1.41E13 cm-2

Rsh: 400 (ohm/sq)

XRD: (002)/(102) = (539.4)/(1078)


Surfa

ce state

s

AlGaN Barrier Layer Structure

31

R.J. Trew. In: Int. Semicond. Dev. Res. Symp. (Dec. 5–7,2001) p. 432.

Appl. Phys. Lett, vol. 85, pp. 6164-6166, 2004.


AlGaN Barrier Layer Growth on Si

單層的Al0.3Ga0.7N有較高的導通電流，雙層的Al0.38Ga0.62N/ Al0.24Ga0.66N barrier

layer則得到較高的Sheet Concentration與較低的導通電阻。

32


33

國際技術 Normally-off GaN HEMT Device

Recessed gate [Dry etch]

[ Sharp] MOS-HEMT [ Fujitsu] MIS-HEMT

•分析說明

-閘極蝕刻凹槽(gate trench)

GaN/oxide介面產生很多缺陷，

影響channel mobility

-蝕刻深度控制不易，造成

Threshold Voltage fluctuations

Without Recessed gate

[ Panasonic] P-AlGaN GATE [ Hong Kong University] F-ion HEMT

•分析說明

- 磊晶成長p-AlGaN可能造成

Doping原子擴散至2-DEG channel

- p-AlGaN濃度提昇不易,影響

Threshold Voltage

- 大電流操作下,F-ion HEMT可能有

reliability的問題

Vth(v) 5.2

Id (mA/mm) 200

Vbd(v) 400

Ron(mΩ-cm2) 2.6

Vth(v) 3

Id (mA/mm) 800

Vbd(v) 320

Ron(mΩ-cm2) ?

Vth(v) 1

Id (mA/mm) 200

Vbd(v) 800

Ron(mΩ-cm2) 2.6

Vth(v) 0.75

Id (mA/mm) 300

Vbd(v) ?

Ron(mΩ-cm2) ?


Bottleneck of MIS HEMTs

SF6

Substrate

u-GaN:1.5um

U-Al0.25Ga0.75N; 20nm u-GaN:1nm

SiO2:300nm

u-GaN:1nm

SF6- 3/5/7min

- Ids與Vth的相關性

-2.0 -1.5 -1.0 -0.5 0.0 0.5

0

20

40

60

80

100

120

140

160

180

200

220

240

Vth (v)

Id (

mA

/mm

)

0

500

1000

1500

2000

2500

3000

VB

D (

v)

0 min.

3 min.

5 min.

7 min. △Vth=2 v

△Ids=-110mA/mm

34

臨界電壓從-1.8 V提升至+0.2 V，導通電流下降58%。


奈米膠

SiO2 mask 奈米壓印圖案

SiO2 pattern by RIE

Rod:

Pitch 750 nm

Fill factor 1:1

Nano-rod Fabrication

35

550umX550um


I-V Testing Results

利用nano rod製作在閘極區域下方，臨界電壓從-2 V提升至+2 V，導通電流下降34%。

可維持與D-mode HEMTs相同的崩潰電壓~860V 36

Vds=10V Vds=10V

Ioff=3.31mA/mm Ioff=0.02mA/mm


Sample Resistivity

(Ω∙cm)

Carrier concentration

(cm-3)

Mobility

(cm2V-1sec-1)

NiO

(100% of O2) 6.1 x 10-2 2.23 x 1019 4

Characteristics of P+-NiOx coated by Sputter

glass Substrate

NiO film

(100 nm)

2’’ Target Power

(w)

Ar:O2 flow rate

(sccm)

temperature

NiO 80 0:16 RT

_Condition:

_Hall measurement:

NiOx Insulation layer

NiOX條件:

Ni(25nm)/O2(9sccm)/T(250℃)/RTP(N2/O2) 500℃ ,1min


HEMT Device (Nano-pattern P+-NiOx gate) -1

Recessed gate Recessed gate

(nano-pattern)

NiOx P+-NiOx NiOx P+-NiOx

Vth (V) - 0.6 2.3 0.2 2.2

△Id↓% 8.4 20 15.7 36

Vbd (V) 2236 2328 2335 1986

Ion/Ioff 3.5E7 3E7 6.1E6 1.5E8

S.S(mV/dec) 80.14 252 105.21 84

_ Overview

Si (111)

buffer

u-GaN

S D /SiNx/SiO2 u-AlGaN

G

NiOx layers

Si (111)

buffer

u-GaN

S

G

D

u-AlGaN

NiOx SiN/SiO2

Recessed gate Recessed gate (nano-pattern)


-4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 100

50

100

150

200

250

300

350

400

450 STD

Porous-450-MIS-P+-NiOx

Rods-750-MIS-P+-NiOx


DOWA-36 nano-pattern-MIS-P+-NiOx

Transfer I-V Characteristic of GaN HEMT

Vgs(V)

Id(m

A/m

m)

△Id:↓36%

-5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 100

5

10

15

20

25

30

35

40

45

50 STD

Porous-450-MIS-P+-NiOx



DOWA-36 nano-pattern-MIS-P+-NiOx

Transfer I-V Characteristic of GaN HEMT

Vgs(V)

Id(m

A/m

m)

△Vth:4.2V

•比較△Vth &△ Ids(max.)變化:

DOWA-36 Vth Id(max) △Vth △Id(max)

STD -2.0 418

Pitch 350 nm; Fill factor 1/1

MIS-Structure- P+-NiOx:100nm 2.2 266 4.2 36.4%


MIS-Structure- P+-NiOx:100nm 3.2 63 5.2 84.9%


MIS-Structure- P+-NiOx:100nm 3.2 8.6 5.2 97.9%

HEMT Device (Nanos-pattern P+-NiOx gate) -2


Ids improvement

( AlGaN barrier structure)

BV improvement

( Carbon doped)

Normally-on

GaN HEMT Device

Ig leakage suppressed

( NiOx applied)

Normally-off

GaN HEMT Device Ids improvement

(Nano-pattern applied)

GaN/Si HEMTs Conclusions

40

GaN/Si epi quality improvement

(linear graded AlGaN buffer layer)


Summary

• GaN/Si磊晶技術關鍵在應力控制，ITRI以nano Rod、

SixNyCz、Mg/In-Si co-doped等緩衝層技術以獲得高品

質的厚GaN on 6” Si，已做整體利佈局。

• 利用前述自有磊晶技術，結合特殊製程，開發 6” GaN/Si

LED發光效率接近GaN/Sapp LED 。

• 利用nano rod+ NiOx製作E-mode GaN/Si HEMT，達崩

潰電壓 ~900V ; Vt ≧ 2 技術水準。

• 降低LED生產成本 : 若在成本低廉的6吋以上矽晶圓生成

氮化鎵，並採用與現代半導體生產線相容的製程，則晶

粒成本會比現有製程有效降低75% ，利於產業切入照明

等應用。

• 加速產業轉型 : 整合與鏈結國內光電與半導體廠的專長

與資源，切入GaN電子元件的高單價產品技術。

GaN epitaxy

on 6” Si substrate

GaN/Si HEMTs

GaN/Si LED


42

End


Wafer size Epi-thickness BOW Carrier

density

Channel

mobility

Sheet

resistance

IMEC • 8-inch • Crack free < 50 μm

6-inch

272+-5 Ω/sq

AZZURRO • 6-inch > 6 μm 15 μm

DOWA • 6-inch

> 5 μm 7.4 μm 6x1012/cm2 1500 cm2/V-s 600 Ω/sq

NTT • 6-inch > 5 μm 34 μm ? 2180 cm2/V-s

440 Ω/sq

IEMN •4-inch 2x1013/cm2 1400 cm2/V-s 235 Ω/sq

ITRI • 6-inch > 4 μm ? 1.5x1013/cm2 1200 cm2/V-s 400 Ω/sq

Benchmark of power device of GaN on Si

Key issue : How to increase the GaN thickness on large scale Si substrate ?

=> stress engineering, then in-situ stress monitoring ！


Surfa

ce state

s

GaN HEMTs Advantages

44

“A 3–10-GHz GaN-Based Flip-Chip Integrated Broad-Band Power Amplifier,” IEEE Transactions on Microwave Theory

and Techniques,vol. 48, pp. 3573-2578, 2000.


0 1 2 3 4 5 6 7 8 9 100

20

40

60

80

100

120

140

160

180

200

Passivation:NiOx

Ni(50nm)/O2(5sccm)/non-RTP

Passivation:SiO2/SiNx

40%

Vg:1V

Lch

:2um

Lg-d

:20um

Ids (

mA

/mm

)

Vds(V)

0 500 1000 1500 2000 2500 3000

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

0.01

0.1

1

Cu

rren

t (m

A)

Voltage(V)

2-20um-passivation SiO2/SiNx

2-30um-passivation SiO2/SiNx

2-20um-Passivation NiOx

2-30um-Passivation NiOx

NiOx as passivation具 depletion 效果(40%)與Leakage current 下降1E-4

NiOX G S

Substrate

u-GaN:1.5um

U-Al0.25GaN; 20nm u-GaN:1nm

D NiOX

•Mesa

•Ti(100nm)/Al(300nm)/RTP

•NiOx:Ni(50nm)/O2(5sccm)

Lift off-non RTP

NiOx Insulation layer of HEMTs

45

DOWA’s epi wafer


Epitaxial relationship of GaN(001) on Si(111)

46


GaN/Si HEMTs Epi-structure Quality

47

U-Si

AlN (100nm)

GaN (1.5 µm)

AlGaN graded layer

with C-doped (2.5um)

Al0.25Ga0.75N (25 nm)

GaN/Si LED and HEMTs - SEMI.ORGGaN/Si LED and HEMTs ... S.I. SiC GaN Bulk-GaN GaN Silicon GaN 3C SiC...

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