Finite Aperture Time Effects in Sampling Circuit14/34 Derived Transfer Function Transfer function in...

群馬大学小林研究室

Gunma University Kobayashi Lab

Finite Aperture Time Effects in Sampling Circuit

M. Arai I. Shimizu H. Kobayashi K. Kurihara S. Sasaki S. Shibuya

K. Niitsu K. Kubo

Gunma University

Nagoya University

Oyama National College of Technology

C2-4 16:45-17:00 Nov. 4, 2015 (Wed)

http://www.google.co.jp/url?sa=i&rct=j&q=&esrc=s&source=images&cd=&cad=rja&uact=8&docid=XxicGsaDCzsPuM&tbnid=2cjxvii7O6Y6aM:&ved=0CAcQjRw&url=http://sophie-in-tokio.blogspot.com/2010/01/owari.html&ei=S7I5VOTZIYSa8QXs8oHQCQ&bvm=bv.77161500,d.dGc&psig=AFQjCNHYkkS5Xy28Z2VuOcAl2KzQaLEzPA&ust=1413153670218700

Contents

● Research Objective ● Waveform Sampling and Sampling Circuit ● Finite Aperture Time - Problem Formulation - Formula Derivation - Effective Finite Aperture Time ● Uncertainty Relationship in Sampling Circuit ● Summary 2/34

Contents

● Research Objective ● Waveform Sampling and sampling Circuit ● Finite Aperture Time - Problem Formulation - Formula Derivation - Effective Finite Aperture Time ● Uncertainty Relationship ● Summary 3/34

Research Objective

● To establish fundamental theory of sampling circuit for high-frequency and high-precision waveform acquisition ● Especially, to clarify finite aperture time effect.

4/34

Contents

● Research Objective ● Waveform Sampling and Sampling Circuit ● Finite Aperture Time - Problem Formulation - Formula Derivation - Effective Finite Aperture Time ● Uncertainty Relationship ● Summary 5/34

Waveform Sampling

Waveform acquisition Sampling High-frequency signal sampling - Finite aperture time (non-zero turn-off time) - Aperture jitter

time

― analog signal

● Sampled point

Ts = 1 / fs

suffers from

volt

age

6/34

Sampling Circuit

7

時間

電圧

時間

電圧

時間

電圧

時間

電圧

CSW

Vin Vout

CSW

Vin Vout

CSW

Vin Vout

• SW: ON

•Vout(t) = Vin(t)

Track mode

•SW: OFF

•Vout(t) = Vin(tOFF)

Hold mode

Track Hold

time

time

time time

volt

age

volt

age

volt

age

vo

ltag

e

7/34

Contents

● Research Objective ● Waveform Sampling ● Finite Aperture Time - Problem Formulation - Formula Derivation - Effective Finite Aperture Time ● Uncertainty Relationship ● Summary 8/34

Finite Aperture Time

9

時間

電圧

時間

電圧

CSW

Vin Vout

CSW

Vin Vout

• SW: ON

•Vout(t) = Vin(t)

Track mode

•SW: OFF


Hold mode time

time

volt

age

vo

ltag

e

Finite transition time from track to hold modes

9/34

Analogy with Camera Shutter Speed

Camera: Finite Shutter Speed Sampling Circuit: Finite Aperture Time

Moving Object

Blurred

Input signal

Acquired signal

High frequency

Low pass filtered

10/34

Signal Frequency and Aperture Time

Higher frequency signal ⇒ More affected by finite aperture time

Ｈ T

time

time

Low frequency

Aperture time

Ｈ T

time

time

High frequency

Aperture time

Inp

ut

volt

age

Inp

ut

volt

age

Ou

tpu

t vo

ltag

e

Ou

tpu

t vo

ltag

e

11/34

Contents


VgVinVc

Transfer Function Derivation

Track Hold Circuit

+

-

Voltage

Time

Obtain values of ●

Equivalent time sampling

Obtain gain, phase for each frequency Frequency transfer function

SW

13/34

Contents


Derived Transfer Function

Transfer function in case of finite aperture time

Track Hold Circuit

+

-

SW

τ1 = R C

[1] A. Abidi, M. Arai, K. Niitsu, H. Kobayashi, “Finite Aperture Time Effects in Sampling Circuits,” 24th IEICE Workshop on Circuits and Systems, Awaji Island, Japan (Aug. 2011)

The formula derivation was done by Prof. Asad Abidi.

15/34

Consistency with Zero Aperture Time Case

Transfer function in case of finite aperture time

Transfer function in case of zero aperture time

16/34

τ1, τ2 Effects to Bandwidth

τ1 (= R C) τ2 (aperture time) : varied

: fixed

Bandwidth starts to decrease at τ2 / τ1= 1

τ1, τ2 effects to bandwidth are comparable.

Numerical calculation from the derived transfer function

17/34

Contents


VgVinVc

SPICE Simulation Verification

Track Hold Circuit

+

-

Voltage

Time

Obtain values of ●

Equivalent time sampling

Obtain gain, phase for each frequency Frequency transfer function

19/34

00.50.711.5234567

τ2[ns]0351015202530354050

τ2[ns]

SPICE Simulation Conditions

Results

SPICE Simulation Results

Gai

n [

dB

]

ω [rad/s]

Theory (Derived Transfer Function)

ω [rad/s]

Gai

n [

dB

]

Results

+

―

TSMC 0.18um

20/34

simulationtheory

Comparison of -3dB Bandwidth

W=20um

ω(-

3d

B)[

rad

/s]

14

12

0

2

4

6

8

10

0 5 15 10 τ2[ns]

simulationtheory

W=200um

ω(-

3d

B)[

rad

/s]

20

16

0

4

8

12

τ2[ns] 0 10 50 40 20 30

ω(-

3d

B)[

rad

/s]

simulationtheory

W=2um

τ2[ns] 0 10 50 40 20 30

35

30

0

5

10

15

20

25

Large discrepancies !

21/34

NMOS ON-Conductance Nonlinearity

Effective aperture time

W=20um

1/R

on

[S]

4

3

0

1

2

Vg[V] 0 0.5 2.0 1.0 1.5

W=2um

1/R

on

[S]

4

3

0

1

2

Vg[V] 0 0.5 2.0 1.0 1.5

W=200um

1/R

on

[S]

4

3

0

1

2

Vg[V] 0 0.5 2.0 1.0 1.5

○ region

Strong nonlinearity of 1/Ron

Define effective aperture time

22/34

ON-Conductance and Effective Aperture Time

Region Effective aperture time

1/R

on

(lo

g sc

ale

) [S

]

Vg [V]

200um

20um

2um

23/34

Empirical Effective Aperture Time Derivation

B A

0.43

Vg[V] 0 0.5 2.0 1.0 1.5

1/R

on

(lo

g sc

ale

) [S

]

20um

24/34

simulation*0.44/1.8theory

ω(-

3d

B)[

rad

/s]

τ2[ns]

20

0

5

10

15

0 5 15 10 τ2[ns]

ω(-

3d

B)[

rad

/s]

14 12

0 2 4 6 8

10

0 5 15 10 τ2[ns]

ω(-

3d

B)[

rad

/s]

35 30

0 5

10 15 20 25

0 5 15 10



simulationtheory

simulationtheory

simulationtheory

Discussion Again W=20um W=2um W=200um

τ2[ns]

ω(-

3d

B)[

rad

/s]

20

0

5

10

15

0 20 40 30 10

X 0.44/1.8 X 0.37/1.8 X 0.43/1.8

0 5 15 10

ω(-

3d

B)[

rad

/s]

14 12

0 2 4 6 8

10

τ2[ns]

ω(-

3d

B)[

rad

/s]

35 30

0 5

10 15 20 25

τ2[ns] 0 20 40 30 10

25/34





Various Values for RC, W

200um 20um

20um 2um

R=50Ω, C=10pF

R=50Ω, C=0.1pF

τ2[ns]

ω(-

3d

B)[

rad

/s]

20

0

5

10

15

0 4 10 6 2 8

ω(-

3d

B)[

rad

/s]

15

0

5

10

τ2[ns] 0 5 15 10

τ2[ns]

ω(-

3d

B)[

rad

/s]

15

0

5

10

0 0.5 1.5 1.0 τ2[ns]

ω(-

3d

B)[

rad

/s]

35 30

0 5

10 15 20 25

0 0.5 1.5 1.0

26/34

Contents

● Research Objective ● Waveform Sampling and Sampling Circuit ● Finite Aperture Time - Problem Formulation - Formula Derivation - Effective Finite Aperture Time ● Uncertainty Relationship in Sampling Circuit ● Summary 27/34

Trade-off of Time Constant and Bandwidth

Time

Short

Long

Wide

Narrow

Aperture time Bandwidth

RC time constant and bandwidth Aperture time and bandwidth

Band

RC bandwidth

28/34

-3dB Bandwidth

aperture time

In case of -3dB bandwidth

Transfer function

29/34

Uncertainty Relationship

2 4 6 8 10

2.0

1.5

1.0

0.5

0.5

1.0

Taylor expansion of Sinc function

Uncertainty Relationship Formula

bandwidth RC time constant

aperture time 30/34

Uncertainty Principle and Relationship

● Uncertainty Principle - Quantum mechanics

● Uncertainty Relationship - Sampling circuit

Can NOT be proved

Can be proved

Impossible to know exactly and simultaneously - Where the object is - How fast it is moving

Prof. W. K. Heisenberg

31/34

Contents


Summary

● Derived explicit transfer function of sampling circuit with finite aperture time effect. ● Verified it with SPICE simulation ● Introduced concept of effective finite aperture time ● Showed uncertainty relationship between time constants and bandwidth in sampling circuit. 33/34

Thank you for your kind attention

謝謝

34/34

Kobayashi Lab.

Gunma University

Frequency Estimation Sampling Circuit

Using Analog Hilbert Filter

and Residue Number System

Yudai Abe, Shogo Katayama, Congbing Li,

Anna Kuwana, Haruo Kobayashi

Division of Electronics and Informatics

Gunma University

2019 13th IEEE International Conference on ASIC

A2-5 17:09 Xi’ An + Dalian Room October 30, 2019

2/25

OUTLINE

1. Research Background and Goal

2. Chinese Remainder Theorem

3. Proposed Waveform Sampling Circuit

4. Simulation Verification

5. Summary and Challenge

3/25

OUTLINE






4/25

Research Background

Next Generation Communication System “5G”

High frequencies

in communication systems

Electronic components

for high frequency bands

Communication speed

1980 1990 2000 2010 2020

1G2G

3G

3.5G

3.9G

4G

5G

2.4kbps

Higher than 10Gbps

5/25

Our Research Goal

High-frequency sampling circuit is difficult to realize

Sampling high frequency signal with multiple low frequency clocks

Use Aliasing proactively

Estimate high-frequency input signal

with multiple low-frequency clock sampling circuits

Analog Hilbert filter and residue number system

Our Approach :

6/25

OUTLINE






7/25

Chinese Remainder Theorem

Chinese arithmetic book ‘Sun Tzu calculation’

Generalization

Chinese Remainder Theorem

Answer 23

Sun Tzu calculation

Sun Tzu

“When dividing by 3, its residue is 2,

dividing by 5, its residue is 3,

dividing by 7,its residue is 2.

What is the original number ?”

孫子算経

8/25

How to use the Chinese remainder theorem

Sun Tzu

“How many soldiers are there?”

He used to quickly find out how many soldiers there are.

・・・

“Divide into 3 people.”

9/25


Sun Tzu


・・・

Remainder : 2



10/25


・・・

Remainder : 3Sun Tzu




11/25

“There are 23 people in all.”


・・・

Sun Tzu



Remainder : 2

12/25

Example of Residue Number System

Residue number system

• Natural numbers

3, 5, 7 (relatively prime)

N=3×5×7=105

• k ( 0

13/25

OUTLINE






14/25

Aliasing Phenomenon

A

t

Waveform frequency : 31kHz

f7kHz

𝐀𝟐

𝟐

1kHz 4kHz 8kHz

Sampling frequency : 8 kHz

Spectrums are folded

within the sampling frequency band

( sampling theorem )

Residue frequency

( 7 is the remainder of 31 divided by 8 )

FFT

15/25

Complex FFT of 𝑗 × sin 2𝜋𝑓𝑖𝑛𝑡

f7kHz1kHz 4kHz 8kHz

f7kHz

1kHz

4kHz 8kHz

InvertResidue

frequency

Complex FFT

Input frequency : 31 kHz


cosሺ2𝜋𝑓𝑖𝑛𝑡) 𝑗 × sin 2𝜋𝑓𝑖𝑛𝑡

Inverted spectrum

anti-symmetric at Nyquist frequency

16/25

Complex FFT of cosሺ2𝜋𝑓𝑖𝑛𝑡) + 𝑗 × sin 2𝜋𝑓𝑖𝑛𝑡

f7kHz

1kHz

4kHz 8kHz

InvertResidue

frequency

f7kHz1kHz 4kHz 8kHz

f7kHz1kHz

4kHz 8kHz

Residue

frequencyRemove

cosሺ2𝜋𝑓𝑖𝑛𝑡) 𝑗 × sin 2𝜋𝑓𝑖𝑛𝑡

cosሺ2𝜋𝑓𝑖𝑛𝑡) + 𝑗 × sin 2𝜋𝑓𝑖𝑛𝑡

+

Complex FFT

Input frequency : 31 kHz


Extract spectrum

of the residual frequency

17/25

David Hilbert

(German mathematician)

1862-1943

RC polyphase filter

Use Analog Hilbert filter

𝐈𝐨𝐮𝐭 = 𝐀𝐜𝐨𝐬ሺ𝛚𝐭 + 𝛉)

𝐐𝐨𝐮𝐭 = 𝐀𝐬𝐢𝐧ሺ𝝎𝒕 + 𝜽)

𝐈𝐢𝐧 = 𝐜𝐨𝐬ሺ𝛚𝐭)

𝐐𝐢𝐧 = 𝟎

Polyphase

Filter

Generate in-phase and quadrature waves

from a single cosine wave

How Generate 𝑗 × sin 2𝜋𝑓𝑖𝑛𝑡

18/25

𝒇𝒊𝒏(Unknown)

Proposed Sampling Circuit

𝒇𝒓𝒆𝒔𝟑

𝒇𝒓𝒆𝒔𝟐

𝒇𝒓𝒆𝒔𝟏

RC

Polyphase

Filter

Sampling

circuit

Complex

FFT

Power

spectrum

Complex

FFT

Power

spectrum

Complex

FFT

Power

spectrum

Residue

number

system

𝐜𝐨𝐬ሺ𝟐𝝅𝒇𝒊𝒏𝒕)

𝐀𝐜𝐨𝐬ሺ𝟐𝝅𝒇𝒊𝒏𝒕 + 𝜽)

𝐀𝐬𝐢𝐧ሺ𝟐𝝅𝒇𝒊𝒏𝒕 + 𝜽)

𝒇𝒔𝟏Sampling frequency

Re1

Im1

Estimate

𝒇𝒊𝒏

Hilbert Filter

Generate

in-phase signal I

quadrature signal Q

Sampling frequencies:

relatively prime

Residue frequencies

Sampling

circuit

Re2

Im2

Sampling

circuit

Re3

Im3

𝒇𝒔𝟐

𝒇𝒔𝟑

19/25

OUTLINE






20/25

Simulation Settings

Complex FFT

Measurement at 20 GHz

using sampling frequencies of ≒ 200 kHz

• Input frequency : 12 GHz

• Frequency resolution : 1 kHz

• Sampling frequency : 229 kHz, 233 kHz, 239 kHz

( Relatively prime )

• Range of measurement : 0~2080622 kHz

( Note: 229 × 233 × 239 = 2080623 )

21/25

Simulation Results

229 kHz Sampling 233 kHz Sampling 239 kHz Sampling

50000 100000 150000 2000000 50000 100000 150000 2000000 50000 100000 150000 2000000

Residue

frequency

171 kHz

Residue

frequency

34 kHz

Residue

frequency

49 kHz

Complex FFT : cosሺ2𝜋𝑓𝑖𝑛𝑡) + 𝑗 × sin 2𝜋𝑓𝑖𝑛𝑡

• Input frequency : 12 GHz

• Frequency resolution : 1 kHz

• Sampling frequency : 229 kHz, 233 kHz, 239 kHz

22/25

Frequency Estimation by Residue Number System

a

[kHz]

b

[kHz]

c

[kHz]

k

[kHz]

0 0 0 0

1 1 1 1

2 2 2 2

┇ ┇ ┇ ┇

169 32 47 11999998

170 33 48 11999999

171 34 49 12000000

172 35 50 12000001

173 36 51 12000002

┇ ┇ ┇ ┇

226 230 236 12752320

227 231 237 12752321

228 232 238 12752322

Residue frequencies

171 kHz, 34 kHz, 49 kHz

Estimate input frequency 12GHz

Input frequency estimation

using residue frequencies

and residue number system

23/25

Simulation Result Overview

𝒇𝒊𝒏(Unknown)

𝟏𝟕𝟏𝒌𝑯𝒛

RC

Polyphase

Filter

Sampling

circuit

Complex

FFT

Power

spectrum

Complex

FFT

Power

spectrum

Complex

FFT

Power

spectrum

Residue

number

system

𝐜𝐨𝐬ሺ𝟐𝝅𝟏𝟐𝑮𝒕)

𝐀𝐜𝐨𝐬ሺ𝟐𝝅𝟏𝟐𝑮𝒕 + 𝜽)

𝐀𝐬𝐢𝐧ሺ𝟐𝝅𝟏𝟐𝑮𝒕 + 𝜽)

𝟐𝟐𝟗𝒌𝑯𝒛Sampling frequency

Re1

Im1

Estimate

𝒇𝒊𝒏 =𝟏𝟐𝑮𝑯𝒛

Sampling

circuit

Re2

Im2

Sampling

circuit

Re3

Im3

𝟐𝟑𝟑𝒌𝑯𝒛

𝟑𝟒𝒌𝑯𝒛

𝟐𝟑𝟗𝒌𝑯𝒛

𝟒𝟗𝒌𝑯𝒛

Estimate unknown input frequency

Hilbert Filter

24/25

OUTLINE






25/25

Summary and Challenge

● Proposed a method to estimate high-frequency signal

using multiple low-frequency sampling circuits.

● Confirmed its operation by theory and simulation.

● Measurable range is wide:

proportional to multiplication of multiple sampling frequencies.

● Estimated input frequency is discrete

Summary

Challenge

Consider estimation with fine frequency resolution

Thank you for your attention

Highly Efficient Waveform

Acquisition Condition in

Equivalent-Time Sampling System

Yuto Sasaki, Yujie Zhao,

Anna Kuwana, Haruo Kobayashi

Gunma University

Oct. 18, Thursday 10:30 ~ 11:00

Session 6B-1

Mixed Signal Designs and ATE

http://www.google.co.jp/url?sa=i&rct=j&q=&esrc=s&source=images&cd=&cad=rja&uact=8&docid=XxicGsaDCzsPuM&tbnid=2cjxvii7O6Y6aM:&ved=0CAcQjRw&url=http://sophie-in-tokio.blogspot.com/2010/01/owari.html&ei=S7I5VOTZIYSa8QXs8oHQCQ&bvm=bv.77161500,d.dGc&psig=AFQjCNHYkkS5Xy28Z2VuOcAl2KzQaLEzPA&ust=1413153670218700http://www.google.co.jp/url?sa=i&rct=j&q=&esrc=s&source=images&cd=&cad=rja&uact=8&docid=XxicGsaDCzsPuM&tbnid=2cjxvii7O6Y6aM:&ved=0CAcQjRw&url=http://sophie-in-tokio.blogspot.com/2010/01/owari.html&ei=S7I5VOTZIYSa8QXs8oHQCQ&bvm=bv.77161500,d.dGc&psig=AFQjCNHYkkS5Xy28Z2VuOcAl2KzQaLEzPA&ust=1413153670218700

2

Outline

Motivation

Equivalent-Time Sampling

Golden Ratio

Proposed Golden Ratio Sampling

Simulation

Conclusion

3

Outline

Motivation


Golden Ratio


Simulation

Conclusion

Motivation

4

in Equivalent-Time Sampling

GoodBad

5

Outline

Motivation


Golden Ratio


Simulation

Conclusion

6


Repetitive Wave

Sampling Clock

Reconstructed Waveform

Higher time resolution than sampling clock period

7

Waveform Missing

Repetitive Wave

Sampling Clock

Reconstructed Waveform

Toothless waveform is appeared

8

Condition

Repetitive Wave

Sampling Clock

𝑻𝒔𝒊𝒈

𝑻𝑪𝑳𝑲

𝑻𝑪𝑳𝑲 = ? × 𝑻𝒔𝒊𝒈

Sampling points move little Requires long time

Waveform Missing Conditions

9

𝑓𝐶𝐿𝐾 ≈1

𝛼𝑓𝑠𝑖𝑛𝑓𝐶𝐿𝐾 ≫ 𝑓𝑠𝑖𝑛 𝑓𝐶𝐿𝐾 ≈ 𝑓𝑠𝑖𝑛𝛼 = 1,

1

2,1

3,2

3,⋯ ,

1

6,⋯

1

Τ1 1024

CLK

1

Τ1 6

1

1

Proposed Optimal Condition

10

𝒇𝑪𝑳𝑲 = 𝝋× 𝒇𝒔𝒊𝒈

𝝋 : Golden ratio ( = 1.6180339887… )

1

Τ1 𝜑

CLK

Sampling points disperse uniformly through measurement

11

Outline

Motivation


Golden Ratio


Simulation

Conclusion

Golden Ratio

12

𝒂

𝒂

𝒃

𝒂 + 𝒃

𝜑 ≡𝑎 + 𝑏

𝑎=𝑎

𝑏

𝜑 =1 + 5

2= 1.6180339887⋯

Fibonacci Number

13

𝑭𝟎 = 𝟎

𝑭𝟏 = 𝟏

𝑭𝒏+𝟐 = 𝑭𝒏 + 𝑭𝒏+𝟏

lim𝑛→∞

𝑭𝒏𝑭𝒏−𝟏

= 𝟏. 𝟔𝟏𝟖𝟎𝟑𝟑𝟗𝟖𝟖𝟕⋯ = 𝛗

𝟎, 𝟏, 𝟏, 𝟐, 𝟑, 𝟓, 𝟖, 𝟏𝟑, 𝟐𝟏, 𝟑𝟒, 𝟓𝟓, 𝟖𝟗, 𝟏𝟒𝟒,⋯

Golden Section Search

14

• Finds the extreme value of a unimodal function by narrowing the range

• Distances of separation points are golden ratio

Golden Section Search (1/5)

0

100

200

300

400

500

600

700

800

900

1000

-10 -8 -6 -4 -2 0 2 4 6 8 10

Compare


0

100

200

300

400

500

600

700

800

900

1000

-10 -8 -6 -4 -2 0 2 4 6 8 10

Smaller

0

100

200

300

400

500

600

700

800

900

1000

-10 -8 -6 -4 -2 0 2 4 6 8 10


Value Reusable

0

100

200

300

400

500

600

700

800

900

1000

-10 -8 -6 -4 -2 0 2 4 6 8 10


Smaller


0

100

200

300

400

500

600

700

800

900

1000

-10 -5 0 5 10

0

100

200

300

400

500

600

700

800

900

1000

-10 -5 0 5 10

0

100

200

300

400

500

600

700

800

900

1000

-10 -5 0 5 10

0

100

200

300

400

500

600

700

800

900

1000

-10 -5 0 5 10

Range is narrowed x 1/Φ in every steps

20

Outline

Motivation


Golden Ratio


Simulation

Conclusion

Proposed Optimal Condition

21

𝒇𝑪𝑳𝑲 = 𝝋 × 𝒇𝒔𝒊𝒈

𝝋 : Golden ratio ( = 1.6180339887… )

1

Τ1 𝜑

CLK

Golden Ratio Sampling (8pt.)

22

1

3

5

6

8

47

2

Golden Ratio Sampling (1/8)

23

1

3

5

6

47

8

2


24

1

2

3

5

6

𝝋 𝟏

47

8


25

1

2

5

6

𝝋𝟏

4

3

7

8


26

1

2

5

6

4

𝟏𝝋

3

7

8


27

1

2

5

6

4

𝟏𝝋

3

7

8


28

1

2

5

6

4

𝟏 𝝋

3

7

8


29

1

2

5

6

74

𝟏 𝝋

3 8


30

1

2

5

6

7

8

4

𝟏 𝝋

3

Distance

31

𝟏

𝝋𝟏

𝟏

𝝋

𝝋

𝝋𝝋

All sections are divided by golden ratio

Longer and shorter range does not exist

Max. & Min. Distance

32

1

1 Τ1 𝜑

Τ1𝜑2Τ1 𝜑3

𝜑 − 1

𝜑

Max. / Min. distances = 𝝋 or 𝝋𝟐 const.

Sampling points disperse uniformly through measurement

Time Resolution

33

×𝟏

𝝋

Fibonacci Number

1

21

35

80.618

0.3820.236

0.146

𝑁𝑆

Max. & min. distances decreases x 1/Φ every Fibonacci numbers

Time resolution improves about 1 / Total Number of data

Max.

Min.

34

Outline

Motivation


Golden Ratio


Simulation

Conclusion

Histogram (1,000 pt.)

35

Uniform Distribution

DNL Transition

36

DNL standard deviation from the approximate curve is SMALL

Sampling phases are NOT appeared in the same bin successively

Accumulated Histogram (1,000 pt.)

37

Uniform Distribution

INL Transition

38

INL standard deviation from the approximate curve is SMALL

Sampling phases disperse uniformly through measurement

INL Transition (Waveform Missing)

Application

Wideband Waveform Sampling Systems

ADC Testing with Histogram Method

Time-to-Digital Converter Calibration

Integral-type Time-to-Digital Converter

40

Probability Density Function

41

𝒑 𝑽 =1

𝜋 𝐴2 − 𝑉2

𝑨: 𝐴𝑚𝑝𝑙𝑖𝑡𝑢𝑑𝑒 𝑜𝑓 𝑆𝑖𝑛𝑢𝑠𝑜𝑖𝑑𝑎𝑙 𝑊𝑎𝑣𝑒

𝑽: 𝑉𝑜𝑙𝑡𝑎𝑔𝑒

𝑉 = −𝐴 𝑉 = 𝐴0

1

𝜋𝐴

2

𝜋𝐴

3

𝜋𝐴

4

𝜋𝐴

Sinusoidal Wave

Ideal Probability of Each Bin

42

𝑩: 𝐹𝑢𝑙𝑙 𝑆𝑐𝑎𝑙𝑒 𝑅𝑎𝑛𝑔𝑒 (𝑉)

𝑵: 𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 𝑜𝑓 𝐴𝐷𝐶 (𝑏𝑖𝑡)

𝒏: 𝐶𝑜𝑑𝑒 𝐵𝑖𝑛 𝑁𝑢𝑚𝑏𝑒𝑟 (𝑛𝑡ℎ)

𝑷 𝒏 =1

𝜋𝑠𝑖𝑛−1

𝐵 𝑛 − 2𝑁−1

𝐴2𝑁− 𝑠𝑖𝑛−1

𝐵 𝑛 − 1 − 2𝑁−1

𝐴2𝑁

Histogram

Differential Non-Linearity

43

𝑫𝑵𝑳𝒏 𝑳𝑺𝑩 =𝐴𝑃𝑛𝐼𝑃𝑛

− 1

𝑨𝑷:𝑀𝑒𝑎𝑠𝑢𝑟𝑒𝑑 𝐻𝑖𝑠𝑡𝑔𝑟𝑎𝑚

𝑰𝑷: 𝐼𝑑𝑒𝑎𝑙 𝐻𝑖𝑠𝑡𝑔𝑟𝑎𝑚

Integral Non-Linearity

44

𝑰𝑵𝑳𝒏 𝑳𝑺𝑩 =

𝑖=1

𝑛

𝐷𝑁𝐿𝑖

Required Number of Samples

45

𝑵𝑹 =𝜋 × 2𝑁−1 × 𝑍 Τ𝛼 2

2

𝛽2

𝒁𝜶/𝟐: 𝑍 𝑣𝑎𝑙𝑢𝑒

𝜷:𝐷𝑁𝐿 𝑒𝑟𝑟𝑜𝑟

Waveform Missing (Case: 1)

46

𝑓𝐶𝐿𝐾 =1

𝛼𝑓𝑠𝑖𝑔 𝛼 = 1,

1

2,1

3,2

3,⋯𝑤ℎ𝑒𝑛

𝛼 =41

95→ 95 𝑝𝑜𝑖𝑛𝑡𝑠


47

𝑓𝐶𝐿𝐾 ≈ 𝑓𝑠𝑖𝑔𝑤ℎ𝑒𝑛


48

𝑓𝐶𝐿𝐾 ≫ 𝑓𝑠𝑖𝑔𝑤ℎ𝑒𝑛

Golden Ratio Sampling

49

𝑓𝐶𝐿𝐾 = 𝜑 × 𝑓𝑠𝑖𝑛𝑤ℎ𝑒𝑛

Histogram (Golden Ratio Sampling)

50𝑵𝒔: 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑆𝑎𝑚𝑝𝑙𝑒𝑠

Golden-ratio vs. Random Sampling

51

0.1 𝐿𝑆𝐵 𝐷𝑁𝐿 𝑒𝑟𝑟𝑜𝑟95% 𝑐𝑜𝑛𝑓𝑖𝑑𝑒𝑛𝑐𝑒 𝑙𝑒𝑣𝑒𝑙

8 𝑏𝑖𝑡 𝐴𝐷𝐶𝑁𝑅 =

3.14 × 27 × 1.96 2

0.1 2= 154480 𝑠𝑎𝑚𝑝𝑙𝑒𝑠

Golden-ratio Sampling Sampling at rand()

52

Outline

Motivation


Golden Ratio


Simulation

Conclusion

53

Conclusion

Our proposed golden ratio sampling rate

In waveform equivalent-time sampling system

Sampling clock frequency x Input signal period

= golden ratio

Can avoid waveform missing.

Sampling points are dispersed uniformly

through the measurement.

Appendix

54

𝑻𝑪𝑳𝑲 =𝑸

𝑷× 𝑻𝒔𝒊𝒈

55

Condition

Repetitive Wave

Sampling Clock

𝑻𝒔𝒊𝒈

𝑻𝑪𝑳𝑲

Fixed Number of Data

56



P, Q: integers and

relatively prime

P: Maximum number of total measurable sampling points

Q: determines phase distance for each sampling

1

𝑃𝑇𝑠𝑖𝑔

𝑸



𝟏𝟎𝟐𝟒× 𝑻𝒔𝒊𝒈

57

𝑸

≈ golden ratio

𝟏𝟎𝟐𝟒 − 𝟑𝟑𝟗

𝟏𝟎𝟐𝟒

𝟔𝟑𝟕

𝟏𝟎𝟐𝟒

min.

Distances of INL standard deviation

from the approximate curve (RMS)

Golden-ratio vs. Real-time Sampling

58

0.1 𝐿𝑆𝐵 𝐷𝑁𝐿 𝑒𝑟𝑟𝑜𝑟95% 𝑐𝑜𝑛𝑓𝑖𝑑𝑒𝑛𝑐𝑒 𝑙𝑒𝑣𝑒𝑙

8 𝑏𝑖𝑡 𝐴𝐷𝐶𝑁𝑅 =

3.14 × 27 × 1.96 2

0.1 2= 154480 𝑠𝑎𝑚𝑝𝑙𝑒𝑠

Golden-ratio Sampling Real-time Sampling

Fundamental Design Consideration

of Sampling Circuit

Keita Kurihara, Kensuke Kobayashi

Masafumi Uemori, Miho Arai, Haruo Kobayashi

Electronics and Informatics Division, Gunma University, Japan

Consultant, Penang, Malaysia

D10-4 14:30-14:50 Apr. 26 2016 (Tue)

2/45

OUTLINE

Research Background and Objective

Sample/Hold Circuit

Two S/H Circuits

Track/Hold Circuit

Impulse Sampling Circuit

Unified S/H Circuit Theory

Condition of Maximum SNR

Under Constant Bandwidth

Conclusion

3/45

OUTLINE


Sample/Hold Circuit

Two S/H Circuits

Track/Hold Circuit





Conclusion

4/45

Waveform Sampling

Continuous-time

Continuous amplitude

signal

Discrete-time

signal

Analog Signal

Vo

lta

ge

time

サンプル信号 Sampled Signal V

oltage

time

Sampling

5/45

Analog-to-Digital Converter

Analog input Analog Input Digital Output

Sampling Clock

Real world signals

Ex) Radio wave

Voice

Video

Temperature ...

Circuit

Rounded as integer

6/45


Fundamental trade-off clarification of S/H circuit design.

Research Objective

Research Background

High-frequency, wideband signals become more utilized

in electronic and communication systems .

Their acquisition with S/H circuit is very important.

Fundamental theory of S/H circuit has not been established yet.

7/45

OUTLINE


Sample/Hold Circuit

Two S/H Circuits

Track/Hold Circuit





Conclusion

8/45

Configuration of S/H Circuit

Open-loop S/H circuit：

Switch and Capacitor

時間

電圧

CSW

Vin Vout

時間

電圧

Sample Hold time time

voltage

voltage

9/45

Operation of S/H Circuit

CSW

Vin Vout

CSW

Vin Vout

SW : ON

Vout(t) = Vin(t)

Sample mode

SW : OFF

Vout(t) = Vin(tOFF)

Hold mode

時間

電圧

tOFF time

voltage

時間

電圧

tOFF time

vo

ltage

10/45

Configuration of Wideband S/H Circuit

S/H Circuit Signal Source

Bandwidth-limited by input buffer

Input

buffer

C

SW

RSG Ron Output

buffer

11/45

Bandwidth-limited by input buffer

Configuration without input buffer

Configuration of Wideband S/H Circuit

Discharge

after

reading

S/H Circuit

SW

RSG Ron

Signal Source

C

12/45

Two Time Constants 𝝉𝟏, 𝝉𝟐 in S/H Circuit

S/H Circuit Signal Source

SW

RSG Ron

𝜏2 C

Two Time Constants in S/H Circuit

𝜏1 : (RSG+ Ron) x C

𝜏2 : Switching time window

13/45

OUTLINE


Sample/Hold Circuits

Two S/H Circuits

Track/Hold Circuit





Conclusion

14/45

Two S/H Circuits

Track/Hold Circuit 𝝉𝟐 ≫ 𝝉𝟏

Impulse Sampling Circuit 𝝉𝟐 ≪ 𝝉𝟏 (narrow window)

ADC on SoC Sampling oscilloscope

Currently used in different worlds

15/45

Our Challenge !!

ADC on the SoC Sampling oscilloscope

Currently used separately Unified Theory

Track/Hold Circuit 𝝉𝟐 ≫ 𝝉𝟏

Impulse Sampling Circuit 𝝉𝟐 ≪ 𝝉𝟏 (narrow window)

16/45

Operation of Two S/H Circuits

ｔ

1

ｔ 𝜏2

1 ≒1

ｔ 𝜏2

1

∝ 𝜏2

ｔ 𝜏2 S H ｔ 𝜏2 S H

Wide pulse

Switch

Step

input

Output

Complete charge

Narrow pulse

Incomplete charge

Switch

Output

Track/Hold (𝜏2 ≫ 𝜏1) Impulse Sampling (𝜏2 ≪ 𝜏1)

17/45 Frequency Transfer Function

of Two S/H Circuits

H1 𝑗ω =1

1 + jτ1𝜔 H2 𝑗ω =

𝜏2τ1𝑠𝑖𝑛𝑐

𝜏22𝜔 𝑒−𝑗

𝜏22 𝜔


𝜏1 = 10𝑝𝑠 𝜏2 = 1𝑝𝑠

𝜏1 = 10𝑝𝑠 𝜏2 = 100𝑝𝑠

18/45

Small DC Gain

Wideband

H1 𝑗ω =1

1 + jτ1𝜔 H2 𝑗ω =



𝜏22 𝜔


𝜏1 = 10𝑝𝑠 𝜏2 = 1𝑝𝑠

𝜏1 = 10𝑝𝑠 𝜏2 = 100𝑝𝑠

Frequency Transfer Function

of Two S/H Circuits

19/45

kT/C Noise in S/H Circuit

R

- + C

____2

RnV

+

-

Noise power

𝑘𝐵 = 1.38 × 10−23 JK−1

𝑇 = 300 K 𝑅 = 50 Ω

𝑃𝑛𝑜𝑖𝑠𝑒 = 4𝑘𝐵𝑇𝑅

4𝜋2𝑅2𝐶2𝑓2 + 1𝑑𝑓

∞

0

=𝑘𝐵𝑇

𝐶=𝑘𝐵𝑇𝑅

𝜏1

R

- +

C

____ 2

Rn

V

+ -

熱雑音

4kTR

周波数

VR

n2 [

V2/H

z]

1/RC Thermal noise

frequency

20/45

𝐵𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ1 = 1/𝜏1

𝑆𝑁𝑅1 ∝ 𝜏1

𝐵𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ2 ≈ 2.78/𝜏2

𝑆𝑁𝑅2 ∝ 𝜏2/ 𝜏1

𝜏1：RC product 𝜏2：Switching time window

Bandwidth and SNR of Two S/H Circuits


H1 𝑗ω =1

1 + jτ1𝜔 H2 𝑗ω =



𝜏22 𝜔

21/45

𝐵𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ1 = 1/𝜏1

𝑆𝑁𝑅1 ∝ 𝜏1

𝐵𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ2 ≈ 2.78/𝜏2

𝑆𝑁𝑅2 ∝ 𝜏2/ 𝜏1

𝜏1：RC product 𝜏2：Switching time window


H1 𝑗ω =1

1 + jτ1𝜔 H2 𝑗ω =



𝜏22 𝜔

Fundamental Trade-off

Trade-off Trade-off

Bandwidth and SNR of Two S/H Circuits

22/45

OUTLINE



Two S/H Circuits

Track/Hold Circuit





Conclusion

23/45 Derivation of Unified Theory (1)

~ Impulse Response by Equivalent Time Sampling ~

𝑉𝑜𝑢𝑡

𝑡𝑖𝑚𝑒

switching 𝑡𝑖𝑚𝑒 𝑤𝑖𝑛𝑑𝑜𝑤

𝑡𝑖𝑚𝑒

𝑉in

𝑡𝑖𝑚𝑒

1

1/𝜏1

24/45

𝑉𝑜𝑢𝑡

𝑡𝑖𝑚𝑒


𝑡𝑖𝑚𝑒

𝑉in

𝑡𝑖𝑚𝑒

1

1/𝜏1

Derivation of Unified Theory (1)


25/45

𝑉𝑜𝑢𝑡

𝑡𝑖𝑚𝑒


𝑡𝑖𝑚𝑒

𝑉in

𝑡𝑖𝑚𝑒

1

1/𝜏1

𝑅𝑒𝑐𝑜𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑒𝑑 𝑤𝑎𝑣𝑒𝑓𝑜𝑟𝑚

𝑉𝑜𝑢𝑡

𝑡𝑖𝑚𝑒

1/𝜏1



26/45

H3 𝑗𝜔 = ℎ 𝑡 𝑒−𝑗𝜔𝑡𝑑𝑡

∞

−∞

= 1

τ1𝑒−1𝜏1𝑡𝑒−𝑗𝜔𝑡𝑑𝑡

𝜏2

0

=1

τ1 𝑒

−1𝜏1+𝑗𝜔 𝑡

𝑑𝑡𝜏2

0

= −1

τ1

1

1𝜏1+ 𝑗𝜔

𝑒−1𝜏1+𝑗𝜔 𝑡

0

𝜏2

=1

1 + 𝑗𝜏1𝜔1 − 𝑒

−𝜏2𝜏11+𝑗𝜏1𝜔

Unified transfer function

ℎ 𝑡 =

0…………… . 𝑡 < 0

1 𝜏1 ⋅ 𝑒−𝑡𝜏1 … 0 ≤ 𝑡 < 𝜏2

0…………… . 𝜏2 ≤ 𝑡

𝑉𝑜𝑢𝑡

𝑡𝑖𝑚𝑒

1/𝜏1 Fourier transform


~ Fourier Transform of Impulse Response ~

27/45 Relationship of

T/H, Impulse Sampling and Unified S/H Circuits

H3 jω =1

1 + jτ1𝜔1 − 𝑒

− 1+𝑗𝜏1𝜔𝜏2𝜏1

(Impulse Sampling Circuit)

Unified Theory

𝐻3(𝑗𝜔) =𝜏2τ1𝑠𝑖𝑛𝑐


𝜏22 𝜔 = 𝐻2(𝑗𝜔) 𝜏2 ≪ 𝜏1

𝜏2 ≫ 𝜏1 𝐻3(𝑗𝜔) =1

1 + jτ1𝜔= 𝐻1(𝑗𝜔)

(Track/Hold Circuit)

lim𝜏2𝜏1→∞

lim𝜏2𝜏1→0

𝜏1𝜔≫1

28/45

Track/Hold Circuit

𝜏2 𝜏1 ≫ 1


𝜏2 𝜏1 ≪ 1

Gain Characteristics of Unified S/H Circuit

29/45

T/H Impulse sampling

𝜏1：RC product (fixed) 𝜏2：Switching time window

GB Product and Switching Time Window 𝛕𝟐 of Unified S/H Circuit

30/45

T/H


Impulse sampling

Impulse Sampling

Circuit

GB Product2 = 𝟐. 𝟖 𝜏1

Track/Hold Circuit

GB Product1 = 𝟏 𝜏1


31/45

Track/Hold Circuit

GB Product1 = 𝟏 𝜏1

Impulse Sampling

Circuit

GB Product2 = 𝟐. 𝟖 𝜏1


GB Product

𝟐. 𝟖 times


Impulse sampling T/H

32/45


GB Product

𝟐. 𝟖 times

𝐺𝐵 𝑃𝑟𝑜𝑑𝑢𝑐𝑡2𝐺𝐵 𝑃𝑟𝑜𝑑𝑢𝑐𝑡1

=𝐷𝐶 𝐺𝑎𝑖𝑛2 ⋅ 𝐵𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ2𝐷𝐶 𝐺𝑎𝑖𝑛1 ⋅ 𝐵𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ1

≈𝜏2/𝜏1 ⋅ 2.8/𝜏2

1 ⋅ 1/𝜏1 = 2.8



33/45

𝜏1：RC product 𝜏2：Switching time window (fixed)

SNR and 𝛕𝟏 (𝛕𝟐 = 𝟏𝟎−𝟏𝟐)

of Unified S/H Circuit


34/45


Track/Hold Circuit

SNR1 ∝ 𝜏1 Impulse Sampling

Circuit

SNR2 ∝ 𝜏2 𝜏1

SNR and 𝛕𝟏 (𝛕𝟐 = 𝟏𝟎−𝟏𝟐)



35/45


Track/Hold Circuit

SNR1 ∝ 𝜏1 Impulse Sampling

Circuit

SNR2 ∝ 𝜏2 𝜏1

Maximized SNR

at 𝛕𝟐/𝛕𝟏 ≈ 𝟏. 𝟑

SNR and 𝛕𝟏 (𝛕𝟐 = 𝟏𝟎−𝟏𝟐)



36/45


Maximized SNR

at 𝛕𝟐/𝛕𝟏 ≈ 𝟏. 𝟑

From, 𝜕

𝜕𝜏1𝑆𝑁𝑅3 = 0

SNR3 = 𝜏1/(𝑘𝐵𝑇𝑅) 1 − 𝑒−𝜏2/𝜏1 1 + 2

𝜏2𝜏1= 𝑒

𝜏2𝜏1

𝜏2𝜏1= 1.26 1.26

SNR and 𝛕𝟏 (𝛕𝟐 = 𝟏𝟎−𝟏𝟐)



37/45

OUTLINE


Sample/Hold Circuit

Two S/H Circuits

Track/Hold Circuit





Conclusion

38/45

Transfer function：𝐻3 𝑗𝜔 =1

1+𝑗𝜏1𝜔1 − 𝑒

−𝜏2𝜏11+𝑗𝜏1𝜔

Bandwidth 𝝎𝐵𝑊： 𝐻3 𝑗𝜔𝐵𝑊3 =1

2𝐻3 𝑗0

1

1 + 𝜏12𝜔2

1 − 𝑒−𝜏2𝜏1 cos 𝜔𝜏2

2

+ 𝑒−𝜏2𝜏1 sin 𝜔𝜏2

2

=1

21 − 𝑒

−𝜏2𝜏1

Analytical solution is difficult to obtain.

Rigorous Formula

Bandwidth𝝎𝐵𝑊 of Unified S/H Circuit

39/45 Approximation Formula

Bandwidth𝝎𝐵𝑊 of Unified S/H Circuit

𝜔𝐵𝑊3 ≈2.20

𝒕𝒓𝟏𝟎−𝟗𝟎

𝑡10% 𝑡90% 𝜏2

S

𝑡𝑖𝑚𝑒

𝑣𝑜𝑙𝑡𝑎𝑔𝑒

𝒕𝒓𝟏𝟎−𝟗𝟎

0.9S

0.1S

𝑆 = 1 − 𝑒−𝜏2𝜏1

Assume first-order system,

deriving 𝝎𝐵𝑊 from 𝑡𝑟10−90

40/45 SNR Under Constant Bandwidth

𝑆𝑁𝑅 = 101

𝑘𝐵𝑇𝑅𝜏11 − 𝑒

𝑡𝑟10−90𝜏1

1 − 9𝑒𝑡𝑟10−90𝜏1

Bandwidth

[rad/s]

109

1012

1010

1011

41/45 SNR Under Constant Bandwidth

𝑆𝑁𝑅 = 101

𝑘𝐵𝑇𝑅𝜏11 − 𝑒

𝑡𝑟10−90𝜏1

1 − 9𝑒𝑡𝑟10−90𝜏1

Bandwidth

[rad/s]

109

1012

1010

1011

Maximum SNR

at 𝝉𝟐/𝝉𝟏 ≈ 𝟏. 𝟓

42/45

𝑁𝑜𝑟𝑚𝑎𝑙𝑖𝑧𝑒𝑑 𝑆𝑁𝑅

𝑆𝑁𝑅𝑚𝑎𝑥 = 1.1 × 𝑆𝑁𝑅𝑇/𝐻

SNR vs 𝛕𝟐/𝛕𝟏 of Unified S/H Circuit

43/45

OUTLINE



Two S/H Circuits

Track/Hold Circuit





Conclusion

44/45

Conclusion

Two S/H Circuits

Bandwidth, SNR

Trade-off

Theoretical limitation


GB Product: Impulse mode is 2.8 times larger than T/H mode

Maximum SNR condition:

τ2/τ1 ≈ 1.3 Under Constant Switching Time Window τ2/τ1 ≈ 1.5 Under Constant Bandwidth

Track/Hold Circuit 𝜏2 ≪ 𝜏1 Impulse Sampling Circuit 𝜏2 ≫ 𝜏1

45/45

Final Statement

学而不思則罔

Deep consideration

would advance modern technology.

47/45

Appendix

48/45

Characteristics of S/H Circuits

T/H Circuit Impulse Sampling Circuit

Transfer

Function H1 𝑗ω =

1

1 + jτ1𝜔 H2 𝑗ω =



𝜏22 𝜔

DC Gain 𝑉𝑠𝑖𝑔𝑛𝑎𝑙1 = H1 0 = 1 𝑉𝑠𝑖𝑔𝑛𝑎𝑙2 = H2 0 =𝜏2τ1

Bandwidth 𝜔𝐵𝑊1 =1

𝜏1 𝜔𝐵𝑊2 ≈

2.78

𝜏2

Thermal

Noise 𝑉𝑛𝑜𝑖𝑠𝑒 =

𝑘𝐵𝑇𝑅𝜏1 𝑉𝑛𝑜𝑖𝑠𝑒 =

𝑘𝐵𝑇𝑅𝜏1

GB

Product 𝐺𝐵𝑃1 =

1

𝜏1 𝐺𝐵𝑃2 ≈

2.78

𝜏1

SNR 𝑆𝑁𝑅1 =𝜏1

𝑘𝐵𝑇𝑅∝ 𝜏1 𝑆𝑁𝑅2 =

1

𝑘𝐵𝑇𝑅⋅𝜏2𝜏1∝𝜏2𝜏1

49/45

∝𝟏

𝝉𝟏

∝𝟏

𝝉𝟏

∝𝟏

𝝉𝟏

∝𝟏

𝝉𝟏

∝𝟏

𝝉𝟏

∝ 𝝉𝟏

∝𝟏

𝝉𝟏

∝𝟏

𝝉𝟏

const

const

∝𝟏

𝝉𝟏

∝𝟏

𝝉𝟏

SN

R

B*S

NR

G

BP

Band

Nois

e

DC

Gain

Characteristics

of S/H Circuits

𝜏𝟏:varied

𝜏𝟐:fixed

(𝜏𝟐 = 10−12)

50/45 まとめ(𝜏1 =10−12)

SN

R

B*S

NR

const

const

GB

P

const

const

Band

const

∝𝟏

𝝉𝟐

const Nois

e

DC

Gain

∝ 𝝉𝟐

const

const

∝ 𝝉𝟐

const

Characteristics

of S/H Circuits

𝜏𝟏:fixed

(𝜏𝟏 = 10−12)

𝜏𝟐:varied

51/45 Derivation of the transfer function

of the impulse sampling circuit

𝐻2 𝑗𝜔 = 𝑉𝑜𝑢𝑡𝑒−𝑗𝜔𝑡𝑑𝑡

∞

0

= 1

𝜏1𝑒−𝑗𝜔𝑡𝑑𝑡

𝜏2

0

=1

𝜏1

1

𝑗𝜔1 − 𝑒−𝑗𝜔𝜏2

=1

𝜏1

1

𝑗𝜔𝑒𝑗𝜔𝜏22 − 𝑒−𝑗

𝜔𝜏22 𝑒−𝑗

𝜔𝜏22

=𝜏2τ1𝑠𝑖𝑛𝑐


𝜏22𝜔

52/45 lim

𝜏2/𝜏1 →01 − 𝑒

− 1+𝑗𝜏1𝜔𝜏2𝜏1 = 0 ?

lim𝜏2𝜏1→0

𝜏1𝜔≫1

H3 jω

= lim𝜏2𝜏1→0

𝜏1𝜔≫1

1

1 + jτ1𝜔1 − 𝑒

− 1+𝑗𝜏1𝜔𝜏2𝜏1

=1

jτ1𝜔1 − 𝑒−𝑗𝜏2𝜔

=1

𝜏1

1

𝑗𝜔 𝑒𝑗

𝜔𝜏22

− 𝑒−𝑗𝜔𝜏22 𝑒−𝑗

𝜔𝜏22



𝜏22 𝜔

= H2 jω

𝐻2 𝑗𝜔 = 𝑉𝑜𝑢𝑡𝑒−𝑗𝜔𝑡𝑑𝑡

∞

0

=1

𝜏1𝑒−𝑗𝜔𝑡𝑑𝑡

𝜏2

0

=1

𝜏1

1

𝑗𝜔1 − 𝑒−𝑗𝜔𝜏2

=1

𝜏1

1

𝑗𝜔𝑒𝑗𝜔𝜏22 − 𝑒−𝑗

𝜔𝜏22 𝑒−𝑗

𝜔𝜏22



𝜏22𝜔

lim𝜏2/𝜏1 →0

1 − 𝑒− 1+𝑗𝜏1𝜔

𝜏2𝜏1

= lim𝜏2/𝜏1 →0

1

− 𝑒−𝜏2𝜏1𝑒−𝑗𝜏2𝜔

= 1 − 𝑒−𝑗𝜏2𝜔

Measurement 31 (2002) 187–199www.elsevier.com/ locate /measurement

Sampling clock jitter effects in digital-to-analog convertersa a , a b*Naoki Kurosawa , Haruo Kobayashi , Hideyuki Kogure , Takanori Komuro ,

bHiroshi SakayoriaDepartment of Electronic Engineering, Gunma University, 1-5-1 Tenjin-cho, Kiryu 376-8515, Japan

bAgilent Technologies Japan Ltd., 9-1 Takakura-cho Hachioji, Tokyo 192-8510, Japan

Abstract

This paper describes sampling clock jitter effects in digital-to-analog converters. A formula for the output error power dueto sampling clock jitter for a sinusoidal input is derived and verified by numerical simulations, and its spectrumcharacteristics is shown. Also its effects on DAC SNR is clarified by numerical simulation as follows: (i) When the totalnoise power outside as well as inside the signal band is taken into account, the DAC SNR remains almost constant regardlessof the sampling jitter. (ii) However, when an analog lowpass filter follows the DAC and only the noise power inside thesignal band is considered, the DAC SNR degrades as the jitter increases and the input signal frequency becomes higher. Thusthe sampling clock jitter is serious for the high speed DAC. 2002 Elsevier Science Ltd. All rights reserved.

Keywords: Jitter; Sampling; DAC; Analog circuit; Spread spectrum

1. Introduction numerical simulation verifies the derived formula. InSection 4, the power spectrum characteristics of the

Digital-to-analog converters (DACs) are essential DAC output error due to the sampling jitter iscomponents for measuring instruments (such as discussed, and in Section 5 we clarify by numericalarbitrary waveform signal generators) and communi- simulations that sampling clock jitter degrades sig-cation systems (such as transceivers), and higher nal-to-noise ratio (SNR, one of the important per-sampling speed is being demanded for them [1–3]. formance metrics of the DAC [3]) significantly.For such high sampling speed DACs, their sampling Finally Section 6 provides conclusion.clock jitter effects may be crucial; the clock jittereffects of DACs have not been well investigated,even though those of analog-to-digital converters 2. DAC output error power due to sampling(ADCs) and sampling circuits have been [4–8]. In clock jitterthis paper we analyze their effects theoretically andverify them by numerical simulations. In Section 2, 2.1. Problem formulationthe formula for the DAC output error power due tothe sampling jitter is derived, and in Section 3, Fig. 1 shows a DAC where a digital input V (n) isin

applied with a sampling clock of CLK. Ideally thesampling clock CLK operates with a period of T fors*Corresponding author. Tel.: 181-277-30-1788; fax: 181-277-every cycle, however in reality its timing can fluc-30-1707.

E-mail address: k [email protected] (H. Kobayashi). tuate which is called jitter or phase noise (Fig. 2)]

0263-2241/02/$ – see front matter 2002 Elsevier Science Ltd. All rights reserved.PI I : S0263-2241( 01 )00028-8

188 N. Kurosawa et al. / Measurement 31 (2002) 187 –199

sampling period of T in most of practical situations,swe assume that

T Ts s] ]2 , e , . (1)n2 2

Also we suppose that the DAC has sufficiently goodFig. 1. A DAC with digital input signal, sampling clock and resolution so that quantization can be neglected, andanalog output signal.

the DAC output V (t) is zero-order hold [3]. Thenout[9,10]. If we denote jitter as e , then the n-th Fig. 3 shows the DAC outputs with an ideal clocknsampling timing of CLK is nT 1 e instead of nT . (without jitter) and an actual clock (with jitter) whiles n sSince the jitter e is sufficiently smaller than the Fig. 4 shows the DAC output error due to jitter.n

Fig. 2. Ideal sampling clock (without jitter) and actual sampling clock (with jitter e ) provided to a DAC.n

Fig. 3. DAC output waveforms with ideal sampling clock (without jitter) and actual sampling clock (with jitter e ).n

N. Kurosawa et al. / Measurement 31 (2002) 187 –199 189

Fig. 4. DAC output error due to sampling clock jitter e .n

2.2. Error power formula due to jitter assumed for the DAC sampling clock; the n-th DACsampling timing is nT 1 D instead of nT , where Ds n s n

The DAC output error power P due to the is a periodic sequence with period M. This problemesampling clock jitter is defined as follows: formulation is similar to that for the timing skew

effect in time-interleaved ADC systems [4,13]. InN211 2 Ref. [12] it is considered that the DAC sampling]P [ lim O e ue u (Time Average)e n nNN→` (2) clock is phase-modulated by a deterministic sinen50

2 wave and it is given by5 E[e ue u] (Ensemble Average).n n

Here e is the DAC output error due to jitter (see Fig. A cos(v t 1 b sin(v t))n s j4). If the input signal V (t) and the sampling jitterinare not correlated (which is the case in general), e where v is the nominal DAC clock frequency, v isn s jand e are independent and we obtain the jitter frequency and b is the modulation index.n

On the contrary, in this paper we consider the case2P 5 E[e ]E[ue u]. (3)e n n that the DAC sampling clock is phase-modulated bya random signal, as described above in this section.

Proposition. When the input V (n) to the DAC is aincosine wave

fin 3. Numerical simulation of DAC output error]V (n) 5 A cos 2p n ,S Din f power due to sampling clock jitters

the error power P due to jitter is given bye Example 1. Suppose that the jitter e follows anuniform distribution whose probability function p(e )f nin2 2 ]P 5 2A sin p n E[ue u].S D is shown in Fig. 5:e fs

1Here f is the input frequency and f is the samplingin s ] (2a # e # a)nfrequency ( f 5 1/T ). p(e ) 5 2as s n 50 (otherwise).Proof of Proposition. See Appendix A.

Note that 0 , a , T /2 according to Eq. (1). SincesRemark. The references of [11,12] discuss non- 1

]E[ue u] 5 a,uniform sampling effects to DACs, however, our n 2problem formulation is different from theirs. In Ref.[11], periodic fixed-amount of timing offsets are we obtain


Fig. 5. Probability distribution of the jitter e (uniform distribu-ntion, 0 , a , T /2).s Fig. 7. Probability distribution of the jitter e (triangular dis-n

tribution, 0 , a , T /2).s

fin2 2 1]P 5 A a sin p . (4)S De ] (a 2 ue u) (2a # e # a)f 2 n ns p(e ) 5 an 5Fig. 6 shows a graph of f /f versus P calculated 0 (otherwise).in s enumerically from Eq. (4) and a graph obtained froma DAC simulation including jitter, where a 5 T /4s Similarly, we assume 0 , a , T /2 according to Eq.sand A 5 2 are used in both cases. We see that both (1). Sincematch well and hence Eq. (4) is verified by simula-tion.

1]E[ue u] 5 a,n 3Example 2. Suppose that the jitter e follows an

distribution whose probability function p(e ) is inntriangular shape as shown in Fig. 7: we obtain

Fig. 6. f /f versus P characteristics for the cosine wave input of amplitude A 5 2 and the jitter of the uniform distribution with a 5 T /4in s e s(Fig. 5). The solid line shows numerical calculation results from Eq. (4) while 1 indicates DAC simulation results including jitter.


Fig. 8. f /f versus P characteristics for the cosine wave input of amplitude A 5 2 and the jitter of the triangular distribution with a 5 T /4in s e s(Fig. 7). The solid line shows numerical calculation results from Eq. (5) while 1 indicates DAC simulation results including jitter.

f2 in2 2] ]P 5 A a sin p . (5)S De 3 fsFig. 8 shows a graph of f /f versus P calculatedin s enumerically from Eq. (5) and a graph obtained froma DAC simulation including jitter, where a 5 T /4sand A 5 2 are used in both cases. We see that bothmatch well and Eq. (5) is verified by simulation.

Example 3. Suppose that the jitter e follows andistribution whose probability function is in cosine

Fig. 9. Probability distribution of the jitter e (cosine distribution,nshape as shown in Fig. 9: 0 , a , T /2).s

pep n] ]cos (2a # e # a)S D n4a 2ap(e ) 5n H f2 in2 20 (otherwise). ] ]P 5 (p 2 2)A a sin p . (6)S De p fs

Similarly, we assume 0 , a , T /2 according to Eq. Fig. 10 shows a graph of f /f versus P calculateds in s e(1). Since numerically from Eq. (6) and a graph obtained from

a DAC simulation including jitter, where a 5 T /4sa and A 5 2 are used in both cases. We see that both]E[ue u] 5 (p 2 2),n match well and Eq. (6) is verified by simulation.p

we obtain Example 4. Suppose that the jitter e follows an


Fig. 10. f /f versus P characteristics for the cosine wave input of amplitude A 5 2 and the jitter of the cosine distribution with a 5 T /4in s e s(Fig. 9). The solid line shows numerical calculation results from Eq. (6) while 1 indicates DAC simulation results including jitter.

distribution whose probability function is in cosine we obtainsquared shape as shown in Fig. 11:

f1 in2 2 2] ]P 5 (p 2 4)A a sin p . (7)pe1 S De 2n2 fp] ] scos (2a # e # a)S D na 2ap(e ) 5n 5Fig. 12 shows a graph of f /f versus P calculated0 (otherwise). in s enumerically from Eq. (7) and a graph obtained from

Similarly, we assume 0 , a , T /2 according to Eq.s a DAC simulation including jitter, where a 5 T /4s(1). Since and A 5 2 are used in both cases. We see that botha match well and Eq. (7) is verified by simulation.2]]E[ue u] 5 (p 2 4),n 22p

Remark. (i) The numerical simulation results in thissection show the plausibility of ergodic processassumption in Eq. (2); Eqs. (4)–(7) are derived byensemble average while the numerical simulationuses time average, and as Figs. 6, 8, 10 and 12 showthat the equations and the simulation results matchvery well.

(ii) In general the quantization noise (which weneglect in our problem formulation in Section 2) andthe noise due to the sampling jitter in a DAC arestatistically independent. Hence the total error powerwhen both the quantization and the sampling jitterexist is just the simple addition of the error powerdue to quantization and that due to the samplingFig. 11. Probability distribution of the jitter e (cosine squaredn

distribution, 0 , a , T /2). jitter. We have confirmed this fact by numericals


Fig. 12. f /f versus P characteristics for the cosine wave input of amplitude A 5 2 and the jitter of the cosine squared distribution (Fig.in s e11) with a 5 T /4. The solid line shows numerical calculation results from Eq. (7) while 1 indicates DAC simulation results includingsjitter.

simulation; Fig. 13 shows simulation results for jitter power when both jitter and quantization exist is theand quantization effects, where jitter of the uniform addition of the error power when only jitter exists todistribution with a 5 T /800 (Fig. 5) and 6-bit that when only quantization exists. According to oursquantization are assumed. We see that the error simulation, this fact holds for jitter of other dis-

Fig. 13. Simulation results for jitter and quantization effects, where jitter of the uniform distribution with a 5 T /800 (Fig. 5) and 6-bitsquantization are assumed. We see that the error power when both jitter and quantization exist are the addition of the error power when onlyjitter exists to that when only quantization exists.


tributions and other levels of quantization (e.g. 8-bit be approximated by multiplication of the samplingquantization). impulse by e , where e 5 62A sin(p( f /f ))n n in s

1](iii) According to our experiences, the cosine sin(2p( f /f )(n 2 )). The sampling impulse can bein s 2

squared distribution in Example 4 (Fig. 11) approxi- approximated by Fourier series with a fundamentalmates the actual jitter distribution most accurately. frequency of f . Hence the peak frequencies of thes

DAC error power due to jitter are kf 6 f .s in

4. Power spectrum of DAC output error due to5. Sampling jitter effects on DAC SNRsampling clock jitter

According to Eq. (8), one might ponder as fol-Next we will consider the power spectrum charac-lows: ‘If the input signal f is smaller than Nyquistteristics of the DAC output error due to the jitter. infrequency f /2 (which is usually the case), kf 6 fSuppose that the input V (n) to the DAC is a cosine s s ininare beyond f /2 for all of k 5 1, 2, 3, . . . (in otherwave swords these are out of signal band) and hence the

fin error peaks can be attenuated by an analog filter]V (n) 5 A cos 2p nS Din fs following the DAC. Therefore the sampling jittereffects on DACs are not serious.’ However, thisand the DAC suffers from sampling clock jitter ofstatement is not true. Their effects are very seriousthe uniform distribution (Fig. 5). Fig. 14 showsand now we will show their effects to DAC SNR.simulation results of the power spectrum of the error,Fig. 15 shows the power spectrum of a 10-bit idealand we see that their power has peaks atDAC output without jitter for f /f 5 103/512. Sincein s

kf 6 f (k 5 1, 2, 3, . . . ). (8) we consider the case that the DAC output is zero-s inorder hold, the DAC output error due to the zero-

Remark. For all of the other jitter distributions order hold output has peaks of the power spectrum atshown in the above examples, the error power due to kf 6 f (k 5 1, 2, 3, . . . ) [3]. Then it follows froms inthe jitter has peaks at the same frequencies. This can Eq. (8) that the DAC output errors due to jitter andbe explained qualitatively as follows: the error can zero-order hold have the peaks of the power spec-

Fig. 14. The power spectrum of DAC output error power due to jitter (whose distribution is shown in Fig. 5 with a 5 T /4) for the inputsV (n) 5 cos(2p( f /f )n) with f /f 5 103/512. The peaks are located at f k6 f where k 5 1, 2, 3, . . . .in in s in s s in


Fig. 15. The power spectrum of a 10-bit DAC zero-hold output without the sampling clock jitter for f /f 5 103/512.in s

trum at the same frequencies. On the other hand, Fig. jitter. However, in practical situation, the DAC is16 shows the power spectrum of the same DAC with often followed by an analog low filter which suffi-jitter (cosine squared distribution of a 5 T /4 in Fig. ciently attenuates the noise components beyond f /2.s s11), and we see that the noise floor increases. Figs. In this case we consider that SNR is given by 1017 and 18 show the SNRs of the DAC with and log hsignal powerj / hnoise power between 0 to f /210 swithout jitter, where the whole noise (outside as well (total noise power in the signal band)j [dB], andas inside the signal band f /2) is considered. We see Figs. 19 and 20 show the simulation results of SNRssthat SNR degrades slightly (by a few dB) due to the using the above definition with the sampling clock

Fig. 16. The power spectrum of a 10-bit DAC zero-hold output with the sampling clock jitter of cosine squared distribution of a 5 T /4s(Fig. 11), for f /f 5 103/512.in s


Fig. 17. Simulation result of SNR versus f /f of a 10-bit DAC with and without jitter of cosine squared distribution of a 5 T /4 (Fig. 11).in s sHere the total noise power outside as well as inside the signal band is considered.

Fig. 18. Simulation result of SNR versus the jitter a /T of a 10-bit DAC with jitter of cosine squared distribution (Fig. 11) forsf /f 5 3/512. Here the total noise power outside as well as inside the signal band is considered.in s

jitter; Fig. 19 shows that as the input frequency f power due to the zero-hold output and the jitter hasinincreases for a given jitter, SNR gets worse while the peaks at kf 6 f (k 5 1, 2, 3, . . . ) (which iss inFig. 20 shows that as the jitter increases for a given higher than f /2 for all k) and if we consider thesinput frequency f , SNR degrades significantly. whole noise outside as well as inside the signal bandinThese results can be interpreted as follows: the noise f /2, the dominant noises are located at these fre-s


Fig. 19. Simulation result of SNR versus f /f of a 10-bit DAC with and without jitter of cosine squared distribution of a 5 T /4 (Fig. 11).in s sHere only the noise power inside the signal band f /2 is considered.s

Fig. 20. Simulation result of SNR versus the jitter a /T of a 10-bit DAC with jitter of cosine squared distribution (Fig. 11) for f /f 5 3/512.in sHere only the noise power inside the signal band f /2 is considered.s

quencies. The sampling clock jitter induces the the total noise power remains almost constant. Hencespread spectrum effects for the peak frequency when the total noise power is considered, the SNR ofnoises (as well as the signal power) and the power at the DAC is almost constant regardless of the sam-these frequencies is widely spread to other frequen- pling jitter. On the other hand, when only the noisecies, and hence the noise floor increases. However, inside the signal band f /2 is taken into account, thes


SNR degrades significantly due to the sampling jitter e 5V (n 2 1) 2V (n)n in inbecause the noise floor inside the signal band is f fin in

] ]raised by the jitter (in this case the noise peaks at 5 A cos 2p (n 2 1) 2 A cos 2p nS D S Df fs skf 6 f are out of signal band and we do not have tos inf f 1consider them). in in] ] ]S D5 2A sin p sin 2p n 2 .S D S D2f fs s

In case e . 0,n

6. Conclusion e 5V (n) 2V (n 2 1).n in in

In both cases,We have described sampling clock jitter effects in2 2DACs. A formula for the output error power due to e 5 [V (n) 2V (n 2 1)]n in insampling clock jitter is derived and its spectrum

f f 1in in2 2 2characteristics is shown. Also we have investigated ] ] ]S D5 4A sin p sin 2p n 2S D S D2f fits effects on SNR by numerical simulation and s sfound the following: f f 1in in2 2 ] ] ]S D5 2A sin p 1 2 cos 4p n 2 .S DF S DG(i) When the total noise power outside as well as 2f fs sinside the signal band is taken into account, the DAC

SinceSNR remains almost constant regardless of thesampling jitter. f 1in

] ]S DE cos 4p n 2 5 0,(ii) However, when an analog lowpass filter F S DG2fsfollows the DAC and only the noise power inside thesignal band is considered, the DAC SNR degrades as we obtainthe jitter increases and the input signal frequency fin2 2 2becomes higher. Thus the sampling clock jitter is ]E[e ] 5 2A sin p . (A.1)S Dn fsserious for the high speed DAC.

As another DAC timing non-ideality issue, we are Then it follows from Eqs. (3) and (A.1) thatcurrently investigating the characterization of the

fin2 2glitches which are caused by the timing skew inside ]P 5 2A sin p E[ue u],S De nfsthe DAC [2,3] and this result will be reportedelsewhere. and thus the proposition is proved. (Q.E.D.)

ReferencesAcknowledgements

[1] H. Kobayashi, K. Kobayashi, H. Sakayori, Y. Kimura, ADCWe would like to thank M. Morimura, K. Standard and Testing in Japanese Industr, Computer Stan-

Kobayashi, K. Yamashita and K. Wilkinson for dards & Interfaces, Elsevier Publishers 23(1), pp. 57–64(March 2001).valuable discussions. A part of this work was

[2] M. Gustavsson, J.J. Wikner, N.N. Tan, CMOS Data Conver-performed at Gunma University Satellite Ventureters for Communications, Kluwer Academic Publishers,

Business Laboratory. 2000.[3] B. Razavi, Principles of Data Conversion System Design,

IEEE Press, 1995.[4] H. Kobayashi, M. Morimura, K. Kobayashi, Y. Onaya,

Aperture Jitter Effects on Wideband Sampling Systems,Appendix AProceedings of the Instrumentation and Measurement Tech-nology Conference, pp. 880–885, Venice, Italy (May 1999).

This Appendix gives proof of Proposition in [5] H. Kobayashi, K. Kobayashi, Y. Takahashi, K. Enomoto, H.Section 2. Look at Fig. 4, and in case e # 0, Kogure, Y. Onaya, M. Morimura, Finite Aperture Time andn


Sampling Jitter Effects in Wideband Data Acquisition Sys- Dr. Eng. degree in electrical engineering from Waseda Universitytems, Proceedings of the Automatic RF Techniques Group in 1995. In 1982, he joined Yokogawa Electric Corp. Tokyo,56th Measurement Conference – Metrology and Test for RF Japan, where he was engaged in the research and developmentTelecommunications, pp. 115–121, Boulder, Colorado, USA related to measuring instruments and a mini-supercomputer. From(Dec. 2000). 1994 to 1997 he was involved in the research and development of

[6] S.S. Awad, Analysis of accumulated timing-jitter in the time ultra-high-speed ADCs and DACs at Teratec Corporation. He wasdomain, IEEE Trans. Instrum. Measurem. 47 (1) (1998) also an adjunct lecturer at Waseda University from 1994 to 1997.69–74. In 1997 he joined Gunma University and presently is an Associate

[7] M. Shinagawa, Y. Akazawa, T. Wakimoto, Jitter analysis of Professor in Electronic Engineering Department there. Dr.high-speed sampling systems, IEEE J. Solid-State Circ. 25 Kobayashi received the 1994 Best Paper Award from the Japanese(1) (1990) 220–224. Neural Network Society, and he is a member of the IEEE.

[8] W.L. Gans, The measurement and deconvolution of timejitter in equivalent-time waveform samplers, IEEE Trans. Hideyuki KOGURE received the B.S. degree in electronicInstrument. Measurem. 32 (1) (1983) 126–133. engineering from Gunma University, Japan in 2000, and currently

[9] A. Hajimiri, T. Lee, A general theory of phase noise in he is an M.S. course student there. His research interests includeelectrical oscillators, IEEE J. Solid-State Circ. 33 (2) (1998) analog integrated circuit design.179–193.

[10] B. Razavi, A study of phase noise in CMOS oscillators, Takanori KOMURO received his BSEE degree in electronicIEEE J. Solid-State Circ. 31 (3) (1996) 331–343. engineering from the University of Tokyo, and joined Yokogawa

[11] Y.-C. Jenq, Digital-to-analog (D/A) converters with Electronic Works in 1985. He had developed AD converter fornonuniformly sampled signals, IEEE Trans. Instrument. measurement instruments. From 1991 to 1995, he had joined aMeasurem. 45 (1) (1997) 56–59. consortium called Superconductive Sensor Laboratory, at which

[12] Y.-C. Jenq, Direct digital synthesizer with jittered clock, he took part to develop electronic portion of MEG system. In 1995IEEE Trans. Instrument. Measurem. 46 (3) (1996) 653–655. he joined Kanazawa Institute of Technology as researcher. Then

[13] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, K. he had developed SQUID system. In 1997, he joined AgilentKobayashi, Explicit Analysis of Channel Mismatch Effects Technologies Japan Ltd. And he is now developing measuringin Time-Interleaved ADC Systems, IEEE Trans. Circ. Syst. – sub-system for LSI tester. He is a member of the IEEE.I, 48(3) (March 2001) pp. 261–271.

Hiroshi SAKAYORI received his BSEE degree in electronicengineering from Waseda University, and joined Agilent Tech-Naoki KUROSAWA received the B.S. degree in electronicnologies Japan Ltd. (former Hewlett-Packard Japan Ltd.) in 1972.engineering from Gunma University, Japan in 2000, and currentlyHe has developed LCR meters and related products, and semi-he is an M.S. course student there. His research interests includeconductor parameter analyzer. From 1992 to 1997, he hasanalog integrated circuit design.temporarily left Agilent Technologies and has joined a consortiumcalled Teratec, at which he took part to develop high speed dataHaruo KOBOYASHI received the B.S. and M.S. degrees inconversion technology. He is now responsible for developinginformation physics from University of Tokyo in 1980 and 1982measuring sub-system for mixed-signal LSI tester. He is a memberrespectively, the M.S. degree in electrical engineering fromof the Institute of Electrical Engineers of Japan.University of California, Los Angeles (UCLA) in 1989, and the

群馬大学小林研究室

Gunma University Kobayashi Lab

Consideration on Fundamental Performance Limitation

of Analog Electronic Circuits Based on Uncertainty Principle

H. Kobayashi I. Shimizu N. TsukijiM. Arai K. Kubo H. Aoki

Gunma University Oyama National College of TechnologyTeikyo Heisei University

KL-01 13:00-13:25 Nov. 29, 2017 (Wed)

International Conference onMechanical, Electrical and Medical Intelligent System

http://www.google.co.jp/url?sa=i&rct=j&q=&esrc=s&source=images&cd=&cad=rja&uact=8&docid=XxicGsaDCzsPuM&tbnid=2cjxvii7O6Y6aM:&ved=0CAcQjRw&url=http://sophie-in-tokio.blogspot.com/2010/01/owari.html&ei=S7I5VOTZIYSa8QXs8oHQCQ&bvm=bv.77161500,d.dGc&psig=AFQjCNHYkkS5Xy28Z2VuOcAl2KzQaLEzPA&ust=1413153670218700http://www.google.co.jp/url?sa=i&rct=j&q=&esrc=s&source=images&cd=&cad=rja&uact=8&docid=XxicGsaDCzsPuM&tbnid=2cjxvii7O6Y6aM:&ved=0CAcQjRw&url=http://sophie-in-tokio.blogspot.com/2010/01/owari.html&ei=S7I5VOTZIYSa8QXs8oHQCQ&bvm=bv.77161500,d.dGc&psig=AFQjCNHYkkS5Xy28Z2VuOcAl2KzQaLEzPA&ust=1413153670218700

My First Research

Computer with Superconductor (Josephson Device)

Under supervision of Prof. Ko Hara (原宏)at University of Tokyo

Physicist

Undergraduate (Bachelor) course, 4th year

[1] K. Hara, H. Kobayashi, S. Takagi, F. Shiota, “Simulation of a Multi-Josephson Switching Device'', Japanese J. of Applied Physics (1980).

2/42

Research Motivation of This Paper

time

Quantum state 1

Quantum state 2

ΔE

Δt

ΔE Δt ≥ h/(4π) Uncertainty principle

Transition time Δt Time uncertainty

My strong impression :

State transition

3/42

Our Statement

Uncertainty relationships are everywhere in electronic circuits

Ultimately, some would converge to Heisenberg uncertainty principle

in quantum physics.

陰陽思想太極図

Our conjecture

4/42

Contents

● Research Objective

● Uncertainty Principle and Relationship

● Invariant Quantity

● Electronic Circuit Performance Analogyto Uncertainty Relationship and Invariant

● Quantitative Discussion

● Conclusion

5/42

Contents






● Conclusion

6/42

Research Objective

● Our ObjectiveIn analog electronic circuits- Clarify tradeoff among their performance indices - Provide their fundamental limitation

● Our ApproachBased on- Uncertainty principle in quantum mechanics- Uncertainty relationship in signal processing

7/42

Contents






● Conclusion

8/42

Uncertainty Principle in Quantum Mechanics

Δx Δp ≥ h/(4π)

Δt ΔE ≥ h/(4π)

These cannot be proved principle.

x: position, p: momentum.

t: time, E: energy

W. K. Heisenberg

9/42

Uncertainty Relationship in Signal Processing (1)

Sampling frequency : fsSampling period: Ts (= 1/fs)

Δf = fs/N = 1/(Ts N)

Δf Ts = 1/N

● Discrete Fourier Transform (DFT)

Number of DFT points :N

Time & frequency resolution

This can be proved mathematically Relationship

frequencyΔf

0

10/42

Uncertainty Relationship in Signal Processing (2)

● Uncertainty Relationship between Time & Frequency of Continuous Waveform

This can be proved mathematically Relationship

11/42

Contents






● Conclusion

12/42

Importance of Invariant (1)

・Energy conservation law・Mass conservation law・Momentum conservation law・Charge conservation law

Invariant quantity clarify phenomena & characteristics

Conservation Law in Physics :

vmv2v1 m2m1 m1 m2

p1 = m1 v1, p2 = m2 v2 p1’= m1 vm, p2’=m2 vm

p1+ p2 = p1’ + p2’13/42

Importance of Invariant (2)Invariant quantity

clarify phenomena & characteristics

f(x) = x

Fixed-Point in Mathematics :

Compass Polaris

Utility for Voyage

14/42

Contents






● Conclusion

15/42

Gain, Signal Band and Power

● For a given amplifier

Gain ・ bandwidth = constant

Gain → large, bandwidth → narrow

PowerGain ・ Bandwidth

FOM = Technology constant

● Amplifier Performance

→ Converge to uncertainty principle

conjecture

Gai

n [

dB

]

Frequency [Hz]

16/42

ADC Sampling Speed, Resolution and Power

Resolution: Vfull /ΔV = 2n

FOM = Δt・ΔV･P / Vfull

= Δt・P / 2n

Power: P

Sampling period: Δt FOM =

Voltage Resolution・PowerSampling Speed

FOM → Smaller, ADC → Better

Technology constant

→ Converge to uncertainty principleconjecture 17/42

Clock Jitter, Power

Δt ･E ≥ K1

Clock jitter: Δt

Clock generator energy : Epower : P

Design tradeoff

(Δt / T ) P ≥ K1

T

Power → larger, Jitter → smaller

18/42

Noise, Capacitor

p (momentum) ⇔ Q (charge)

v (velocity) ⇔ V (voltage)

m (mass) ⇔ C (capacitor)

Momentum conservation law⇔ Charge conservation law

Uncertainty principleΔx Δp ≥ K ⇔ ΔV f ΔQ ≥ K

⇔ C ΔV2 f ≥ K

ΔV2 = kT/CNoise power

Noise bandwidth: f

Analogy

C → large, Noise → small 19/42

Noise, Capacitor (2)

Vout(t)

R

+ +

--

C

Transfer function

G(s) = 1/ (1 + sRC )

Vin(t)

Ec = (1/2) C Vout

● For a given T=RCthe same gain & phase characteristics for different (R1, C1), (R2, C2), …with R1 C1 = R2 C2 = … = T

Vnoise = kT/ C

● For a given Vout

2

2

C → large, R → smallSame gain & phase characteristicsLow noiseLarge energy

20/42

Capacitor Charge & Loss

I

Vout

C

R

Eloss = (R・I )・I・T= R・C・V・I

Vout = I・T / C

Eloss

Eloss ・T= R・C・Vout

For given R, C, VoutI → small, T → long Eloss → small

Uncertainty relationship

I : Charge CurrentT: Charge Duration

21/42

Waveform Sampling Circuit





[2] M. Arai , H. Kobayashi , et. al.,“Finite Aperture Time Effects in Sampling Circuit,”IEEE 11th International Conference on ASIC, Chengdu (Nov. 2015).

Example ofUncertainty RelationshipIn Signal Processing

22/42

Waveform Sampling

- Finite aperture time (non-zero turn-off time)- Aperture jitter

time

― analog signal

● Sampled point

suffers from

volt

age

23/42

Sampling Circuit

24

時間

電圧

時間

電圧

時間

電圧

時間

電圧

CSW

Vin Vout

CSW

Vin Vout

CSW

Vin Vout

• SW: ON

•Vout(t) = Vin(t)

Track mode

•SW: OFF


Hold mode

Track Hold

time

time

timetime

volt

age

volt

age

volt

age

volt

age

24/42

Finite Aperture Time

25

時間

電圧

時間

電圧

CSW

Vin Vout

CSW

Vin Vout

• SW: ON

•Vout(t) = Vin(t)

Track mode

•SW: OFF


Hold modetime

time

volt

age

volt

age

Finite transition time from track to hold modes

25/42

Analogy with Camera Shutter Speed

Camera: Finite Shutter Speed Sampling Circuit:Finite Aperture Time

Moving Object

Blurred

Input signal

Acquired signal

High frequency

Low pass filtered

Finite Aperture Time Effects in Sampling Circuit14/34 Derived Transfer Function Transfer function in...

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