1

エレクトロニクス産業の将来技術エレクトロニクス産業の将来技術エレクトロニクス産業の将来技術エレクトロニクス産業の将来技術ー　シリコンー　シリコンー　シリコンー　シリコンLSIを中心に　ーを中心に　ーを中心に　ーを中心に　ー

Prof. Takayasu SakuraiCenter for Collaborative Research, and

Institute of Industrial Science,University of Tokyo

E-mail:tsakurai@iis.u-tokyo.ac.jp

1

1 産業を取り巻く環境産業を取り巻く環境産業を取り巻く環境産業を取り巻く環境2 消費電力の危機消費電力の危機消費電力の危機消費電力の危機3 配線の危機配線の危機配線の危機配線の危機4 複雑さの危機複雑さの危機複雑さの危機複雑さの危機5 将来展望将来展望将来展望将来展望

ニューガラスフォーラム　ニューガラスフォーラム　ニューガラスフォーラム　ニューガラスフォーラム　’00/9

T.Sakurai

Silicon Age

Info processing by LSI（（（（Si））））

Info transfer by fibers（（（（SiO２２２２））））

Year

Rel

ativ

e pr

oduc

tion

10000

1000

1960 199019801970

100

102000

Oil

Steel

Silicon

By Yoshio Nishimura

Memory

Processors

Sensors

Communicators

T.Sakurai

World-Wide Semiconductor Market

1980 1990 2000 201010

100

1000

（（（（Billion$））））

by Starc

SemiconductorSteel

Automobile

Electric

GNP

YearYearYearYear

10000

T.Sakurai

World semiconductor market

Data : World semicon market statistics

000020202020404040406060606080808080100100100100120120120120140140140140160160160160180180180180200200200200

1986

1986

1986

1986

1987

1987

1987

1987

1988

1988

1988

1988

1989

1989

1989

1989

1990

1990

1990

1990

1991

1991

1991

1991

1992

1992

1992

1992

1993

1993

1993

1993

1994

1994

1994

1994

1995

1995

1995

1995

1996

1996

1996

1996

1997

1997

1997

1997

1998

1998

1998

1998

1999

1999

1999

1999

2000

2000

2000

2000

2001

2001

2001

2001

YearYearYearYear

Billion $

Billion $

Billion $

Billion $ MOS LogicMOS LogicMOS LogicMOS Logic

MOS uPMOS uPMOS uPMOS uP

MOS MemoryMOS MemoryMOS MemoryMOS Memory

Digital BipolarDigital BipolarDigital BipolarDigital Bipolar

AnalogAnalogAnalogAnalog

DiscreteDiscreteDiscreteDiscrete

T.Sakurai

日本の半導体市場日本の半導体市場日本の半導体市場日本の半導体市場

http://www.eiaj.or.jp/japanese/press/pre64/index_2.htm

T.Sakurai

地域別半導体メーカシェア地域別半導体メーカシェア地域別半導体メーカシェア地域別半導体メーカシェア

日本日本日本日本

米国米国米国米国

欧州欧州欧州欧州

その他その他その他その他

60606060

50505050

40404040

30303030

20202020

10101010

000081 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

(%)(%)(%)(%)

1980年年年年

T.Sakurai

Moore’s Law

10K

1M

100M

10G

1001970 1980 1990 2000

1M4M

16M64M

256M1G

2GD

evic

e co

unt p

er c

hip

Year

DRAMμμμμP

2010

Des

ign

rule

(µ µµµm

)

0.01

0.1

1

10

T.Sakurai

微細加工技術の進展微細加工技術の進展微細加工技術の進展微細加工技術の進展

1995199519951995 2000200020002000 2005200520052005 2010201020102010

1000100010001000万万万万

1111億億億億

10101010億億億億

年年年年

0.010.010.010.01

0.10.10.10.1

1111

チップ当たりのトランジスタ数

チップ当たりのトランジスタ数

チップ当たりのトランジスタ数

チップ当たりのトランジスタ数

ゲート線幅

ゲート線幅

ゲート線幅

ゲート線幅( (((ミクロン

ミクロン

ミクロン

ミクロン) )))

T.Sakurai

System LSI for Next Generation Games

Clock freq. 300MHz

　　　　10M transistors

　　　　Graphics synthesizer integrate

40M tr. With embedded DRAM

Memory bandwidth 3.2GB/s

Floating operation 6.2GFLOPS/sec

3D CG 6.6M polygon/sec

MPEG2 decode

T.Sakurai

Limit of Miniturization

Conventional I-V curve at 0.04µm (Even down to 0.014µm)　　　　

0.04µm MOSFET

0.0 0.4 0.8 1.2 1.6 2.00.00

0.21

0.42

0.63 Vg = 2.0 V

Vg = 1.6 V

Vg = 1.2 V

Vg = 0.8 V

Gate Length = 40 nm

Dra

in C

urre

nt[m

A/µ

m]

Drain Voltage [V]

0.04µm

M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, "Sub-50nm gate Length N-MOSFETs with 10 nm Phosphorus Source and Drain Junctions", IEDM Technical Digest, pp. 119 -122, 1993.H. Kawaura, T. Sakamoto, Y. Ochiai, J. Fujita, and T. Baba, "Fabrication and Characterization of 14-nm-Gate-Length EJ-MOSFETs", Extended Abstracts of SSDM, pp.572-573, 1997.

T.Sakurai

MOSトランジスタに使われる材料トランジスタに使われる材料トランジスタに使われる材料トランジスタに使われる材料

Drain Source

Gate

0.2micron

配線間、素子間絶縁：配線間、素子間絶縁：配線間、素子間絶縁：配線間、素子間絶縁：

SiO2（（（（なるべく低誘電率に）なるべく低誘電率に）なるべく低誘電率に）なるべく低誘電率に）

基板：　基板：　基板：　基板：　Si ゲート：　多結晶ゲート：　多結晶ゲート：　多結晶ゲート：　多結晶Si　　　　→→→→ 高融点金属高融点金属高融点金属高融点金属

配線：　配線：　配線：　配線：　Al →→→→ Cuゲート絶縁膜：ゲート絶縁膜：ゲート絶縁膜：ゲート絶縁膜：SiO2（（（（なるべく高い誘なるべく高い誘なるべく高い誘なるべく高い誘

電率に）電率に）電率に）電率に）

T.Sakurai

Scaling Law

Drain Source

Gate

0.2micron

Drain SourceGate

0.2micronSize 1/2

Size x1/2Voltage x1/2Electric Field x1Speed x3Cost x1/4

Power density x1.6RC delay/Tr. delay x3.2Current density x1.6Voltage noise x3.2Design complexity x4

Favorable effects Unfavorable effects

T.Sakurai

Three crises in VLSI designs

Power crisis

Interconnection crisis

Complexity crisis

T.Sakurai

Ever Increasing VLSI Power(Power consumption of processors published in ISSCC)

959085800.01

0.1

1

10

100

Year

Pow

er (W

)x4 / 3years

T.Sakurai

Year

Volta

ge [V

]

Pow

er p

er c

hip

[W]

VDD

cur

rent

[A]

VDD, Power and Current Trend

1998 2002 2006 2010 20140

0.5

1

1.5

2

2.5

0 0

200 500

Current

Power

Voltage

International Technology Roadmap for Semiconductors 1998 update sponsored by the Semiconductor Industry Association in cooperation with European Electronic Component Association (EECA) , Electronic Industries Association of Japan (EIAJ), Korea Semiconductor Industry Association (KSIA), and Taiwan Semiconductor Industry Association (TSIA)

T.Sakurai

IT from anywhere by anybody

E-cashingE-tradingE-banking

Cell phoneTecketingReservation

Home automationGame on netEntertainment

InternetWeb brouseWeb TVE-mail

PDAScheduleAddress book

Computer centric →→→→Communication centric, Display centric

Low-power and wireless are the keys

T.Sakurai

Performance Requirements for MultimediaRequired Performance (MOPS)

FAX/Modem

10 100 1000 10000

SoundSpeech recognition

TV conf. (H.324...)MPEG1 decoding

MPEG1 encoding

MPEG2 encoding

2D/3D graphics

100000

MPEG2 decoding

HDTV decoding

Future

HDTV encoding

Present

T.Sakurai

What sets the technology trend?

NMOS CMOS

Bipolar CMOS

Cost up

Speed downNot cost nor speed but power set the technology trend.

Integration can achieve low cost and high speed as a system.

T.Sakurai

Power & Delay Dependence on VDD & VTH

Power : P = pt •fCLK •CL •VDD + I0 •10 •VDD 2

V thS

(αααα=1.3)

k • CL • VDD

(VDD - Vth)ααααDelay =

k•QI

=

12

34

-0.400.40.8

00.2

0.4

0.6

0.8

1x 10-4

Vth (V)

VDD(V)

Pow

er (W

)

A

B

12

34

-0.400.40.8

0

1

2

3

4

5x 10

-10

Del

ay (s

)

Vth (V)VDD(V)

A B

T.Sakurai

Measurement of 32bit full adder

Photograph of 32bit FA0.3µµµµm CMOS

0000 0.50.50.50.5 1111 1.51.51.51.5 22220000

1111

2222

3333

4444

Norm

aliz

ed

Norm

aliz

ed

Norm

aliz

ed

Norm

aliz

ed t ttt

pd

pdpd

pd

VDD [V]

90ºC

50ºC

20ºC Measured

K.Kanda, K.Nose, H.Kawaguchi, and T.Sakurai,"Design Impact of Positive Temperature Dependence of Drain Current in Sub 1V CMOS VLSI's",CICC99, pp.563-566, May 1999.

T.Sakurai

Transient response of chip temperature

0000 10101010 20202020 30303030 40404040 5050505020202020

60606060

100100100100

140140140140

180180180180

Time [sec]Time [sec]Time [sec]Time [sec]

Tem

pera

ture

[ºC

]

VDD =0.5V, VTH = 0.2V

VDD = 3.3V, VTH = 0.5V

• Same package• Same power at room temp.

Better package is needed to avoid thermal runaway in low voltage.

K.Kanda, K.Nose, H.Kawaguchi, and T.Sakurai,"Design Impact of Positive Temperature Dependence of Drain Current in Sub 1V CMOS VLSI's",CICC99, pp.563-566, May 1999.

T.Sakurai

Ultra Low-Voltage Operation

inverter (T=300K)

2nand(T=300K)

inverter (T=77K)

Vin (V)

Vout

(V)

50mV

25mV

100mV360mV

140mV

J.Burr&J.Shott,"A 200mV Self-Testing Encoder/Decoder using Stanford Ultra-Low-Power CMOS",ISSCC94, pp.84-85.

((((Stanford Univ.)Stanford Univ.)Stanford Univ.)Stanford Univ.)

T.Sakurai

Approach to low-power LSI

Example of MPEG2 decodingProcessor (software)～～～～25W

DSP～～～～4W

Dedicated sytem LSI (SW/HW)～～～～0.7W

Low

-pow

er

Hig

h fle

xibi

lity

T.Sakurai

Homogeneous vs. Heterogeneous

SpecialEngine

Homogeneous Architecture

(High flexibility)

Heterogeneous Architecture(System LSI)

(Low-power, more efficient)

MPUMPUMPUMPU

Memory

I/F, Analog

MPUMPUMPUMPU

I/F, Analog

MPUDSP

Memory

T.Sakurai

DRAM Embedding

DRAM Processor System LSI

Two orders of magnitude improvement in bandwidth and power

K.Sawada, T.Sakurai, et al, "A 72K CMOS Channelless Gate Array with Embedded 1Mbit Dynamic RAM," in Proc. CICC'88, pp.20.3.1-20.3.4, May 1988.

T.Sakurai

DRAM混載混載混載混載

ドレインドレインドレインドレイン ソースソースソースソース

ゲートゲートゲートゲート

0.2ミクロンミクロンミクロンミクロン（（（（0.0002ミリ）ミリ）ミリ）ミリ）

トランジスタトランジスタトランジスタトランジスタ DRAMのメモリセルのメモリセルのメモリセルのメモリセル

・異なる技術を結合・異なる技術を結合・異なる技術を結合・異なる技術を結合・テストは・テストは・テストは・テストはBISTBISTBISTBISTをををを活用活用活用活用・自動モジュールジェネレータ・自動モジュールジェネレータ・自動モジュールジェネレータ・自動モジュールジェネレータ

T.Sakurai

Future trend of NLOGIC and NMEMORY

1999 2002 2005 2008 2011106

107

108

109

1010

NCHIPNMEMORYNLOGIC

97%80%NMEMORY

NCHIP

3%

2011

20%

1999

NLOGIC

NCHIP

Year

# of

tran

sist

ors

T.Sakurai

Application slicing and software feedback loop in Voltage Hopping

S.Lee and T.Sakurai, “Run-time Power Control Scheme Using Software Feedback Loop for Low-Power Real-time Applications,”ASPDAC'00, A5.2, pp.381~pp.386, Jan. 2000.S.Lee and T.Sakurai, “Run-time Voltage Hopping for Low-power Real-time Systems,” DAC'00, June 2000.

3

1 2 3 N...4

TR3

TR1TR2

TR4

TSF = Time constraint of sync frame

1 2TC2TC3

TTAR3

fVAR = f1 = fCLK TTD

TTD

fVAR = f2 = fCLK/2

fVAR = f3 = fCLK/3

fVAR = f4 = fCLK/4

TTD

TTD

TL3,f1 = TTD + TW3

TL3,f2 = TTD + TW3 x 2

TL3,f4 = TTD + TW3 x 4TL3,f3 = TW3 x 3

Clock frequency for the previous timeslot was f3.

Processor coreProcessor core

Voltagefrequencycontroller

Voltagefrequencycontroller

Clock & VDDClock & VDDControl info

T.Sakurai

Run-time Voltage Hoppingreduces power to less than 1/10

MPEG-4 video encoding

Transition Delay TTD (ms)0.0 0.2 0.4 0.6 0.8 1.0

Nor

mal

ized

Pow

er P

/PFI

X

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

RVH: 2 levels (f,f/2)RVH : 3 levels (f,f/2,f/3)RVH : 4 levels (f,f/2,f/3,f/4)RVH : infinite levelspost-simulation analysis

SH-4

Clock

VDDSH-4 Modified

Clock

VDD

T.Sakurai

Transient voltage waveform

Simulation resultsTime (ms)0 10 20 30 40 50 60 70

Nor

mal

ized

Sup

ply

Volta

ge V

/VD

D

0.0

0.5

1.0proposed: 2 levels (f,f/2)proposed: 3 levels (f,f/2,f/3)proposed: infinite levelspost-simulation analysis

1 sync frame = 33 timeslots = 66.66667 ms

MPEG-4 video encodingMPEG-4 video encoding

T.Sakurai

Three crises in VLSI designs

Power crisis

Interconnection crisis

Complexity crisis

T.Sakurai

Complex interconnect

T.Sakurai

Advances in interconnection technology

Interconnection in 1985 Interconnection in 1998

T.Sakurai

Interconnect determines cost & perf.

P: Power, D: Delay, A: Area, T:Turn-around

0

20

40

60

80

100

Pow

er [%

]Ctransistor

5

6

7

8

'95 2000 '5 '10

# of

int.

laye

rs

Year

(SIA'97)

0

20

40

60

80

100

Del

ay [%

]

(F.O.=3, Al=1mm)

0

20

40

60

80

100

Proc

ess

step

s [%

]

'95 2000 '5 '10Year

'95 2000 '5 '10Year

'95 2000 '5 '10Year

# of layers

Cint

RC delay

Int.

Tr's

Cgate

T.Sakurai

Interconnect parameters trend

0

1

2

3

4

1996 2000 2004 2008 2012Year

εεεε r

ρρρρ[ΩΩΩΩ • cm]

Aspect ratio

Width [x0.1μμμμm]

Al Cu

Semiconductor Industry Association roadmaphttp://notes.sematech.org/1997pub.htm

T.Sakurai

RC delay and gate delay

1996 2000 2004 2008 201210-12

10-11

10-10

10-9

10-8

Year

Clock period

Gate delay

3mm

1mm

100µm

50µm

Del

ay (s

ec)

T.Sakurai

RC delay of global interconnections

1996 2000 2004 2008 201210-10

10-9

10-8

10-7

10-6

Year

Clock period

Minimum cross-section interconnect

Del

ay (s

ec)

6µm x 6µm cross-section interconnectGlobal interconnect

Chip 18mm x 18mm 27mm x 27mm

T.Sakurai

Buffered interconnect delay

1998 2002 2006 2010 201410-11

10-10

10-9

10-8

Gate delay

1um x 1um chip long

Clock period (global)

Clock period (local)

1um x 1um chip long buffered

Year

Del

ay (s

ec)

T.Sakurai

Coupling among Interconnection

Difficulty in checking setup and hold time.

00

0.2

0.4

0.6

0.8

1

0.1µm spaceLength 3mm

0→→→→1 0→→→→1 0→→→→10→→→→0 0→→→→1 0→→→→01→→→→0 0→→→→1 1→→→→0

Time (ns)

Volta

ge (A

.U.)

5 10

In-phase

Out-phaseNo change

T.Sakurai

Interconnect Cross-Section and Noise

Unscaled / anti-scaled• Clock• Long bus• Power supply

Scaled interconnect• Signal

1V 50W -> 50A current5% noise -> 0.05V noise -> 1mΩΩΩΩ sheet R -> 15µm thick CuArea pad + package, or thick layer on board is needed.

T.Sakurai

Three crises in VLSI designs

Power crisis

Interconnection crisis

Complexity crisis

T.Sakurai

VLSI Design in 2010

Designing a map of 10m wide roadsfor a world atlas

T.Sakurai

Complexity vs. Productivity

System LSI design complexity increases faster than productivity. (http://notes.sematech.org/97melec.htm)

2000 2002 2004 2006 2008 2010 20121

10

100

1000Design complexity

Productivity improved with lots of development

Productivity improved with current rate

T.Sakurai

Overcome complexity crisis

MPU Core

Cache

ROMRAM

MPEG CoreUSB Core

ProprietaryLogic

IP (A inc.)IP (B univ.)IP (C inst.)IP (D semi.)

IP ; CPU, DSP, memories, analog, I/O, logic..HW/FW/SW

• Re-use and sharing of design• Design in higher abstraction

T.Sakurai

Issues in System-on-Chip

• Un-distributed IP’s (i.e. CPU, DSP of a certain

company)

• Huge initial investment for masks & development

• IP testability, upfront IP test cost

• Process-dependent memory IP’s

• Difficulty in high precision analog IP’s due to noise

• Process incompatibility with non-Si materials and/or

MEMS

T.Sakurai

Super-connect

Bandwidth

0.1

1

10

100

Design rule Power@1GB/s

Area

102

103

104

105

[µµµµm] [mW] [GB/sec]

[µµµµm2

/bit]

Super-connect

Off-chip On-chip

1

10

100

1000

Cost/line

[AU]

10

1000[day]

100

Turn-aroundtime

1

10

100

1000

1

10

100

1000

T.Sakurai

System-in-Package (SIP)

Chip

Substrate

SolderResistor Capacitor Inductor

Two-layer Al TaSi SiO2 Si3N4 Polyimide

K.L.Tai, “System-In-Package (SIP): Challenges and Opportunities,” ASPDAC, pp.191-196, Jan. 2000

T.Sakurai

System on a chip

3-D assembly

3-Dimensional assembly

MPU Core

DRAM

Logic

Analog Chip

MPU Core

Cache

ROMLogic

AnalogUSB Core

DRAM• Smaller area• Shorter interconnect• Optimized process for

each die (Analog, DRAM, MEMS…)

• Good electrical isolation• Through-chip via

• Heat dissipation is an issue

Cache

ROMUSB

Heat spreader/Heat pipe

T.Sakurai

Micro-machined mechanical switch

G.Weinberger, “The New Millennium: Wireless Technologies for a Truly Mobile Society,” ISSCC, pp.20-24, Feb. 2000.

T.Sakurai

Silicon MEMS motor

マイクロマシン技術で作ったマイクロマシン技術で作ったマイクロマシン技術で作ったマイクロマシン技術で作った0.1ミリのモーターミリのモーターミリのモーターミリのモーター東京大学、生産技術研究所、藤田博之教授提供東京大学、生産技術研究所、藤田博之教授提供東京大学、生産技術研究所、藤田博之教授提供東京大学、生産技術研究所、藤田博之教授提供

T.Sakurai

Silicon MEMS microphone

M.Pinto, “Atoms to Applets: Building Systems ICs in the 21st Century,” ISSCC, pp.26-30, Feb. 2000.

10umWill soon exceed the performance of the best commercial microphones, yet be inexpensive and potentially integrated with on-chip electronics.

T.Sakurai

DRAM製造設備投資製造設備投資製造設備投資製造設備投資

0000

200200200200

400400400400

600600600600

8008008008001000100010001000

1200120012001200

1400140014001400

1600160016001600

1800180018001800

2000200020002000

1M1M1M1M 4M4M4M4M 16M16M16M16M 64M64M64M64M 256M256M256M256M 1G1G1G1G

世代世代世代世代

億円

億円

億円

億円

資料：半導体産業研究所資料：半導体産業研究所資料：半導体産業研究所資料：半導体産業研究所

T.Sakurai

LSI in 2014Year Unit 1999 2014 Factor

Design rule µm 0.18 0.035 0.2Tr. Density /cm2 6.2M 390M 30Chip size mm2 340 900 2.6Tr. Count per chip (µP) 21M 3.6G 170DRAM capacity 1G 1T 256Local clock on a chip Hz 1.2G 17G 14Global clock on a chip Hz 1.2G 3.7G 3.1Power W 90 183 2.0Supply voltage V 1.5 0.37 0.2Current A 60 494.6 8Interconnection levels 6 10 1.7Mask count 22 28 1.3Cost / tr. (packaged) µcents 1735 22 0.01Chip to board clock Hz 500M 1.5G 3.0# of package pins 810 2700 3.3Package cost cents/pin 1.61 0.75 0.5

International Technology Roadmap for Semiconductors 1998 update sponsored by the Semiconductor Industry Association in cooperation with European Electronic Component Association (EECA) , Electronic Industries Association of Japan (EIAJ), Korea Semiconductor Industry Association (KSIA), and Taiwan Semiconductor Industry Association (TSIA) , International Technology Roadmap for Semiconductors: 1999 edition. Austin, TX:International SEMATECH, 1999.

T.Sakurai

Possible electronic system in 2014

• Sensors/actutors

• 0.035µm 3.6G Si FET’s with VTH & VDD control

• Locally synchronous 17GHz clock, globally asynchronous

• Chip / Package / Board system co-design for power lines, clocks, and long wires (super-connect)

MPU, LogicConfigurable units

Sensors Variousmemories

Micro-actuatorsAnalog

T.Sakurai

Retinal Prosthesis

Prosthesis Prosthesis -- DualDual IntraocularIntraocular UnitsUnits

Courtesy: Prof. Wentai Liu (North Carolina Univ.)http://www.ece.ncsu.edu/erl/faculty/wtl_data/retina.html

T.Sakurai

Retinal Prosthesis

Bio-Compatible - not toxic to neurons Large amount of current without causing irreversible electrochemical reactions

400 uC/cm2 for Platinum and 3 mC/ cm2 for Iridium Not dissolve as a result of simulation Two metal meet the above demands - Platinum and Iridium Substrate for array - Silicone, Silicon, Polyimide, etc

Platinum (5x5) on Silicone by Janusz

Electrodes ArrayElectrodes Array

T.Sakurai

Chip + Electrode Array onChip + Electrode Array on PolyimidePolyimide

Courtesy: Prof. Wentai Liu (North Carolina Univ.)http://www.ece.ncsu.edu/erl/faculty/wtl_data/retina.html

Possibly super-connect

T.Sakurai

Cochlear Implants

22 Electrodes Spatially Attached at

Cochlear (low pitch sound at the apex)

Power and Signals by Carrier Radio Frequency

Retinal Prosthesis