デザイン・ガイド: TIDA-01622 30W/in3 94%効率、65W USB Type … · 2019. 7. 12. ·...

CC1

NV6117

CSD17578Q3

UCC24612-1

VOUT

UCC28780 ATL431

NV6115

EMI Filter and

Rectifier Bridge

85 VAC§�265 VAC

Copyright © 2018, Texas Instruments Incorporated

ISO7710

Opto

GND

TPS25740B

TPD1E05U06

1JAJU496B–February 2018–Revised April 2019

TIDUDW2 翻訳版 — 最新の英語版資料 http://www-s.ti.com/sc/techlit/TIDUDW2Copyright © 2018–2019, Texas Instruments Incorporated

30W/in3、94%効率、65W USB Type-C™ PD AC/DCアダプタのリファレンス・デザイン

参参考考資資料料

デデザザイインン・・ガガイイドド: TIDA-0162230W/in3、、94%効効率率、、65W USB Type-C™ PD AC/DCアアダダププタタののリリフファァレレンンスス・・デデザザイインン

概概要要

この完全テスト済みのUSB Power Deliveryリファレンス・デザインは、ノートパソコン用アダプタやスマートフォンの充電

器に適した、入力電圧範囲の広い(85～265V AC)高効率、高電力密度のAC/DCアダプタ・ソリューションです。このリファレンス・デザインは、TIの最新ACFコントローラUCC28780が制御するアクティブ・クランプ・フライバック・トポロジを、1次電源段として採用しています。またTIのPDソース・コントローラTPS25740Bを使用して、PD 2.0の全機能を実現します。極めて高いスイッチング周波数で94%のピーク効率を達成しているほか、電力密度も30W/in3に向上し、従来のソリューションに比べてはるかに高くなってい

ます。

リリソソーースス

TIDA-01622 デザイン・フォルダUCC28780 プロダクト・フォルダUCC24612 プロダクト・フォルダTPS25740B プロダクト・フォルダATL431 プロダクト・フォルダISO7710 プロダクト・フォルダCSD17578Q3A プロダクト・フォルダTPD1E05U06-Q1 プロダクト・フォルダ

E2E™エキスパートに質問

特特長長

• 高効率 (ピーク値 94%)

• 高い電力密度 (30W/in³)

• 無負荷時の低消費電力 (60mW)

• 20VOUT、0.25W 出力で軽負荷時の入力電力が小さい(0.5W)

• USB PD 2.0 規格に完全準拠、5V/3A、9V/3A、15V/3A、20V/3.25A の出力に対応

• アクティブ・クランプ・フライバック + SR トポロジ

• 小サイズ (62mm×28.6mm×18.4mm)

アアププリリケケーーシショョンン

• ノート PC 向け電源アダプタの設計

• モバイル向け充電器の設計

• その他の AC/DC アダプタ/電源

• 産業用AC/DC

http://www-s.ti.com/sc/techlit/TIDUDW2.pdfhttp://www.tij.co.jp/tool/jp/TIDA-01622http://www.ti.com/product/UCC28780http://www.ti.com/product/UCC24612http://www.ti.com/product/TPS25740Bhttp://www.ti.com/product/ATL431http://www.ti.com/product/ISO7710DRhttp://www.ti.com/product/CSD17578Q3Ahttp://www.ti.com/product/TPD1E05U06-Q1http://e2e.ti.comhttp://e2e.ti.com/support/applications/ti_designs/http://www.ti.com/solution/notebook_pc_power_adaptershttp://www.ti.com/solution/mobile-wall-charger-design?keyMatch=mobile%20wall%20charger&tisearch=Search-EN-Everythinghttp://www.ti.com/solution/other_acdc_adapterspsuhttp://www.ti.com/solution/industrial_acdc_480w

VoutPFC Stage

Isolated DC/DC Stage

USB PD Control Stage

Filter and Rectifier

AC Mains

System Description www.tij.co.jp

2 JAJU496B–February 2018–Revised April 2019



使用許可、知的財産、その他免責事項は、最終ページにあるIMPORTANT NOTICE (重要な注意事項)をご参照くださいますようお願いいたします。

1 System Description

Smartphones and notebook PCs need adapters to charge their batteries. A USB-PD function makescharging convenient because the smartphone charger and notebook PC adapter are combined to oneconverter. High efficiency and high power density are required for the adapter to save power and makethe device easier to carry. A smartphone charger or notebook adapter is an AC/DC converter. 図 1 showsa typical diagram of this converter. When the output power is lower than 75 W, a PFC stage is notrequired.

図図 1. Typical Diagram of USB-PD Adapter

This adapter reference design operates over a wide input voltage range from 85-V to 265-V AC and mustbe able to power different equipment with different voltage demands automatically. When faults such asover-current, over-power, and over-voltage happen, the adapter reacts quickly to protect the terminaldevice.

This reference design is a high efficiency, high power density, 65-W output power USB-PD 2.0 AC/DCadapter that achieves a peak efficiency of 94% and a 30-W/in3 power density. The input voltage rangesfrom 85-V to 265-V AC and the output is fully compatible with USB PD2.0 standard with 5-V/3-A, 9-V/3-A,15-V/3-A, and 20-V/3.25-A outputs. When an over-current, short-circuit, or over-power event occurs, thisadapter reference design can cut off the output and recovery automatically. With over-voltage, the adapteris latched to avoid further damage to the terminal devices. Also, this adapter meets low no-load powerconsumption, which is less than 60 mW.

This converter operates at a high switching frequency of 600 kHz (max), which helps decrease the size ofthe transformer and capacitors. Furthermore, the EMI filter is much simpler and smaller than lowfrequency converters.

http://www.tij.co.jphttp://www-s.ti.com/sc/techlit/TIDUDW2.pdf

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1.1 Key System Specifications

表表 1. Key System Specifications

PARAMETER TEST CONDITION MIN TYP MAX UNITINPUT CHARACTERISTICSInput voltage (VINAC) 85 230 265 V ACFrequency (fLINE) 47 50 63 HzBrown-in voltage 75 V ACBrownout voltage 70 V ACOUTPUT CHARACTERISTICS

Output voltage

5-V sink attached 4.95 5 5.05 V9-V sink attached 8.95 9 9.05 V15-V sink attached 14.9 15 15.1 V20-V sink attached 19.85 20 20.15 V

Output current

5-V sink attached 3 A9-V sink attached 3 A15-V sink attached 3 A20-V sink attached 3.25 A

Load regulation

5-V sink attached 0.2 0.5 %9-V sink attached 0.3 0.5 %15-V sink attached 0.6 1.0 %20-V sink attached 0.8 1.0 %

Ripple and noise

5-V sink attached 130 mV9-V sink attached 140 mV15-V sink attached 156 mV20-V sink attached 204 mV

Maximum output power 65 WSYSTEM CHARACTERISTICS

Peak efficiencyLow line 93.8 %High line 94.0 %

Operating ambient temperature 64.5 °CStandards and norms EMI IEC 61000-2-3 Class D, EN 55032 class BBoard form factor 62 mm × 28.6 mm × 18.4 mm


CC1

NV6117

CSD17578Q3

UCC24612-1

VOUT

UCC28780 ATL431

NV6115

EMI Filter and

Rectifier Bridge

85 VAC§�265 VAC

Copyright © 2018, Texas Instruments Incorporated

ISO7710

Opto

GND

TPS25740B

TPD1E05U06

System Overview www.tij.co.jp




2 System Overview

2.1 Block Diagram

図 2 shows the high-level block diagram of the circuit. The main topology of this reference design is activeclamp flyback (ACF), which is controlled by TI’s new ACF controller UCC28780. The synchronize rectifiercontroller UCC24612-1 controls the synchronize rectifier MOSFET for better efficiency performance. Themain switching devices are NV6115 and NV6117 GaN devices from Navitas Semiconductor, Inc. The TIUSB-PD source controller TPS25740B controls the output fully compatible with the USB-PD 2.0 standardwith 5-V/3-A, 9-V/3-A, 15-V/3-A, 20-V/3.25-A outputs.

図図 2. Block Diagram of TIDA-01622

2.2 Highlighted Products

2.2.1 UCC28780

The UCC28780 is a high-frequency active-clamp flyback controller that enables high-density AC/DC powersupplies that comply with stringent global efficiency standards. Zero voltage switching (ZVS) is achievedover wide operating range with an advanced auto-tuning technique, adaptive dead time optimization, andvariable switching frequency control law. Along with multimode control that changes the operation basedon input and output conditions, the UCC28780 controller enables high efficiency without the risk of audiblenoise. The controller has a variable switching frequency of up to 1 MHz and accurate programmable OPP,which provides consistent thermal design power across a wide line range. This consistent power meanspassive components can be further reduced and enable high power density.

Key features for this device include the following:

• Configurable with external Si or GaN FETs

• Adaptive burst control for light-load efficiency with low output ripple and no audible noise

• Secondary-side regulation allows for dynamically scalable output voltage

• Internal soft start

• Brownout detection without direct line sensing


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• Fault protections: Internal overtemperature, output overvoltage, overcurrent, short circuit, and pin fault

• NTC resistor interface with external enable

2.2.2 UCC24612

The UCC24612 is a high-performance controller and driver for standard and logic-level N-channelMOSFET power devices used for low-voltage, secondary-side synchronous rectification. The combinationof controller and MOSFET emulates a near-ideal diode rectifier. This solution not only directly reducespower dissipation of the rectifier, but also indirectly reduces primary-side losses as well due tocompounding of efficiency gains. Using drain-to-source voltage sensing, the UCC24612 is ideal for ACFpower supplies. This device is available in a 5-pin SOT-23-5 package.


• Up to 1-MHz operating frequency

• VDS MOSFET sensing

• 4-A sink, 1-A source gate-drive capability

• Micro-power sleep current for 90+ designs

• Automatic light-load management

• Synchronous wake-up from sleep and light-load modes

• Adaptive minimum off time for better noise immunity

• 16-ns typical turnoff propagation delay

• 9.5-V gate drive clamp levels for minimum driving loss

2.2.3 TPS25740B

Without any firmware configuration, the TPS25740B implements a source that is certified for USB-PD 2.0version 1.2 and Type-C revision 1.2 designed to minimize time to market. The device offers four differentvoltages using USB-PD. The voltages and currents advertised are easily configured and the device canselect the voltage from the power supply based on the voltage requested by the attached sink. The deviceautomatically handles discharging the VBUS output per USB-PD requirements.


• Pin-selectable voltage advertisement:

– 5 V, 9 V, 12 V, and 15 V

– 5 V, 9 V, 15 V, and 20 V

• Pin-selectable peak power settings:

– Eight options 18 W to 100 W

• High voltage and safety integration:

– OVP, OCP, OTP, and VBUS discharge

– IEC 61000-4-2 protection on CC1 and CC2

– Input pin for fast shutdown under fault

– Control of external N-channel MOSFET

– Three-pin external power supply control

– Wide VIN supply: 4.65 V to 25 V






• Below 10-μA quiescent current when unattached

• Port attachment indicator

• Self-directed port power management for dual-port applications

2.2.4 ATL431

The ATL431 is a three-terminal adjustable shunt regulator with specified thermal stability over applicableautomotive, commercial, and industrial temperature ranges. The output voltage can be set to any valuebetween VREF (approximately 2.5 V) and 36 V with two external resistors. The regulator has a typicaloutput impedance of 0.05 Ω. The operation current is as low as 35 µA (min), keeping the power loss at aquite low value.

2.2.5 ISO7710

The ISO7710 device is a high-performance, single-channel digital isolator with 5000-VRMS (DW package)and 3000-VRMS (D package) isolation ratings per UL 1577. This device is also certified by VDE, TUV, CSA,and CQC. The ISO7710 device provides high EMI and low emissions at a low power consumption whileisolating CMOS or LVCMOS digital I/Os. The isolation channel has a logic input and output bufferseparated by a silicon dioxide (SiO2) insulation barrier. In the event of input power or signal loss, defaultoutput is high for a device without suffix F and low for a device with suffix F.

2.2.6 CSD17578Q3A

The CSD17578Q3A is a 30-V NexFET™ Power MOSFET with a very low RDSon of 6.3 mΩ and a SON 3.3-mm×3.3-mm package. In this reference design, this device is used as a PD function switch for its low costand RDSon.

2.2.7 TPD1E05U06-Q1

The TPD1E05U06-Q1 is a one-channel ESD protection diode for speeds up to 6 Gbps. The ultra-lowloading capacitance makes this device ideal for protecting any high-speed signal applications includingUSB 2.0 or 3.0, HDMI 1.4 or 2.0, SIM cards, and so on.

2.3 System Design Theory

This reference design operates over a wide input voltage ranges from 85-V to 265-V AC and is fullycompatible with the USB-PD 2.0 standard with 5-V/3-A, 9-V/3-A, 15-V/3-A, and 20-V/3.25-A outputs. Thepower supply operates as ACF topology controlled by the UCC28780. And the output voltage is selectedby TPS25740B based on the voltage requested by the attached sink. The peak efficiency achieves 94% ata 230-V AC input and 93% at a 115-V AC input. The high switching frequency helps to decrease thetransformer and EMI filter size to achieve a high power density.


� �dera DS _ GaN BULK _maxPS _max

OUT _max

1 K V VN 6.87

V

� u �

out _ maxhold _ up

2 2BULK _RUN Brownout

2 PT

CV V

uu

K

�





2.3.1 ACF Converter Design

ACF is a two-switch topology that achieves soft switching and recovers leakage inductance energy.Compared with traditional ACF in continuous conduction mode (CCM), ACF in critical conduction mode(CrCM) uses the magnetizing inductance instead of leakage inductance to store ZVS energy. Asmagnetizing inductance is much larger than leakage inductance, only a small amount of negativemagnetizing current is required to achieve full ZVS soft switching. By controlling the amount of negativemagnetizing current, ZVS can easily be achieved from zero to full load. With proper design, the outputrectifier achieves zero current switching (ZCS) during turnoff. All these features make ACF successful athigh power density and efficiency adapter applications.

表表 2. ACF Design Goal Parameters

PARAMETER TEST CONDITION MIN TYP MAX UNITINPUT CHARACTERISTICSInput voltage (VINAC) 85 230 265 V ACBrown-in voltage 75 V ACBrownout voltage 70 V ACOUTPUT CHARACTERISTICSOutput voltage 5 20 VMaximum output power 65 WBurst mode load threshold 60 %

Peak efficiencyLow line 93.8 %High line 94.0 %

Load regulation 1.0 %

2.3.1.1 Bulk Capacitor Calculation

The minimum value of a bulk capacitor is determined by the hold-up time (Thold_up). A larger bulk capacitorvalue means a larger capacitor size; therefore, to maintain a high power density, the bulk capacitor valueis determined by the hold-up time.

(1)

Where:

• POUT_max is the maximum output power

• VBULK_RUN is the typical DC voltage on a bulk capacitor

• VBrownout is the DC brownout voltage

2.3.1.2 Transformer Turns Ratio Calculation

The transformer turns ratio is determined by the voltage rating of GaN and synchronous rectificationMOSFET. The voltage stress of GaN NV6117 is 650 V and the SR MOSFET is a 150-V Si device.Therefore, the maximum and minimum turns ratio can be calculated separately using 式 2 and 式 3,respectively.

(2)

Where:


NPNS

Na1

Na2

2 2max BIULK _ min

mSW _ min OUT _ max

D VL 79 H

2 f P

u u K P

u u

PS OUT _ maxmax

BULK _ min PS OUT _ max

N VD 0.67

V N V

u

� u

� �BULK _max

PS _mindera DS _ SR OUT _max spike

VN 4.68

1 K V V V

� u � �





• Kdera is the GaN voltage derating

• VDS_GaN is the maximum GaN drain-to-source voltage rating

• VBULK_max is the maximum bulk voltage

• VOUT_max is the maximum output voltage

(3)

Where:

• VDS_SR is the SR MOSFET drain-to-source voltage rating

• Vspike is the spike voltage on SR MOSFET

A larger turns ratio means a larger main switch duty cycle and smaller secondary RMS current. In thisreference design, the turns ratio is designed as 6 to maintain the minimum secondary RMS current, whichdoes better to the efficiency and thermal.

2.3.1.3 Primary Magnetic Inductance Calculation

After NPS is chosen, the primary magnetic inductance (Lm) can be determined based on the minimumswitching frequency (fSW_min) at the minimum bulk voltage (VBULK_min), maximum duty cycle (Dmax), andmaximum output power (POUT_max). When selecting the minimum switching, consider the impact on full-loadefficiency and EMI filter design.

Calculate the maximum duty cycle and primary inductance using 式 4 and 式 5.

(4)

(5)

2.3.1.4 Auxiliary-to-Secondary Turn Ratio Design

The UCC28780 and both GaN devices are all powered by auxiliary winding at run mode. Two windingsare designed to make sure that VDD will not be lower than the turnoff voltage and to minimize the powerconsumption. 図 3 shows the auxiliary power diagram.

図図 3. Auxiliary Power Diagram

The Na1 winding is designed to power the devices at 5-V and 9-V outputs. Considering the voltagederating at a light load, there should be enough margin on VDD_min. Then at a 9-V output, the VDD is equalto the TVS diode voltage of 18 V. Na1 must stay a small value to decrease the power consumption on thetransistor.


FDRBleed

PS OUT _ maxclamp

residual

tR

N VC ln

V

u§ ·

¨ ¸© ¹

SWm BULK _ min

m

Ci V

L� � u

OUT _ max 2m m

m SW _ min

2 Pi i

L f� �u

�K u u

2m m

clamp _ maxk PS OUT _ min

2L i1C

L 3 N V�

uS u u

a2 _ max DD _ max

S

N 0.9V1.35

N 20

a2 _ min DD _ min

S

N 1.8V1.26

N 15

a1_ min DD _ min

S

N 1.8V3.78

N 5





The Na2 winding is designed to power the devices at 15-V and 20-V outputs. Calculate the auxiliary-to-secondary turn ratio using 式 6, 式 7, and 式 8.

(6)

(7)

(8)

2.3.1.5 Clamp Capacitor Calculation

Consider the design trade-off between conduction loss reduction and turnoff switching loss of the high-side switching device (QH). A higher clamp capacitor (Cclamp) results in less RMS current flowing throughthe transformer windings and switching devices; therefore, the conduction loss can be reduced. However,a higher Cclamp design results in QH turning off before the clamp current returns to zero. The condition ofnon-ZCS increases the turnoff switching loss of QH. Therefore, Cclamp needs to be fine tuned based on theloss attribution. For best results, design the resonance between leakage inductance (Lk) and Cclamp to becompleted by the time between resonant current is zero and QH is turned off. In this setup, thedemagnetization time must be equal to around three quarters of the resonant period. Use 式 9, 式 10, and式 11 to design Cclamp for obtaining ZCS at a minimum bulk voltage, minimum output voltage, and full load.A low-ESR clamp capacitor is required to minimize the conduction loss.

(9)

(10)

(11)

2.3.1.6 Bleed Resistor Calculation

A large bleed resistor (RBleed) is used to discharge clamp capacitor voltage to a residual voltage (Vresidual)during the 1.44-s fault delay recovery time (tFDR). After the converter recovers from the fault mode, thelower Vresidual reduces the maximum current flowing through QH and SR within their respective safeoperating areas, even if the output voltage is shorted. The target Vresidual can be calculated based on themaximum pulse current of QH or the SR current reflected to the primary side, depending on which is lower.

(12)

2.3.1.7 Output Capacitor Calculation

Output capacitance (COUT) is determined by evaluating several factors and choosing the largest of theresults.1. The minimum output capacitor value must be enough to meet transient specification of output voltage

due to a given load step until the voltage-control loop can respond to restore regulation.

Where:


� �REF

CTL3REF REF REF REF

D1 D2 CTL2 CTL1

VR

15 V V V V VR R R R

�

� � �

� �REF

CTL1REF REF REF

D1 D2 CTL2

VR

15 V V V VR R R

�

� �

� �REF

CTL2REF REF

D1 D2

VR

9 V V VR R

�

�

� �max SW _ min m SW pk pkCo _ max

OUT _ max

2 1 D f L C VR

I

�� u Su u

S u

load transOUT _ min

trans _ max

I tC

V

' u '

'

� � kresidual max_ QH max_ SRclamp

LV min i , i

C u





• ΔIload is maximum load-step magnitude for transient response

• ΔVtrans_max is the maximum transient voltage deviation for transient response

• Δttrans is the transient response time2. The maximum ESR of output capacitor is often limited by the maximum output peak-to-peak voltage

ripple (Vpk-pk), where the worst-case output ripple is considered at maximum load (IOUT_max). If the high-frequency switching ripple at the output is mainly dominated by the ESR ripple, a sinusoidalapproximation of the secondary current waveform of the ACF is made to calculate the ESRrequirement based on the target output ripple specification.

(13)

(14)

(15)

2.3.2 USB-PD Design

The USB-PD source controller TPS25740B is used in this reference design to achieve USB-PD 2.0functions. The device can control an external voltage regulator by three digital PINs (CTL1, CTL2, andCTL3) to select the voltage from the power supply based on the voltage requested by the attached sink.表 3 summarizes the control relationship between the CTL1, CTL2, and CTL3 statuses and VBUS.

表表 3. PD Control Relationship

VOLTAGE CONTAINED IN PDO REQUESTED BY UFP CTL3 STATE CTL2 STATE CLT1 STATE5 V High-z High-z High-z9 V High-z Low High-z15 V High-z Low Low20 V Low Low Low

The USB-PD control resistors can be calculated from 式 16, 式 17, and 式 18 based on 表 3.

(16)

(17)

(18)


www.tij.co.jp Hardware, Software, Testing Requirements, and Test Results




3 Hardware, Software, Testing Requirements, and Test Results

3.1 Required Hardware and Software

3.1.1 Hardware

• Isolated AC source

• Single-phase power analyzer

• Digital oscilloscope

• Multimeters

• Electronic load

• USB Type-C™ UFP Load Board PMP20413

3.2 Testing and Results

3.2.1 Test Setup1. Connect input terminals of the reference board to the AC power source.2. Connect output terminals to the PMP20413 input terminals.3. Connect the PMP20413 output terminals to electronic load, maintaining correct polarity.4. Set a minimum load of about 0 A and minimum voltage of 25 V.5. Gradually increase the input voltage from 0 V to turn on voltage of 75-V AC.6. Observe that the output voltage across the load terminals has risen to about 5 V.7. Increase the load to maximum load smoothly and observe the switching waveforms.8. Select different output voltages through the PMP20413 device.9. Increase the load to maximum load smoothly and observe the switching waveforms.10. Compare these results with those presented in the design guide.

3.2.2 Test Results

3.2.2.1 Efficiency

表 4 through 表 11 list the efficiency data of the different voltages.

表表 4. 5 V at 115-V AC/60 Hz

OUTPUT VOLTAGE OUTPUT CURRENT INPUT POWER EFFICIENCY5.008 0.75 4.6 81.75.006 1.53 8.9 86.15.004 2.25 12.8 88.05.002 3 16.8 89.3

表表 5. 5 V at 230-V AC/50 Hz

OUTPUT VOLTAGE OUTPUT CURRENT INPUT POWER EFFICIENCY5.004 0.75 5 75.15.002 1.5 8.9 84.3

5 2.25 12.9 87.25 3 16.6 90.4


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表表 6. 9 V at 115-V AC/60 Hz

OUTPUT VOLTAGE OUTPUT CURRENT INPUT POWER EFFICIENCY9.02 0.75 8 84.69.02 1.5 15 90.29.02 2.25 22 92.39.01 3 29 93.2

表表 7. 9 V at 230-V AC/50 Hz

OUTPUT VOLTAGE OUTPUT CURRENT INPUT POWER EFFICIENCY9.02 0.75 8.1 83.59.01 1.5 15.3 88.39.01 2.25 22.4 90.59.01 3 29 93.2

表表 8. 15 V at 115-V AC/60 Hz


表表 9. 15 V at 230-V AC/50 Hz


表表 10. 20 V at 115-V AC/60 Hz

OUTPUT VOLTAGE OUTPUT CURRENT INPUT POWER EFFICIENCY19.85 0.82 17.8 91.419.84 1.63 34.9 92.719.83 2.44 51.8 93.419.83 3.25 68.9 93.5

表表 11. 20 V at 230-V AC/50 Hz

OUTPUT VOLTAGE OUTPUT CURRENT INPUT POWER EFFICIENCY19.83 0.82 18.1 89.819.81 1.63 35.3 91.519.8 2.44 52 92.919.8 3.25 68.5 94.0


Load

Out

put V

olta

ge

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.00

5

10

15

20

25

D003

5 V9 V

15 V20 V

Load

Effi

cien

cy (�

)

0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.9574

76

78

80

82

84

86

88

90

92

94

D005

5 VOUT9 VOUT15 VOUT20 VOUT

Load

Effi

cien

cy (�

)

0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.9581.5

82.5

83.5

84.5

85.5

86.5

87.5

88.5

89.5

90.5

91.5

92.5

93.5

D004

5 VOUT9 VOUT15 VOUT20 VOUT





図 4 and 図 5 show the efficiency curves.

図図 4. Efficiency Curve at 115-V AC 図図 5. Efficiency Curve at 230-V AC

3.2.2.2 Standby Power Loss

表表 12. Standby Power Loss

VinTIDA-01622

INPUT POWER LOSS CoC V5 TIER 2 DOE_VI

115-V AC/60 Hz 35 mW75 mW 150 mW

230-V AC/50 Hz 45 mW

3.2.2.3 Load Regulation

図 6 shows the load regulation at 115-V AC/60 Hz.

図図 6. Load Regulation






3.2.2.4 Output Voltage Transitions

3.2.2.4.1 Start-up

図図 7. Start-up Waveform at 115-V AC and No Load

3.2.2.4.2 5 V to 9 V

図図 8. 5-V to 9-V Transition at 115-V AC and No Load






3.2.2.4.3 9 V at 15 V


3.2.2.4.4 15 V to 20 V







3.2.2.4.5 5 V to 15 V


3.2.2.4.6 5 V to 20 V







3.2.2.4.7 9 V to 20 V


3.2.2.5 Output Voltage Ripple

図図 14. 115-V AC/60-Hz Input, 5-V/3-A Output






図図 17. 115-V AC/60-Hz Input, 20-V/3.25-A Output

3.2.2.6 Loop Gain

図図 18. Loop Gain at 115-V AC/60-Hz Input, 20-V/3.25-A Output






図図 19. Loop Gain at 230-V AC/50-Hz Input, 20-V/3.25-A Output

3.2.2.7 CE Test Results

図図 20. 115-V AC Input, 20-V/3.25-A Output

表表 13. Final Result for 115-V AC Input, 20-V/3.25-A Output

FREQ(MHz)

QUASIPEAK(dBµV)

AVERAGE(dBµV)

LIMIT(dBµV)

MARGIN(dB)

MEAS TIME(ms)

BANDWIDTH(kHz) LINE FILTER

CORR(dB)

0.280500 51.81 — 60.80 8.99 1000.0 9.000 L1 ON 19.62.483250 46.66 — 56.00 9.34 1000.0 9.000 L1 ON 19.63.099750 48.25 — 56.00 7.75 1000.0 9.000 L1 ON 19.63.653250 48.39 — 56.00 7.61 1000.0 9.000 L1 ON 19.6






図図 21. 230-V AC Input, 20-V/3.25-A Output

表表 14. Final Result for 230-V AC Input, 20-V/3.25-A Output

FREQ(MHz)

QUASIPEAK(dBµV)

AVERAGE(dBµV)

LIMIT(dBµV)

MARGIN(dB)

MEAS TIME(ms)

BANDWIDTH(kHz) LINE FILTER

CORR(dB)

0.368250 — 41.30 48.54 7.24 1000.0 9.000 N ON 19.60.370500 48.52 — 58.49 9.97 1000.0 9.000 N ON 19.60.737250 — 45.21 46.00 0.79 1000.0 9.000 N ON 19.60.739500 53.59 — 56.00 2.41 1000.0 9.000 N ON 19.61.106250 — 42.36 46.00 3.64 1000.0 9.000 N ON 19.61.844250 — 40.59 46.00 5.41 1000.0 9.000 N ON 19.61.844250 53.44 — 56.00 2.56 1000.0 9.000 N ON 19.62.215500 — 40.21 46.00 5.79 1000.0 9.000 N ON 19.62.217750 52.50 — 56.00 3.50 1000.0 9.000 N ON 19.6

3.2.2.8 Thermal Image

図図 22. Thermal Image at 90-V AC/60-Hz Input, 20-V/3.25-A Output


Design Files www.tij.co.jp




4 Design Files

4.1 Schematics

To download the schematics, see the design files at TIDA-01622.

4.2 Bill of Materials

To download the bill of materials (BOM), see the design files at TIDA-01622.

4.3 PCB Layout Recommendations

4.3.1 Layout Prints

To download the layer plots, see the design files at TIDA-01622.

4.4 Altium Project

To download the Altium project files, see the design files at TIDA-01622.

4.5 Gerber Files

To download the Gerber files, see the design files at TIDA-01622.

4.6 Assembly Drawings

To download the assembly drawings, see the design files at TIDA-01622.

5 Software Files

To download the software files, see the design files at TIDA-01622.

6 Related Documentation

This reference design did not use any documentation.

6.1 商商標標E2E, NexFET are trademarks of Texas Instruments.USB Type-C is a trademark of USB Implementers Forum, Inc.すべての商標および登録商標はそれぞれの所有者に帰属します。

http://www.tij.co.jphttp://www-s.ti.com/sc/techlit/TIDUDW2.pdfhttp://www.ti.com/tool/TIDA-01622http://www.ti.com/tool/TIDA-01622http://www.ti.com/tool/TIDA-01622http://www.ti.com/tool/TIDA-01622http://www.ti.com/tool/TIDA-01622http://www.ti.com/tool/TIDA-01622http://www.ti.com/tool/TIDA-01622

www.tij.co.jp 改訂履歴



Revision History

改改訂訂履履歴歴資料番号末尾の英字は改訂を表しています。その改訂履歴は英語版に準じています。

Revision A (August 2018) かからら Revision B にに変変更更 ........................................................................................................... Page

• ノート PC 向け電源アダプタの設計、モバイル向け充電器の設計、その他の AC/DC アダプタ/電源を「アプリケーション」に追加. 1

2018年年2月月発発行行ののももののかからら更更新新 ............................................................................................................................................... Page

• デザインのタイトル、概要、 2.3でピーク効率を92%から94%に変更 ................................................................... 1• 特長および

表 1で、20mmを18.4mmに変更 ......................................................................................................... 1• 表 4 追加 .................................................................................................................................. 11• 表 5 追加 .................................................................................................................................. 11• 表 6 追加 .................................................................................................................................. 11• 表 7 追加 .................................................................................................................................. 11• 表 8 追加 .................................................................................................................................. 11• 表 9 追加 .................................................................................................................................. 11• 表 10 追加................................................................................................................................. 11• 表 11 追加................................................................................................................................. 11• 表 12 追加................................................................................................................................. 13• 図 4 変更 .................................................................................................................................. 13• 図 5 変更 .................................................................................................................................. 13• 図 18 追加................................................................................................................................. 19• 図 19 追加................................................................................................................................. 20• 図 22 変更................................................................................................................................. 21• 図 23 追加................................................................................................................................. 22• 図 24 追加................................................................................................................................. 22• 図 25 追加................................................................................................................................. 23


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これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションが適用される各種規格や、その他のあらゆる安全性、セキュリティ、またはその他の要件を満たしていることを確実にする責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。TI の製品は、TI の販売条件（www.tij.co.jp/ja-jp/legal/termsofsale.html）、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用されるTI の保証または他の保証の放棄の拡大や変更を意味するものではありません。IMPORTANT NOTICE

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重重要要ななおお知知ららせせとと免免責責事事項項

TI は、技術データと信頼性データ（データシートを含みます）、設計リソース（リファレンス・デザインを含みます）、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。

これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションが適用される各種規格や、その他のあらゆる安全性、セキュリティ、またはその他の要件を満たしていることを確実にする責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。TI の製品は、TI の販売条件（www.tij.co.jp/ja-jp/legal/termsofsale.html）、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用されるTI の保証または他の保証の放棄の拡大や変更を意味するものではありません。IMPORTANT NOTICE

Copyright © 2019, Texas Instruments Incorporated日本語版日本テキサス・インスツルメンツ株式会社

http://www.tij.co.jp/ja-jp/legal/termsofsale.htmlhttp://www.tij.co.jp/

30W/in3、94%効率、65W USB Type-C™ PD AC/DCアダプタのリファレンス・デザイン1 System Description1.1 Key System Specifications

2 System Overview2.1 Block Diagram2.2 Highlighted Products2.2.1 UCC287802.2.2 UCC246122.2.3 TPS25740B2.2.4 ATL4312.2.5 ISO77102.2.6 CSD17578Q3A2.2.7 TPD1E05U06-Q1

2.3 System Design Theory2.3.1 ACF Converter Design2.3.1.1 Bulk Capacitor Calculation2.3.1.2 Transformer Turns Ratio Calculation2.3.1.3 Primary Magnetic Inductance Calculation2.3.1.4 Auxiliary-to-Secondary Turn Ratio Design2.3.1.5 Clamp Capacitor Calculation2.3.1.6 Bleed Resistor Calculation2.3.1.7 Output Capacitor Calculation

2.3.2 USB-PD Design

3 Hardware, Software, Testing Requirements, and Test Results3.1 Required Hardware and Software3.1.1 Hardware

3.2 Testing and Results3.2.1 Test Setup3.2.2 Test Results3.2.2.1 Efficiency3.2.2.2 Standby Power Loss3.2.2.3 Load Regulation3.2.2.4 Output Voltage Transitions3.2.2.5 Output Voltage Ripple3.2.2.6 Loop Gain3.2.2.7 CE Test Results3.2.2.8 Thermal Image

4 Design Files4.1 Schematics4.2 Bill of Materials4.3 PCB Layout Recommendations4.3.1 Layout Prints

4.4 Altium Project4.5 Gerber Files4.6 Assembly Drawings

5 Software Files6 Related Documentation6.1 商標

改訂履歴Important Notice

デザイン・ガイド: TIDA-01622 30W/in3 94%効率、65W USB Type … · 2019. 7. 12. ·...

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