Embedded System Lab.

Embedded System Lab.

Sungmin Koosm.koo1989@gmail.com

“NVM Duet: Unified Working Memory and Persistent Store

Architecture”

Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang, Shun-Chih Yu, Cheng-

Yuan Michael Wang

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Index

Background Introduction Data Consistency vs. Bank-Level Parallelism Data Durability vs. Write Speed NVM Duet Evaluation

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Background Structure of PCM(Phase Chang Memory) cell

2-states Amorphous state(high resistance, 0) Polycrystalline state(low resistance, 1)

Read and Write mechanisms of PCM RESET(writing bit “0”)

Heat the phase change material Short latency High power consumption

SET(writing bit “1”) Sustained low voltage pulse Long latency Low power consumption

To read the state of phase change material, a low enough voltage pulse is applied to the material.

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Background MLC PCM

The large resistance difference between the amorphous state and the polycrystalline state makes it possible to store multiple bits per PCM cell

‘Iterative programming’ technique

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Background Characteristics Comparison

PCM memory system architectures

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Introduction NVM technologies have gained a lot of attention recently.

Non-volatile, byte-addressability SCM blurs the line between working memory and persistent store.

Enable the construction of large-scale working memory High density, scalability, MLC technique

Alternative to conventional persistent store. can be connected to CPUs via a direct memory access path Ordinary load, store instruction(previous study)

SCM will play the role of both working memory and persistent store at the same time.

NVM duet Guarantee consistency and durability not require advance partitioning of PCM resources between persistent

store and working memory All the management is transparent to applications.

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Data Consistency vs. Bank-Level Parallel-ism Achieve consistency mechanism

Persistent update mechanisms at the software level Journaling, shadow update

Enforcing ordering writes at the hardware level

Consistent update

Issues write requests to create N3’ and N4’ Issuing write requests to create N1’, which points to N2, N3’, and N4’ Issue a barrier

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Data Consistency vs. Bank-Level Parallel-ism

Figure 3(a) displays a schedule that respects the barriers. Figure 3(b) shows if the barriers were not present. Figure 3(c) have knowledge of the use case for each write

A, B, and G belong to working memory The others belong to persistent store

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Data Durability vs. Write Speed

The write speed can be estimated based on the target band allocation

A small R is used for a narrow target band to prevent the iterative write from completely missing the target band.

Resistance drift PCM’s limited non-volatility The resistance of PCM

cells drifts upward Occur data losses

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NVM Duet HW/SW Interface

Built on recently proposed software framework(NV-heap, Mnemosyne) Programmers declare persistent data in the PCM main memory(keywords) Link persistent data to a reserved virtual address space (PersistSpace)

AllocMap(one bit each PCM frame) Convey to the memory controller the OS’s knowledge of the use case of each

piece of data

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NVM Duet Duet Scheduler

fully exploit the bank-level parallelism Rule 1: Writes to working memory can be scheduled regardless of barri-

ers. Rule 2: Writes to persistent store are prioritized over writes to working

memory if a barrier is pending in the memory controller.

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NVM Duet Dual-Retention PCM Architecture

Dual-Retention PCM chips Provide two access modes with different retention guarantees Command interface(mode signal)

Smart Refresh Remove unnecessary refreshing operation

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Evaluation

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Evaluation

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References Haros Volos, Andres Jaan Tack, and Michael M.Swift.

Mnemosyne: Lightweight Persistent Memory.

Ju-Young Jung and Sangyeun Cho. Memorage: Emerging Persistent RAM based Malleable Main Memory and Storage Architecture.

유승훈 , 이은지 , 반효경 . Design and Implementation of a Write Effi-cient Journaling File System for Phase Change Memory.

Eunji Lee, Hyokyung Bahn, and Sam H. Noh. Unioning of the Buffer Cache and Journaling Layers with Non-volatile Memory.

Fei Xia, Jin Xiong, and Ning-Hui Sun. A survey of Phase Change Memory System.

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Q&A